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vhdl 14-3-08

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					            SATHYABAMA UNIVERSITY
              (Established under section 3 of UGC Act, 1956)

Course & Branch: B.E .- ECE
Title of the paper: Programming in VLSI
Semester: VII                                          Max. Marks: 80
Sub.Code: 413704                                       Time: 3 Hours
Date: 14-03-2008                                       Session: FN
                              PART – A                    (10 x 2 = 20)
                         Answer All the Questions
1.   What are the different types of design units?

2.   Differentiate signals and variables.

3.   What do you mean by component instantiation and what          are
     the two ways for the association of formals and actual.

4.   Which function is used if two components drive a common
     signal?

5.   What are the main reasons that configurations are used in
     VHDL?

6.   What do you mean by incomplete binding information?

7.   Differentiate subprogram overloading and operator
     overloading.

8.   What are the two main forms of USE clause?

9.   What do you mean by shared variables?

10. What are the three main purposes for writing test bench?
                        PART – B               (5 x 12 = 60)
                      Answer All the Questions

11. Explain in detail the differentiate types of operators in VHDL.
                                  (or)
12. With an example explain inertial delay and Transport delay.

13. Write a VHDL program for a 9 bit parity generator circuit using
    structural modeling.
                               (or)
14. Write a VHDL program for a 4 bit binary up-down counter using
    behavioral modeling whose inputs are clear, clock,    control for
    up and down.

15. Explain in detail the two ways of performing the binding.
                                (or)
16. Write a VHDL program that describes a 4*1 multiplexer       using
    block statement.

17. Explain in detail the two ways of subprograms.
                                 (or)
18. Discuss in detail about the design libraries.

19. Write a VHDL program to design a circuit that counts the
    number of positive edge clock pulses.
                                (or)
20. Write a VHDL program for a generic model of a divide by 2*N
    clock generator.

				
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