SATHYABAMA UNIVERSITY (Established under section 3 of UGC Act, 1956) Course & Branch: M.Tech - VLSI Title of the paper: Programming in HDL Semester: II Max. Marks: 80 Sub.Code: 782202 Time: 3 Hours Date: 11-12-2008 Session: FN PART – A (6 x 5 = 30) Answer All the Questions 1. What do you mean by oblivious simulation and event-driven simulation? 2. Discuss about concurrent and sequential assignments. 3. Mention different data types used in VHDL with examples. 4. Give VHDL description for an inverter. 5. What are the top-down wiring components used to model the HDL? 6. Explain the configuration declaration in an architectural body of VHDL language. PART – B (5 x 10 = 50) Answer All the Questions 7. Explain different modeling styles used for an architectural body of the system. (or) 8. Discuss the basic elements of VHDL language in detail. 9. What are the various categories of pre-defined operators available in the VHDL language? Explain them. (or) 10. Write VHDL descriptions for a two input NOR gate and an XOR gate. Use 4ns and 7ns delays for NOR and XOR gates respectively. 11. Show how certain types of information can be passed into an entity using Generics. (or) 12. Write short notes on (a) Package declaration (b) Display procedure for formatted ASCIII/O operations. 13. Discuss the basic concepts and language elements of verilog HDL in detail. (or) 14. With examples, explain various expressions, operands and operators used in verilog HDL. 15. Explain about the Data flow modeling of HDL in verilog with examples. (or) 16. Discuss about the Structural modeling of HDL in verilog with examples.