Important question VHDL by smbram1

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									PROGRAMMING IN VHDL

                 SUGGESTED IMPORTANT PART- B QUESTION

UNIT-1 INTRODUCTION OF VHDL

1) Explain in detail about the basic Terminology and capabilities of VHDL .

            Ans =>Pg no: 9,10,11,12 in book 1

2) Explain in detail about language elements of VHDL.

      Ans =>Pg no: 34 to 60 in book 1(Briefly explain only two points in each topic)

3) Explain in detail about different operators.

                Ans =>Pg no: 61-66 in book 1

4) Enumerate the different signal assignment in VHDL?

          Ans =>Pg no: 83 to 89 &103 to 107 in book 1

5) Explain the different delay mechanism.

Ans =>Pg no:90,91 & 107 to 109 in book 1.




UNIT- 2 STYLES OF MODELLING IN VHDL

1) Explain in detail about process statement with example.

       Ans =>Pg. no: 71 to 89 in book 1.

        (Briefly explain only two points)

2) Explain in detail about conditional statement with example.

       Ans=> Pg. no: 74,75 in book 1.

3) Enumerate behavioural modelling with example.

       Ans=> Pg. no: 67 to 71 in book 1.

4) Enumerate dataflow modelling with example.

        Ans=> Pg. no: 16, 17, 18 and 103 to 124 in book 1.

5) Enumerate structural modelling with example.

       Ans=> Pg. no: 14, 15, 16 and 125 to 137 in book 1.
6) Explain different component declaration and component instantiation with
example.

       Ans=> Pg. no: 126,127,128 & 128 to132 in book 1.




UNIT-3 ADVANCED FEATURES AND SUBPROGRAMS

1) Explain in detail generic configuration specification and declaration.

       Ans=> Pg. no: 139 to 155 in book 1.

       (Briefly explain any two points)

2) Mention the types of guarded signals?

       Ans=> Pg. no: 208 to 212 in book 1.

3) Explain the model simulation in VHDL with an example.

       Ans=> Pg. no: 237 to 240 in book 1.

4) What is subprogram with examples.

       Ans=> Pg. no: 163 to 172 in book 1

5) Explain in detail subprogram overloading.

  Ans => Pg. no: 173 to 176 in book 1

6) Explain operator overloading.

       Ans=> Pg. no: 176 to 178 in book 1.

UNIT-4 PACKAGES AND LIBRARIES

1)Explain in detail package body and package declaration.

       Ans=> Pg no:183 to 185 & 185,186 in book 1.

2) Explain in detail design libraries.

      Ans=> Pg no:187,188 in book 1.



3)Briefly explain modelling synchronous logic?

       Ans=> Pg no:277 to 282 in book 1
4) Explain moore fsm in VHDL.

       Ans=> Pg no:288,289,290 in book 1.

5) Explain mealy fsm in VHDL.

       Ans=> Pg no:290,291,292 in book 1.



UNIT-5 INTRODUCTION TO VERILOG HDL

1)Explain in detail data types of operators.

    Ans=> Pg. no: 36 to 47, 50 to 54,55 to 68 in book 1

2) Explain in detail about behavioural modelling.

       Ans=> Pg. no: 9 to 11 in book 1

3) Explain in structural modelling .

            Ans=> Pg. no:14 to 16 in book 1

4) Explain dataflow modelling.

       Ans=> Pg. no: 14 to 11 in book 1

5) Program using three models

  Ans=> REFER CLASS NOTES

								
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