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DEPARTMENT OFECE                                         LAB CODE: 613751
CO-ORDINATORS NAME: Mr. T. VINO, Ms. M. S. SHEEBA        LAB NAME: VLSI DESIGN LAB

613751 – VLSI DESIGN LABORATORY

LIST OF EXPERIMENTS

SIMULATION AND SYNTHESIS THE CIRCUITS IN VHDL

1. Verification of Logic Gates
4. Encoder and Decoder
5. Multiplexer and Demultiplexer
6. Magnitude Comparator
7. Code Converters
8. Flip-Flops
9. Shift Registers
10.        Counters

Page 1 of 20
DEPARTMENT OFECE                                                 LAB CODE: 613751
CO-ORDINATORS NAME: Mr. T. VINO, Ms. M. S. SHEEBA                LAB NAME: VLSI DESIGN LAB

1. VERIFICATION OF LOGIC GATES

AIM:

To develop VHDL code for the verification of Logic Gates, simulate it and verify the output using
XILINX ISE 7.1i

ALGORITHM:

 Declare the name of design, entity and architecture body.

 Write the source code in VHDL.

 Compile the code and check for the errors.

 Simulate the program and verify the waveform using any of the simulators ISE or MODELSIM

 Verify the output for all the combination of the input values.

LOGIC DIAGRAM & TRUTH TABLE:

AND GATE:

LOGIC DIAGRAM:                                                                   TRUTH TABLE:

Input A      Input B      Output Y
0           0            0
0           1            0
1           0            0
y<= a and b;                                            1           1            1
OR GATE:

LOGIC DIAGRAM:                                                              TRUTH TABLE:

Input A      Input B     Output Y
0           0            0
0           1            1
y<= a or b;                                                  1           0            1
1           1            1

NOT GATE:
Page 2 of 20
DEPARTMENT OFECE                                         LAB CODE: 613751
CO-ORDINATORS NAME: Mr. T. VINO, Ms. M. S. SHEEBA        LAB NAME: VLSI DESIGN LAB

LOGIC DIAGRAM:                                             TRUTH TABLE:

Input A Output Y
0               1
1               0
y<= not a;

NAND GATE:
LOGIC DIAGRAM:                                                  TRUTH TABLE:

Input A Input B Output Y
0       0           1
0       1           1
y<= a nand b;                                       1       0           1
1       1           0
NOR GATE:
LOGIC DIAGRAM:                                               TRUTH TABLE:

Input A Input B Output C
0          0           1
0          1           0

y<= a nor b;                                        1          0           0
1          1           0
XOR GATE:

LOGIC DIAGRAM:                                                      TRUTH TABLE:

Input A Input B Output Y
0           0           0
y<= a xor b;                                            0           1           1
1           0           1
XNOR GATE:                                                      1           1           0

LOGIC DIAGRAM:                                                  TRUTH TABLE:

Input A Input B Output Y
0           0           1
0           1           0
1           0           0
1           1           1
y<= a xnor b;

Page 3 of 20
DEPARTMENT OFECE                                                  LAB CODE: 613751
CO-ORDINATORS NAME: Mr. T. VINO, Ms. M. S. SHEEBA                LAB NAME: VLSI DESIGN LAB

RESULT:

Thus the VHDL codes for the different logic gates were written, simulated. Synthesized and the
outputs verified

AIM:

To develop VHDL code for Half adder, Full adder, Half subtractor and Full subtractor simulate it
and verify the output using XILINX ISE 7.1i

ALGORITHM:

 Declare the name of design, entity and architecture body.

 Write the source code in VHDL.

 Compile the code and check for the errors.

 Simulate the program and verify the waveform using any of the simulators ISE or MODELSIM

 Verify the output for all the combination of the input values.

LOGIC DIAGRAM & TRUTH TABLE:

Input A   Input B   Output SUM    Output CARRY
0         0            0              0
0         1            1              0
1         0            1              0
1         1            1              1

Page 4 of 20
DEPARTMENT OFECE                                         LAB CODE: 613751
CO-ORDINATORS NAME: Mr. T. VINO, Ms. M. S. SHEEBA        LAB NAME: VLSI DESIGN LAB

LOGIC DIAGRAM:

TRUTH TABLE:

Input A        Input B          Input C           Output SUM        Output CARRY
0              0                 0                  0                    0
0              0                 1                  1                    0
0              1                 0                  1                    0
0              1                 1                  0                    1
1              0                 0                  1                    0
1              0                 1                  0                    1
1              1                 0                  0                    1
1              1                 1                  1                    1

HALF SUBTRACTOR:                                          TRUTH TABLE:

Input A    Input B   DIFF   BORROW
0       0        0       0
0       1        1       1
1       0        1       0
1       1        0       0

Page 5 of 20
DEPARTMENT OFECE                                                LAB CODE: 613751
CO-ORDINATORS NAME: Mr. T. VINO, Ms. M. S. SHEEBA               LAB NAME: VLSI DESIGN LAB

FULL SUBTRACTOR:

LOGIC DIAGRAM:

TRUTH TABLE:

Input A      Input B       Input C         DIFF       BORROW
0            0              0             0             0
0            0              1             1             1
0            1              0             1             1
0            1              1             0             1
1            0              0             1             0
1            0              1             0             0
1            1              0             0             0
1            1              1             1             1

RESULT:

Thus the VHDL codes for Half adder, Full adder, Half subtractor and Full subtractor were written,
simulated, synthesized and the outputs verified.

Page 6 of 20
DEPARTMENT OFECE                                                 LAB CODE: 613751
CO-ORDINATORS NAME: Mr. T. VINO, Ms. M. S. SHEEBA               LAB NAME: VLSI DESIGN LAB

AIM:

To develop source code for ripple carry adder circuit by using VHDL and obtain the simulation,
synthesis using XILINX ISE 7.1i

ALGORITHM:

 Declare the name of design, entity and architecture body.

 Write the source code in VHDL.

 Compile the code and check for the errors.

 Simulate the program and verify the waveform using any of the simulators ISE or MODELSIM

 Verify the output for all the combination of the input values.

LOGIC DIAGRAM & TRUTH TABLE:

Page 7 of 20
DEPARTMENT OFECE                                                      LAB CODE: 613751
CO-ORDINATORS NAME: Mr. T. VINO, Ms. M. S. SHEEBA                     LAB NAME: VLSI DESIGN LAB

TRUTH TABLE:

INPUT                                                   OUTPUT

A0    A1     A2     A3     B0       B1     B2       B3         CIN      S0     S1     S2     S3   COUT

0     0      0      0      0       0       0        0         0        0       0     0      0     0

0     0      0      1      0       0       0        1         0        0       0     1      0     0

0     0      1      0      0       0       1        0         0        0       1     0      0     0

0     0      1      1      0       0       1        1         0        0       1     1      0     0

0     1      0      0      0       1       0        1         0        1       0     1      0     0

0     1      0      1      0       1       1        1         0        1       1     1      1     0

0     1      1      0      1       1       1        0         1        1       1     0      1     1

1     1      1      1      1       1       1        1         1        1       1     1      1     1

RESULT:
Thus the VHDL codes for Ripple Carry Adder was written, simulated, synthesized and the outputs
verified.

4. ENCODER AND DECODER

AIM:

To develop VHDL code for Encoder (8 x 3) and Decoder (2 x 4), simulate it and verify the output
using XILINX ISE 7.1i

ALGORITHM:

 Declare the name of design, entity and architecture body.

 Write the source code in VHDL.

 Compile the code and check for the errors.

 Simulate the program and verify the waveform using any of the simulators ISE or MODELSIM.

 Verify the output for all the combination of the input values.

Page 8 of 20
DEPARTMENT OFECE                                         LAB CODE: 613751
CO-ORDINATORS NAME: Mr. T. VINO, Ms. M. S. SHEEBA        LAB NAME: VLSI DESIGN LAB

LOGIC DIAGRAM & TRUTH TABLE:

ENCODER:

LOGIC DIAGRAM:

TRUTH TABLE:

D0     D1     D2    D3      D3     D4    D5        D6    X         Y         Z
1      0     0      0      0      0      0        0     0         0          0
0      1     0      0      0      0      0        0     0         0          1
0      0     1      0      0      0      0        0     0         1          0
0      0     0      1      0      0      0        0     0         1          1
0      0     0      0      1      0      0        0     1         0          0
0      0     0      0      0      1      0        0     1         0          1
0      0     0      0      0      0      1        0     1         1          0
0      0     0      0      0      0      0        1     1         1          1

Page 9 of 20
DEPARTMENT OFECE                                             LAB CODE: 613751
CO-ORDINATORS NAME: Mr. T. VINO, Ms. M. S. SHEEBA            LAB NAME: VLSI DESIGN LAB

DECORDER:

LOGIC DIAGRAM:

TRUTH TABLE:

A          B         Enable        Z(0)            Z(1)         Z(2)          Z(3)

0          0          1             0              1             1             1

0          1          1             1              0             1             1

1          0          1             1              1             0             1

1          1          1             1              1             1             0

RESULT:

Thus the VHDL codes for encoder and decoder were written, simulated, synthesized and the
outputs verified.

Page 10 of 20
DEPARTMENT OFECE                                                  LAB CODE: 613751
CO-ORDINATORS NAME: Mr. T. VINO, Ms. M. S. SHEEBA                LAB NAME: VLSI DESIGN LAB

5. MULTIPLEXER AND DE-MULTIPLEXER

AIM:

To develop VHDL code for Multiplexer (4 x 1) and De-Multiplexer (1 x 4), simulate it and verify the
output using XILINX ISE 7.1i

ALGORITHM:

 Declare the name of design, entity and architecture body.

 Write the source code in VHDL.

 Compile the code and check for the errors.

 Simulate the program and verify the waveform using any of the simulators ISE or MODELSIM

 Verify the output for all the combination of the input values.

LOGIC DIAGRAM & TRUTH TABLE:

MULTIPLEXER:

TRUTH TABLE:
SELECT INPUT
S0             S1          OUTPUT Y
0              0              D(0)
0              1              D(1)
1              0              D(2)
1              1              D(3)

Page 11 of 20
DEPARTMENT OFECE                                              LAB CODE: 613751
CO-ORDINATORS NAME: Mr. T. VINO, Ms. M. S. SHEEBA             LAB NAME: VLSI DESIGN LAB

DE-MULTIPLEXER:
LOGIC DIAGRAM:

TRUTH TABLE:

INPUT                                     OUTPUT

Din        S0          S1          Y0          Y1            Y2       Y3
1          0           0           1           0            0         0

1          0           1           0           1            0         0

1          1           0           0           0            1         0

1          1           1           0           0            0         1

RESULT:

Thus the VHDL codes for multiplexer and de-multiplexer were written, simulated, synthesized and
the outputs verified.
6. CODE CONVERTERS

AIM:

To develop VHDL code for Code Converters, simulate it and verify the output using XILINX ISE
7.1i

ALGORITHM:
Page 12 of 20
DEPARTMENT OFECE                                                LAB CODE: 613751
CO-ORDINATORS NAME: Mr. T. VINO, Ms. M. S. SHEEBA              LAB NAME: VLSI DESIGN LAB

 Declare the name of design, entity and architecture body.

 Write the source code in VHDL.

 Compile the code and check for the errors.

 Simulate the program and verify the waveform using any of the simulators ISE or MODELSIM

 Verify the output for all the combination of the input values.

CODE CONVERTER (BINARY TO GRAY): LOGIC DIAGRAM:

TRUTH TABLE:

BINARY                                            GRAY
B3        B2          B1           B0           G3          G2              G1   G0
0          0            0           0           0            0              0     0
0          0            0           1           0            0              0     1
0          0            1           0           0            0              1     1
0          0            1           1           0            0              1     0
0          1            0           0           0            1              1     0
0          1            0           1           0            1              1     1
0          1            1           0           0            1              0     1
0          1            1           1           0            1              0     0
1          0            0           0           1            1              0     0
1          0            0           1           1            1              0     1
1          0            1           0           1            1              1     1
1          0            1           1           1            1              1     0
1          1            0           0           1            0              1     0
1          1            0           1           1            0              1     1
1          1            1           0           1            0              0     1

1          1            1           1           1            0              0     0

Page 13 of 20
DEPARTMENT OFECE                                                  LAB CODE: 613751
CO-ORDINATORS NAME: Mr. T. VINO, Ms. M. S. SHEEBA                 LAB NAME: VLSI DESIGN LAB

CODE CONVERTER (GRAY TO BCD):

LOGIC DIAGRAM:

TRUTH TABLE:

GRAY                                                BCD
G3             G2           G1          G0             B0         B2            B1          B0
0             0            0           0             0           0            0            0
0             0            0           1             1           0            0            1
0             0            1           1             0           0            1            0
0             0            1           0             1           0            1            1
0             1            1           0             0           1            0            0
0             1            1           1             1           1            0            1
0             1            0           1             0           1            1            0
0             1            0           0             1           1            1            1
1             1            0           0             0           0            0            0
1             1            0           1             1           0            0            1

RESULT:

Thus the VHDL codes for Code Converters were written, simulated synthesized and the outputs
verified.
7. MAGNITUDE COMPARATOR

AIM:

To develop VHDL code for Magnitude Comparator, simulate it and verify the output using XILINX
ISE 7.1i

ALGORITHM:
Page 14 of 20
DEPARTMENT OFECE                                                  LAB CODE: 613751
CO-ORDINATORS NAME: Mr. T. VINO, Ms. M. S. SHEEBA                LAB NAME: VLSI DESIGN LAB

 Declare the name of design, entity and architecture body.

 Write the source code in VHDL.

 Compile the code and check for the errors.

 Simulate the program and verify the waveform using any of the simulators ISE or MODELSIM

 Verify the output for all the combination of the input values.

LOGIC DIAGRAM & TRUTH TABLE:

I/P       X       Y         Z

a=b        1       0         0

a<b        0       1         0

a>b        0       0         1

RESULT:

Thus the VHDL codes for Magnitude Comparator were written, simulated synthesized and the
outputs verified.

8.   FILP FLOPS

AIM:

To develop VHDL code for Flip Flops (SR, JK, D,T), simulate it and verify the output using XILINX
ISE 7.1i

ALGORITHM:

 Declare the name of design, entity and architecture body.

 Write the source code in VHDL.

 Compile the code and check for the errors.

 Simulate the program and verify the waveform using any of the simulators ISE or MODELSIM

 Verify the output for all the combination of the input values.

LOGIC DIAGRAM & TRUTH TABLE:

Page 15 of 20
DEPARTMENT OFECE                                         LAB CODE: 613751
CO-ORDINATORS NAME: Mr. T. VINO, Ms. M. S. SHEEBA        LAB NAME: VLSI DESIGN LAB

SR FLIP FLOP:                                                            TRUTH TABLE:

Q (t)        S       R            Q (t+1)
0          0       0              0
0          0       1              0
0          1       0              1
0          1       1              X
1          0       0              1
1          0       1              0
1          1       0              1
1          1       1              X

JK FLIP FLOP:
LOGIC DIAGRAM:                                                   TRUTH TABLE:

Q (t)    J       K         Q (t+1)
0       0       0            0
0       0       1            0
0       1       0            1
0       1       1            1
1       0       0            1
1       0       1            0
1       1       0            1
1       1       1            0

D FLIP FLOP:

LOGIC DIAGRAM:                                                                        TRUTH TABLE:

Q(t)         D   Q(t+1)
0           0     0
0           1     1
1           0     0
1           1     1

Page 16 of 20
DEPARTMENT OFECE                                                 LAB CODE: 613751
CO-ORDINATORS NAME: Mr. T. VINO, Ms. M. S. SHEEBA               LAB NAME: VLSI DESIGN LAB

T FLIP FLOP:

LOGIC DIAGRAM:                                                                          TRUTH TABLE:

Q(t)    T    Q(t+1)
0      0         0
0      1         1
1      0         1
1      1         0

RESULT:

Thus the VHDL codes for Flip Flops were written, simulated synthesized and the outputs verified.

9. SHIFT REGISTERS

AIM:
To develop source code for shift register circuit by using VHDL and obtain the simulation,
synthesis using XILINX ISE 7.1i
ALGORITHM:
 Declare the name of design, entity and architecture body.

 Write the source code in VHDL.

 Compile the code and check for the errors.

 Simulate the program and verify the waveform using any of the simulators ISE or MODELSIM

 Verify the output for all the combination of the input values.

LOGIC DIAGRAM & TRUTH TABLE:

Page 17 of 20
DEPARTMENT OFECE                                             LAB CODE: 613751
CO-ORDINATORS NAME: Mr. T. VINO, Ms. M. S. SHEEBA            LAB NAME: VLSI DESIGN LAB

TRUTH TABLE:

CLK     Din         Q0        Q1           Q2        Q3
↑        1           1         0            0         0
↑        0           0         1            0         0
↑        1           1         0            1         0
↑        0           0         1            0         1

SHIFT REGISTER – SERIAL INPUT PARALLEL OUTPUT:

LOGIC DIAGRAM:

TRUTH TABLE:

INPUT                                OUTPUT
Si           Q1          Q2          Q3              Q4        S0
0             0          0              0            0          0
1             0          0              0            1          0
1             0          0              1            1          0
1             0          1              1            1          0
1             1          1              1            1          1
0             1          1              1            0          1
0             1          1              0            0          1
0             1          0              0            0          1
\
RESULT:

Thus the VHDL program is simulated and the output waveform and the corresponding RTL
schematic is obtained.

Page 18 of 20
DEPARTMENT OFECE                                                 LAB CODE: 613751
CO-ORDINATORS NAME: Mr. T. VINO, Ms. M. S. SHEEBA               LAB NAME: VLSI DESIGN LAB

10. COUNTERS

AIM:

To develop source code for up/down counter circuit by using VHDL and obtain the
simulation,synthesis using XILINX ISE 7.1i

ALGORITHM:
 Declare the name of design, entity and architecture body.

 Write the source code in VHDL.

 Compile the code and check for the errors.

 Simulate the program and verify the waveform using any of the simulators ISE or MODELSIM

 Verify the output for all the combination of the input values.

LOGIC DIAGRAM & TRUTH TABLE:

Page 19 of 20
DEPARTMENT OFECE                                          LAB CODE: 613751
CO-ORDINATORS NAME: Mr. T. VINO, Ms. M. S. SHEEBA         LAB NAME: VLSI DESIGN LAB

TRUTH TABLE:

UP COUNTING                        DOWN COUNTING
Direction             OUTPUT          Direction         OUTPUT
HIGH                  0000             LOW               1111
HIGH                  0001             LOW               1110
HIGH                  0010             LOW               1101
HIGH                  0011             LOW               1100
HIGH                  0100             LOW               1011
HIGH                  0101             LOW               1010
HIGH                  0110             LOW               1001
HIGH                  0111             LOW               1000
HIGH                  1000             LOW               0111
HIGH                  1001             LOW               0110
HIGH                  1010             LOW               0101
HIGH                  1011             LOW               0100
HIGH                  1100             LOW               0011
HIGH                  1101             LOW               0010
HIGH                  1110             LOW               0001
HIGH                  1111             LOW               0000

RESULT:

Thus the VHDL program is simulated and the output waveform and the corresponding RTL
schematic is obtained.

Page 20 of 20

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