Introduction to Bioinformatics - North South University(4)

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					    Lecture 7

    Presented By
 Dr. Shazzad Hosain
Asst. Prof. EECS, NSU
       Real Mode Memory Addressing
• The first 1MB memory is Real memory or the
  Conventional memory
                                                         Segment n
                                        SS     A000h
                                                             *
                                                             *
                                                             *
                                                                       1MB

                                             offset      Segment 2
     16 bit Segment registers
                                        DS     8000h

                                                           Segment 1
1.   1 MB requires 20 bit address
2.   Each segment is 64 KB              CS 0000h
3.   Offset address is 16 bit or 2 byte
4.   Actual address = segment address + offset address
  Real Mode Memory Addressing
• Real mode operation allows to address 1MB of
  memory space – even for the Pentium
  microprocessor
• This first 1MB memory is called the real memory
  or the conventional memory
• A combination of segment and offset address
  access the real memory
• Segment registers contains the beginning address
  of any 64KB memory segment
• The offset address selects the any location within
  the 64KB memory space
    Segment Plus Offset Determines Address

 To get the real address
      1. Pad 0H at the end of segment register
      2. Add the offset value


    CS       = 1000H       DS       = 1234H
    Offset   = F000H       Offset   = 245FH
        10000H                 12340H
         F000H                  245FH
        1F000H                 1479FH

1. Since each segment is 64 K, the offset
   address can take maximum of FFFFH
2. Once, the beginning address is found in
   segment registers, ending address is
   calculated by adding FFFFH with the value of
   segment register after padding 0H after it.
                                                  From Intel Microprocessor
Default Segment and Offset Registers




                1. If CS = 1400H and IP/EIP = 1200 H
                2. The microprocessor access instruction from
                   14000 H+ 1200H = 15200H.
                          Suppose
                          1. 1000H bytes of code
                          2. 190H bytes of data
                          3. 200H bytes of stack


                                                                Allows
                                                                relocation




Figure 2-4: A memory system showing the
placement of four memory segments                  Figure 2-5
             Protected Mode
• The segment register now contains a selector
• Selector selects a descriptor from a descriptor
  table
• The descriptor describes the memory
  segment’s location
• Two descriptor table
  – Global Descriptor Table (GDT)
  – Local Descriptor Table (LDT)
           Selectors and Descriptors

                                  *
                                  *
                                  *   8191
                                       *
                                       *
                 Offset     16         2       31
                             8         1       15
                             0         0        7

Segment Registers                 GDT/LDT
As Selector

    1.   8192 number of descriptors in each table
    2.   Each descriptor 8 bytes long, thus table size is 64 KB
    3.   Selector selects one descriptor
    4.   Descriptor describes the segment
Selectors and Descriptors                         8191
                                                   *
                                                   *
     Segment Register              Offset   16     2        31
                                             8     1        15
                        CS/DS/ES             0     0         7
                                                 GDT/LDT

                            0000 0000 0001 0010     0012H
                            0000 0000 0100 0100     0044H
                            1111 1111 1111 0000     FFF0H
           Selectors and Descriptors
                          8191
                           *
                           *
           Offset   16     2       31
                     8     1       15
CS/DS/ES             0     0        7
                         GDT/LDT
Access Right Bits
           Selectors and Descriptors
                          8191
                           *
                           *
           Offset   16     2       31
                     8     1       15
CS/DS/ES             0     0        7
                         GDT/LDT




                                    7   0000     0000   0000         0000   6

                                    5   1001     1011           00H         4

                                    3          A0H             C2H          2

                                    1          10H             00H          0
           Selectors and Descriptors
                          8191
                                           Code a descriptor for 80286 that
                           *
                           *               starts at 210000H and ends at
           Offset   16     2       31      21001FH. This memory segment is a
                     8     1       15      code segment that can be read
CS/DS/ES             0     0        7
                         GDT/LDT




                                    7    0000     0000     0000         0000   6

                                    5                              21H         4

                                    3           00H               00H          2

                                    1           00H               1FH          0


                                        Limit = 21001FH – 210000H = 001FH
Selectors and Descriptors
                    Code a descriptor for 80286 that
                    starts at 210000H and ends at
                    21001FH. This memory segment is a
                    code segment that can be read




             7    0000     0000     0000         0000   6

             5    1xx1     1x11             21H         4

             3           00H               00H          2

             1           00H               1FH          0


                 Limit = 21001FH – 210000H = 001FH
          Selectors and Descriptors




•   32 bit / 4 byte base, memory size is 4 GB = 22x210x210x210
•   AV = 1, means available, 0 means not available
•   D = 1, means 32 bit instructions, 0 means 16 bit instructions
•   G bit or the Granularity bit
    – G = 0, the limit is from 1 to 1MB in length
    – G = 1, the limit is multiplied by 4K bytes (appended with 000H). So
      segment length is 4K to 4G bytes in steps of 4K bytes
          Selectors and Descriptors

                                               01H                A         0H
                                      7                     0 D O V              6

                                      5                            00H           4

                                      3          00H                  00H        2

                                      1          FFH                  FFH        0

                                                       Start = 01000000H
                                                       Limit =    0FFFFH
• G bit or the Granularity bit                         End = 0100FFFFH
   – G = 0, the limit is from 1 to 1MB in length
   – G = 1, the limit is multiplied by 4K bytes (appended with 000H). So
     segment length is 4K to 4G bytes in steps of 4K bytes
          Selectors and Descriptors

                                               00H                 A         0H
                                      7                     1 D O V               6

                                      5                            28H            4

                                      3          00H                   00H        2

                                      1          00H                   10H        0

                                                       Start = 00280000H
                                                       Limit =    00010 H
                                                                    000
• G bit or the Granularity bit                         End = 00390000H
   – G = 0, the limit is from 1 to 1MB in length
   – G = 1, the limit is multiplied by 4K bytes (appended with 000H). So
     segment length is 4K to 4G bytes in steps of 4K bytes
                                                03H                    A         0H
                                       7                       1 D O
                                                               G                      6
                                                                       V

                                       5                               00H            4

                                       3          00H                      00H        2

                                       1          2FH                      FFH        0

                                                        End   = 05FFFFFFH
                                                        Start = 03000000H
• G bit or the Granularity bit                          Size    = 02FFFFFFH
   – G = 0, the limit is from 1 to 1MB in length        Limit =       02FFFH

   – G = 1, the limit is multiplied by 4K bytes (appended with 000H). So
     segment length is 4K to 4G bytes in steps of 4K bytes
       03H                      A         0H
7                       1 D O
                        G                      6
                                V

5   1xx1     001x               00H            4

3          00H                      00H        2

1          2FH                      FFH        0

                 End   = 05FFFFFFH
                 Start = 03000000H
                 Size    = 02FFFFFFH
                 Limit =            02FFFH
                   References
• Chapter 2, Intel Microprocessors – by Brey

				
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