FM Transmitter

					FM Transmitter
        FM Modulation using VCO
                                                 [1]
                                          fout
  i   c  c f mt 

  t    t t  c f mt dt  c
                  
                  
 SPM  Ac cos  c t  c f mt dt
                                    
                                                  Vin

 c - Free Running Frequency of VCO
                  Corresponding DC bias
Cf   - Gain of VCO
         Block Diagram


Input            VCO   PA


        DC Bias
         Vcc/2
         Chipset


• 4046 Phase-Locked Loop

• LM7171 Wide-Band Power Amplifier

• 741 Op Amp
4046 PLL




Only use the VCO
4046 VCO Characteristic

       C1>=100pF
Schematic
  PCB Layout Considerations
• The signal traces should be short and wide to lower
the impedance.
• The width of the signal traces has to satisfy current
driving capacity.
• Any used board area should be shorted to ground to
reduce AC noise.
• Sockets and pads will induce extra capacitance, so
components should be directly soldered to board.
• Surface mount components are preferred over
discrete ones for less lead inductance.
PCB Layout
Measured Results


 • Carrier Frequency: 15MHz

 • Bandwidth: Controllable

 • Output Power: 500mW
FM Receiver
 FM Demodulation using PLL
                                                             [2]
f     K p K v F s 
   
i   s  K p K v F s 

     1
                                       PFD         LF   Ve
 f  K v Ve
     s
                                 in
          sK p F s 
Ve                         i
       s  K v K p F s 
                                             VCO
s i  Cf mt 
Loop Filter Design
    L  4 n
         n
            R 2C  0.7
         2
                 K pKv       [3]
    n 
              N R 1R2 C
             VCO Design

• VCO free running frequency = Carrier Frequency

• VCO Frequency Range is no smaller than
Bandwidth

• Large VCO gain will increase PLL natural frequency
n and thus improves PLL tracking capability
        Block Diagram


BPF   LNA   PFD         LF   Amp



                  VCO
  Chipset

• 4046 PLL

• CLC425 Wide-band LNA
4046 PLL
Schematic
PCB Layout
Superheterodyne FM
     Receiver
           Block Diagram


 Input                IF Amp +
             Mixer
Matching               IF Filter




                        FM         Amp
              LO
                     Demodulator
         Chipset


• TDA7000 – FM Radio

• LM3875 – Audio Power Amplifier
TDA7000




          [4]
IF Filter
Quadrature Demodulator
              H s  
                                     1
                         R2 1  j R1  R2 C 


                                Vout




                                                    fin
IF Harmonic Distortion

          RF  75kHz

           IF=70kHz

   2IF  IF   IF  IF  IF  15kHz
IF Distortion Suppression




   FLL
                 Correlator
          To suppress interstation noise




• Not Modulated
• Lightly Modulated
• Heavily Modulated
Schematic
PCB Layout
Monolithic FSK Transmitter

                       [5]
                     Block Diagram
                          Reference               PLL
                                                            Output
                          Frequency


                                             Dual Modulus
                     Digital
                                               Prescaler
                     Input


           A/D                     Shift
Analog   Converter                Register
 Input


                               Clock     Data
                                       Sampling
                                         Rate
Inverter
NAND – 2 Input
NAND – 3 Input
NAND – 4 Input
NOR – 2 Input
XOR
Transmission Gate
Edge-Triggered D Flip-Flop
D Flip-Flop with ‘CLEAR’
Voltage Comparator
8-to-3 Encoder
A/D Converter
Parallel-Serial Shift Register
Phase-Frequency Detector
VCO
Dual Modulus Prescaler
                         [6]
                    Output Driver
To drive capacitive load with minimum delay

   
A 0 Wn ,W p        
                  A1 W n ,W p                   
                                            A N 1 Wn ,W p   




                                     CL
                            N  ln
                                     Cin

                                        1
                              C       N
                            A L 
                              C 
                               in 
Capacitor Driving Capability

                     CL=100p
                     f=50MHz
Synthesizer
Synthesizer Response
ADC and SR Response
Chip Layout
Digital Switching Noise

                     [7]
            Noise Mechanism
• Digital switching injects current into substrate through
various kinds of capacitance, which propagates through
the substrate and affects analog circuits.

• Digital switching draws current from power supply rail
with impedance and thus creates voltage drop on power
supply rail.
Digital Switching Noise in PLL
• PLL is a typical mixed-signal integrated circuit



           PFD             LF           VCO

                                  Noise Coupling

                           /N
Simulation Results

             Error Voltage




VCO output
Noise Reducing Techniques

    • Use Differential Topology

    • Separate Power Supply Rails

    • Use guard rings

    • Multi-chip Module

    • Heterogeneous integration
      Test Structure 1

     PFD            LF           VCO




                    /N



All building blocks share power supply rails
Chip Layout 1
     Test Structure 2

     PFD           LF          VCO




                   /N



The counter uses separate power supply rails
Chip Layout 2
        Test Structure 3

       PFD           LF         VCO




                     /N



• The counter uses separate power supply rails
• The PFD and VCO are shielded and ring guarded
        Guard Ring


                    p+      p+
Sink the coupling




         P-type Substrate
                On-Chip Shielding
                      Metal 3       Radiation

     Via2               ICs
     Via1
  Contact
Ohmic Contact
Chip Layout 3
        Test Structure 4

       PFD           LF           VCO




                      /N

• The counter uses separate power supply rails
• Use guard rings around PFD and VCO
• Implement LC VCO
          LC VCO
Lower Phase Noise than Ring Oscillator
                 Oscillator Basics
• Positive feedback of 2n phase shift
• Unity loop gain                                       [8]


 rp   - Tank Loss

             1
 0 
         LC
                            V1             rp   L   C
         1
 gm                               g mV1
        rp
        rp
 Q
       0L


 • Phase noise is reverse proportional to Q
Chip Layout
Electromagnetic Coupling
Microstrip Line Coupling
              4       3




                  L
  W   S

  1       2
                          [9]
Electric Field Distribution




 Even Mode        Odd Mode
                       Impedance Matrix

                    cot l                    cot l                    csc l                    csc l 
    j Zoe  Zoo            j Zoe  Zoo            j Zoe  Zoo            j Zoe  Zoo 
                       2                         2                         2                         2 
                    cot l                    cot l                    csc l                    csc l 
    j Zoe  Zoo            j Zoe  Zoo            j Zoe  Zoo            j Zoe  Zoo         
Z                    2                         2                         2                         2 
                    csc l                    csc l                    cot l                    cot l 
    j Zoe  Zoo            j Zoe  Zoo            j Zoe  Zoo            j Zoe  Zoo 
                       2                         2                         2                         2 
                    csc l                    csc l                    cot l                    cot l 
   j Zoe  Zoo             j Zoe  Zoo            j Zoe  Zoo            j Zoe  Zoo         
                      2                         2                         2                         2 


    Zoe - even mode characteristic impedance
    Zoo - odd mode characteristic impedance

     - propagation constant                            2  c
                                                                  2
Different Configurations

              Low Pass


              Band Pass


              Band Pass


              Band Pass
              Experiment Setup

f  100MHz  2.9GHz
P  0dBm

  Signal
                                  Metal (Copper) Line 1
 Generator
                                       Coupling
                        Metal (Copper) Line 2
                                                          Spectrum
                                                          Analyzer
                      FR-4 Substrate                        f ?
                      Ground Plane                          P ?
             Results




The coupling depends on L, W, S, and 
Integrated Inductor Coupling

• Coupling between integrated spiral inductors

• Coupling from spiral inductors to transistors




                                                  [10]
2.5D Integrated Inductor

                           [11]
Interference Effects on PLL
        Performance
                        [12]
                         References
1.  Jerry D. Gibson, Principles of Digital and Analog Communications
2.  Floyd M. Gardner, Phaselock Techniques
3.  Roland E. Best, Phase-Locked Loops – Theory, Design, and Applications
4.  W.H.A. Van Dooremolen and M. Hufschmidt, A complete FM radio on a chip
5.  R. Jacob Baker, Harry W. Li, David E. Boyce, CMOS Circuit Design, Layout, and
    Simulation
6. J. Navarro Soares and W.A.M. Van Noije, A 1.6-GHz Dual Modulus Prescaler
    Using the Extended True-Single-Phase-Clock CMOS Circuit Technique, IEEE
    Journal of SSCC, Vol.34, No.1, Jan 1999
7. Patrik Larsson, Measurements and Analysis of PLL Jitter Caused by Digital
    Switching Noise, IEEE Journal of SSCC, Vol.36, No.7, July 2001
8. Dan H. Wolaver, Phase-Locked Loop Circuit Design
9. E.M.T.Jones and J.T.Bolljahn, Coupled-Strip-Transmission-Line Filters and
    Directional Couplers, IRE Trans on Microwave Theory and Techniques, 1956
10. A.O.Adan, M.Fukumi, K.Higashi, T.Suyama, M.Miyamoto, M.Hayashi,
    Electromagnetic Coupling Effects in RFCOMS Circuits, 2002 IEEE MTT-S Digest
11. Jaime Aguilera and Joaquin De No, A Guide for On-Chip Inductor Design in a
    Conventional CMOS Process for RF Application
12. Murat F. Karsi, William C. Lindsey, Effects of CW Interference on Phase-Locked
    Loop Performance, IEEE Trans on Comm, Vol.48, No.5, May 2000

				
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