This paper focused on the development of capacitor voltage balancing methods in a flying capacitor multilevel inverter (FCMLI) fed induction motor drive. For improving the performance of flying capacitor multilevel inverter, a switching pattern selection scheme is implemented. The proposed method has been designed a nine -level flying capacitor multilevel inverter by using sinusoidal pulse width modulation technique. The selected pattern has been exposed to give superior performance in load voltage, total harmonics distortion and capacitor voltage fluctuation. The performance of proposed strategies is confirmed through simulation investigations.
ACEEE International Journal on Electrical and Power Engineering, Vol. 1, No. 2, July 2010 An Enhanced Flying Capacitor Multilevel Inverter fed Induction Motor Drive K.Ramani1,A.Rathinam2 and Dr.A.Krishnan3 Research Scholar/SL/Dept.of.EEEfirstname.lastname@example.org 1 2 PG Scholaremail@example.com 3 Dean/ Dept.of.EEEfirstname.lastname@example.org K.S.Rangasamy College of Technology ,Tiruchengode, Namakkal- 637215,Tamilnadu, India Abstract- This paper focused on the development of capacitor.A filter circuit of the RLC type tuned at the capacitor voltage balancing methods in a flying capacitor switching frequency, connected in parallel with the multilevel inverter (FCMLI) fed induction motor drive. load may be used to achieve the natural balancing For improving the performance of flying capacitor under all conditions. However, the extra filter increases multilevel inverter, a switching pattern selection scheme is implemented. The proposed method has been designed the cost of the overall system. Another popular method a nine -level flying capacitor multilevel inverter by using of capacitor voltage balancing is to vary duty cycles of sinusoidal pulse width modulation technique. The selected the switches to charge or discharge the corresponding pattern has been exposed to give superior performance in capacitors. There are many ways such as carrier load voltage, total harmonics distortion and capacitor rotation strategy -, modulating signal voltage fluctuation. The performance of proposed modification strategy , etc. In the control scheme strategies is confirmed through simulation investigations. discussed in -, balancing is achieved by Index Terms - Total Harmonic Distortion, Flying preferential charging or discharging of the capacitors. Capacitor Multilevel Inverter (FCMLI), AC Drive, This paper highlights sinusoidal PWM based flying Sinusoidal pulse width modulation (SPWM). capacitor voltage-balancing schemes fed induction motor is discussed. This scheme does not require any I. INTRODUCTION modification in the carrier or modulating signal. It has advantage or superiority over other previous works. In recent year, multilevel power inverters are The modeling of in this paper highlights significance of popular due to their high-power, high voltage capacity, a nine level FCMLI. low switching losses and low cost. The various different topologies of inverters are neutral point clamped inverters, flying capacitor inverters and II.FLYING CAPACITOR MULTILEVEL cascaded multi level with separated dc source inverter INVERTER (FCMLI) -. Midway the Flying Capacitor Multi-level Inverter (FCMI) does not require isolated dc sides and The FCMLI requires a large number of capacitors to additional clamping diodes. However, these properties clamp the device voltage to one capacitor voltage level, may be quite limited by the voltage unbalancing of provided all the capacitors are equal values. The size of flying capacitors which the most serious problem. the voltage increases between two consecutive legs of the clamping capacitors. Hence the size of voltage 1 Hence the FCMLI has to ensure the voltage balancing steps in the output waveform. of flying capacitors under all the operating conditions. The FCMLI offers a great advantage with respect to the A. Basic Configuration of FCMLI availability of voltage redundancies. They are defined A block diagram of nine-level FCMLI is shown in fig as different combinations of capacitors allowing the 1.It consists of input dc source, switching devices, load charging or discharging of the individual flying and control circuit. capacitors in order to produce the same phase leg voltage. This advantage provides the special opportunity for controlling the individual voltage on flying capacitors -. Many studies have publicized that under certain conditions, a simple open loop control guarantees natural balancing of the flying 1 Ramani.K, and Rathinam.A are with Department of Electrical and Electronics Engineering, K.S.Rangasamy college of Technology, Tiruchengode. 637215 ;Mobil Number +91 97885 18536 / +91 994228851Dr.Krishnan.A, is Dean, K.S.Rangasamy college of Figure 1. Block diagram for FCMLI. Technology, Tiruchengode.637215 22 © 2010 ACEEE DOI: 01.ijepe.01.02.05 ACEEE International Journal on Electrical and Power Engineering, Vol. 1, No. 2, July 2010 The control circuits control the switching devices by Van = S A1 ( Vdc − VC1 ) + S A 2 ( VC1 − VC 2 ) + S A3 ( VC 2 − VC 3 ) using a sinusoidal pulse width modulation (SPWM) strategy. + S A 4 ( V C 3 − V C 4 ) + S A 5 ( VC 4 − VC 5 ) + S A 6 ( V C 5 − V C 6 ) The voltage of main dc-link capacitor is V dc. The V + S A7 VC 6 − VC 7 + S A8VC 8 − dc (3) voltage of the capacitor clamping of the innermost two 2 devices are Vdc (1) n −1 The voltage of the next innermost capacitor will be Vdc V 2Vdc + dc = (2) n −1 n −1 n −1 Each next clamping capacitor will have the voltage Vdc increment of from its immediate inner one. The n −1 Figure 3. Phase-A leg of nine -level FCMLI. voltage levels and the arrangements of the flying capacitor in the FCMLI structure assure the voltage B.Modulation Scheme stress across each main device is same. It is equal to In this paper, control technique of sinusoidal pulse Vdc for an n- level inverter. width modulation (SPWM) strategy is employed. In n −1 this method, a number of triangular waveforms are Three phase of a nine-level inverter fed induction compared with a controlled sinusoidal modulating motor as shown in fig 2. A single leg of a nine -level signal. The switching rules for the switches are decided inverter shown in fig 3 and likewise others two are by the intersection of the carrier waves with the modulating signal [8, 9, and 10]. The proposed nine coupled to the same dc-link battery Vdc . In fig 1 each level inverter, one modulating signal and eight carrier switch S A1 to S A8 and S ' A1 to S ' A8 consist of a power waves are necessary for each phase of the inverter as semiconductor device (e.g. MOSFET, GTO and IGBT shown in Figure 4. etc) with connected in anti-parallel diode. Voltages Vc1, Vc2, Vc3, Vc4, Vc5, Vc6, and Vc7, are 7 3 5 V 3 V Vdc Vdc , Vdc , Vdc , dc , Vdc , dc , and 8 4 8 2 8 4 8 respectively, as n = 9. Figure 4. Modulation scheme for nine -levels The modulating signal of each phase is displaced from each other by 120°. All the carrier signals have same frequency fc and amplitude Ac while the modulating signal has a frequency of fm and amplitude of Am.The fc should be in integer the multiples of fm with three- times. This is required for all the modulating signal of all the three phases see the same carriers, as they are Figure 2. Nine-level FCMLI fed three phases Induction motor. 120° apart. The main dc capacitor combination C is the energy The carrier waves and the modulating signals are storage element, while capacitors CA1, CA2, CA3, CA4, compared and the output of the comparator defines the CA5, CA6 and CA7 are the flying capacitors that provide output voltage waveform. It is assumed that the the multilevel voltage ability to the converter. Skj and modulating signal varies from + 1V to – V.The S’kj are the complementary switches where j=1 to 8 and amplitudes of the eight carriers waves vary in the step k are A, B, C of phases respectively.Thus if SA1 is ON, of + 0.25V. In the positive half cycle the comparator S’A8 is OFF and vice-versa. For any initial state of output will have the value high, if the amplitude of the clamping voltage, the inverter output voltage is given modulating signal is greater than that of the carrier by wave and 0 otherwise. Similarly, for the negative half 23 © 2010 ACEEE DOI: 01.ijepe.01.02.05 ACEEE International Journal on Electrical and Power Engineering, Vol. 1, No. 2, July 2010 cycle if the modulating signal is lower than the carrier 1 wave, the output of the comparator is high and 0 0.5 0 0 0.02 0.04 0.06 0.08 0.1 1 otherwise. 0.5 0 0 0.02 0.04 0.06 0.08 0.1 1 0.5 0 0 0.02 0.04 0.06 0.08 0.1 1 0.5 Voltage in volt 0 0 0.02 0.04 0.06 0.08 0.1 1 0.5 0 0 0.02 0.04 0.06 0.08 0.1 1 0.5 0 0 0.02 0.04 0.06 0.08 0.1 1 0.5 0 0 0.02 0.04 0.06 0.08 0.1 1 0.5 0 0 0.02 0.04 0.06 0.08 0.1 Time in sec Figure 7. Switching pulses for SA1 to SA8 1 Figure 5. Switching voltage Technique for FCMLI 0.5 0 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 1 0.5 In the nine-level FCMLI each carrier waveform and 0 1 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 sine waveform are compared individually. The 0.5 0 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 1 Switching voltage Technique for FCMLI is shown in 0.5 Voltage in volt 0 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 1 fig 5. The individual comparator output is given to the 0.5 0 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 1 switching devices .An example of switching pulse 0.5 0 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 generation simulation model is shown fig 6.As in fig 6 1 0.5 0 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 the comparator output is directly given to SA1 and S A1’ 1 0.5 0 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 is connected through not gate, because S A1’ Time in sec complementary operation of SA1. Figure 8. Switching pulses for S’A1 to S’A8 III. PROPOSED SCHEME In the paper, nine levels inverter is designed. The output voltages nearly get sinusoidal. It reduced harmonics and increase inverter efficiency. The implementation of ZVS or ZCS further reduces the switching loss. The nine level flying capacitor inverter fed induction motor drive has been developed by using MATLAB software. Figure 6. Simulation model for one switching pulse IV. RESULT ANALYSIS In the nine-level FCMLI eight carrier waveform and a sine waveform are compared with comparator .This The nine-level FCMLI has been simulated using MATLAB. comparator output is given to SAj and S’Aj switches The output of the inverter voltage is shown in simulation where j=1 to 8. S’Aj is the complementary function of results. Fig 10 shows the FCMLI phase voltage waveform. SAj. In this way nine output levels are obtained. A The stator of three phase induction motor is star connected. Simulation model for switching pulses shown in A. Nine -Level FCMLI Fig.6.It consists of eight carrier wave generators, a sine wave generator and relational operator. The outputs of The FCMLI output balanced phase voltage is 200Volts each comparator for each phase are combined to with nine levels as shown in figure 9.The line voltage produce the corresponding decision signals for the is shown in fig10. It agrees with the conventional star switches to synthesize the output voltage of that phase. connected stator voltage. Fig 11 exhibits the three The SPWM output reference signal is shown in Figure phase stator voltage waveform. The nine step 5. This signal resembles with the output voltage arrangement brought the simulation waveform in waveform of the inverter and decides the voltage level, closed resemblance with the three phase sinusoidal which is to be generated at a particular instant. waveform for the inverter parameters given in table I. The nine-level FCMLI control circuit produce TABLE I NINE -LEVEL INVERTER PARAMETERS switching pulses for SAj and S’Aj switches where j=1 to 8. S’Aj is the complementary function of SAj. The Number of main switches 48 sequence of the switching pulse turn-on the switching Main devices type IGBT devices, and the FCMLI produce nine-level output Device ON resistance 0.01 ohm voltage. The switching pulses for SAj and S’Aj switches Device OFF resistance 1.0E6 ohm are shown in fig 7 and 8. Forward voltage drop 0V FCMLI capacitances 3600 μF 24 © 2010 ACEEE DOI: 01.ijepe.01.02.05 ACEEE International Journal on Electrical and Power Engineering, Vol. 1, No. 2, July 2010 The nine levels FCMLI phase have nine levels of 1500rpm. A nine level FCMLI fed induction motor speed curve result shown in fig 12. It quickly settles to Vdc 3 Vdc Vdc V 3 V V a constant speed. The stator current and ( , Vdc , , ,0, − dc , − Vdc , − dc , − dc 2 8 4 8 2 8 4 8 electromagnetic torque are initially has maximum ) starting current then get reduced at rated value of the and line to line voltages have fourteen levels. motor current. 1500 200 Speed in rpm 100 Voltage in volt 1000 0 -100 500 -200 0 0.02 0.04 0.06 0.08 0.1 0 Time in sec 0 0.1 0.2 0.3 0.4 0.5 im T e in sec Figure 9. Phase voltage of FCMLI Figure 12 .Speed curve of induction motor 400 Total Harmonic Distortion of nine-level FLCMLI is 200 13.22% which is illustrated in figure 13. In the nine- Voltage in volt 0 level FCMLI, THD is reduced compared to THD value of five and seven -level FCMLI. The THD value of -200 five and seven are 26.26% and 17.76% respectively. -400 Different level of FCMLI THD values are compared it 0 0.02 0.04 0.06 Time in sec 0.08 0.1 shown in table III. It have obtained same simulation parameters values Figure 10. Line voltage of TABLE III COM PARISON OF THD 400 200 Five-level Seven-Level Nine-level FCMLI FCMLI FCMLI Voltge in volt 0 (% of THD) (% of THD) (% of THD) -200 -400 0 0.01 0.02 0.03 0.04 0.05 Tim e in sec 26.26 17.76 13.22 Figure 11. Three phase output line voltage of FCMLI The fluctuation in capacitor voltage is tiny. This can be further reduced by increasing capacitance values and carrier frequency. Flying capacitor voltage Table II highlights the voltages across the capacitors. TABLE. II FLYING CAPACITORS VOLTAGE Capacitors Capacitors voltages C1 50 Volts C2 100 Volts C3 150 Volts C4 200 Volts C5 250 Volts C6 300 Volts B. FCMLI fed Induction Motor Induction motors are widely used in industries because Figure.13 THD of nine levels FCMLI. it offers lot of advantages. The proposed method of a nine -level FCMLI is fed to induction motor drive of rating 5HP, 400V and supply frequency of 50Hz, speed 25 © 2010 ACEEE DOI: 01.ijepe.01.02.05 ACEEE International Journal on Electrical and Power Engineering, Vol. 1, No. 2, July 2010 V.CONCLUSION  G. Carrara, S. Gardella and M. Marchesoni, "A new multilevel PWM method: A theoretical analysis", IEEE In the proposed method, nine levels flying capacitor Trans. Power Electronics, Vol. 7, No. 3, pp. 497-505, multilevel inverter provides sinusoidal waveform and 1992. increased efficiency. The basic concepts and  M. H. Rashid, Power Electronics Handbook, Academic operational features of inverter have been explored. A Press, London, 2001. control scheme has been proposed which uses the preferential charging or discharging of flying the VI. BIOGRAPHIES capacitors to balance their voltages. The control K.Ramani was born in Vedaranyam on scheme allows balanced flying capacitor voltages; May 7, 1982. He is graduated in 2004 hence output phase and line voltages are obtained with from Bharathiar University, Coimbatore much less THD. The nine level flying capacitor and post graduated in 2006 at Anna multilevel inverter fed induction motor has been University, Chennai. He is a Research illustrated with scholar in Anna University Chennai simulation results using MATLAB. The technique is under the guidance of beloved used to improve the level of the inverter to extend the Dr.A.Krishnan, Dean, K.S.Rangasamy College of Technology, Tiruchengode. He is currently design flexibility and reduces the harmonics. working as a senior lecturer in the department of EEE at K.S.Rangasamy College of Technology, Tiruchengode from REFERENCES January 2006. He published 12 international/national  J. L. Thomas, S. Poullain, A. Donzel, and G. Bornard, conferences, journals. His research interest involves in power “Advanced torque control of induction motors fed by a electronics, inverter, modeling of induction motor and floating capacitor multilevel VSI actuator”, IEE optimization techniques. He is guiding UG, PG Students. He Seminar, 'Advances in Induction Motor Control', 23 is life member of an ISTE, IETE member. May, 2000, pp. 5/1 - 5/5.  T. Meynard, H. Foch, P. Thomas, J. Courault, R. Jakob A.RATHINAM was born in Salem on and M. Nahrstaedt, “Multicell converters: basic concepts May 7, 1977. He is graduated in 2008 and industry applications”, IEEE Trans. Ind. from Govt college of Engineering, Electronics, Vol. 49, No. 5, pp. 955-964, Oct. 2002. Salem and doing post graduated in  K.Ramani and A.Krishnan “High performance Flying K.S.Rangasamy College of Capacitor based Multilevel Inverter fed Induction Technology, Tiruchengode He is on Motor” International Journal of Recent Trends in Research under the guidance of Engineering Vol. 2, No. 6, Nov 2009. Pp 7-9 beloved K.Ramani senior lecturer in  L. Xu and V. G. Agelidis, “Active capacitor voltage the department of EEE at control of flying capacitor multilevel converters,” Proc. K.S.Rangasamy College of Technology, Tiruchengode.He IEE Proceeding − Electrical Power Applications, Vol. published 6 international/national Journals and conferences. 151, No. 3, pp. 313-320, May 2004. His research interest involves in power electronics, inverter,  A. Shukla, A. Ghosh and A. Joshi, “ Static shunt and modeling of induction motor and optimization techniques. series compensation of an SMIB system using flying capacitor multilevel inverter”, IEEE Trans. Power Delivery, Vol. 20, No. 4, pp. 2613-2622, 2005. Dr. A.Krishnan received his Ph.D  X. Kou, K. A. Corzine and Y. A. Familiant, “Full binary Degree in Electrical Engineering from combination schema for floating voltage source multi- IIT, Kanpur. He is IEEE senior member level inverters”, Proc. IEEE Ind. Appl. Conf., Vol. 4, pp. and FIE. He is now working as a Dean 2398-2404, 2002. at K.S.Rangasamy College of  Escalante, M.F. and Vannier, J.-C., “Direct approach for Technology, Tiruchengode and guide at balancing the capacitor voltages of a 5-level flying Periyar University, Salem and Anna University, Chennai. His capacitor converter”, Proceedings of EPE '99, 8th research interest includes Control System, Digital Filter, European Conference on Power Electronics and Power Electronics, Digital Signal Processing, and Artificial Applications, Lausanne, France, 7 - 9 September,1999. Intelligent Techniques. He is a visiting professor in ISTE  A. Ghosh and G. Ledwich, Power Quality Enhancement chapter. He has been Published more than 250 technical using Custom Power Devices, Kluwer Academic papers at various National and International Conferences and Publishers, Boston, 2002 Journals. He is a visiting professor foreign universities and ISTE. 26 © 2010 ACEEE DOI: 01.ijepe.01.02.05
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