AN INNOVATIVE APPROACH OF HIGH PERFORMANCE CMOS CURRENT CONVEYOR - II FOR ANALOG SIGNAL PROCESSING APPLICATIONS

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AN INNOVATIVE APPROACH OF HIGH PERFORMANCE CMOS CURRENT CONVEYOR - II FOR ANALOG SIGNAL PROCESSING APPLICATIONS Powered By Docstoc
					  INTERNATIONAL JOURNAL OF Technology (IJCET), ISSN 0976 – 6367(Print),
International Journal of Computer Engineering andCOMPUTER ENGINEERING &
ISSN 0976 – 6375(Online) Volume 3, Issue 1, January- June (2012), © IAEME
                                 TECHNOLOGY (IJCET)

ISSN 0976 – 6367(Print)
ISSN 0976 – 6375(Online)
Volume 3, Issue 1, January- June (2012), pp. 147-153
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AN INNOVATIVE APPROACH OF HIGH PERFORMANCE CMOS
CURRENT CONVEYOR - II FOR ANALOG SIGNAL PROCESSING
                  APPLICATIONS
                              Rajinder Tiwari, R. K. Singh
                    Department of Electronics & Comm. Engineering,
                           Kumaon Engineering College (KEC),
                            Dawarahat (Almora), Uttarakhand
               Email: trajan@rediffmail.com rksinghkec12@rediffmail.com

ABSTRACT

The purpose of this paper is to present a CMOS current conveyor circuit suitable for
implementation of low- voltage, low-power, high bandwidth circuits. This circuit can be
operated for a power supply of fraction of volt so as to achieve the bandwidth of current
transfer function of MHz range and a power consumption of milli-watts range. Firstly, a class A
current conveyor circuit that operates from a single supply of fraction of volt with a high voltage
swing capability is discussed and then the same circuit can be modified to work as a class AB
with a low voltage power supply in the fraction of volt range, while maintaining the same voltage
swing capability. This current conveyor realization is insensitive to the threshold voltage
variation caused by the body effect, which minimizes the layout area and makes both circuits a
valuable addition to the analog signal processing applications. The proposed structure operates as
linear circuit element and has the required performance in terms of a bandwidth using level 3
CMOS technology which is established with the help of 0.3 um simulation using PSpice
software. This proposed current conveyor circuit has lot many applications in the field of analog
signal processing. The proposed circuit operates satisfactorily at 0.2µm with high performance
with the desired applications. PSpice simulation with the modeled parameters confirms the
desired properties & performance of the proposed circuit.

Keywords: Current Conveyor (CC II) Aanalog Signal Processing, pSice simulation, low votlage,
high bandwith, high performance, Current Mirror (CM), Operational Amplifiers (OA).

  I.    INTRODUCTION
The current conveyors and unity gain amplifiers are widely used in the analog circuit designing,
especially, in the signal processing applications [1, 2]. The current conveyors (CC II) can be
considered as the current controlled current source with unity gain amplification capability. This
circuit is quite used to take out the current flowing through a floating branch of a circuit and can be
systematically, used in the realization of the various sub-modules of the mixed analog processing


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International Journal of Computer Engineering and Technology (IJCET), ISSN 0976 – 6367(Print),
ISSN 0976 – 6375(Online) Volume 3, Issue 1, January- June (2012), © IAEME

applications of the systems [3, 4]. In this case, the high performance current mirror circuits are
utilized in the CC-II so as to provide good dynamic swing at the output and high output so as
provide a good cascadability.
Most of the current conveyor circuits reported so far in the research sections of the various
literatures requires high bis voltages. Thus, there always exists the requirement of the discussion of
the CC circuits that can operate at low voltages and low currents. The basic current conveyor
circuit can be categorized as CC-I, CC-II and CC-III [5, 7]. In the practical application of the
analog signal processing, the CC-II has been proved to be more versatile as compared to the
previous one. The port properties of the CC-II can be discussed as below:



                                                                   Vx = Vy
                                                                    Iy = 0                      (1)
                                                                    Iz = ±Ix
Fig 1: Basic Symbol of CC-II           Fig 2: Block Approach of CC-II               Basic Equations




                                  Fig: 3 Performance Characteristics of CC-II

The port properties of a basic current conveyor structure can be explained with the below given
matrix i.e. where Ix, Iy and Iz are the currents flowing in X, Y and Z nodes respectively. Also Vx, Vy
and Vz are the respective voltages in these nodes. As compared to the CC-I, the innovation of this
circuit can be represented by the absence of the current parameter in Y node, owing to the high
impedance. The signal applied to the Y node is almost equal to the X node and is given as:
                                       Vx   g m r0 RXLOAD
                                  α=      =                 ≅1          (2)
                                       Vy 1 + g m r0 RXLOAD
                Iz
          β=       =1                          (3)
                Ix

Similarly, the ratio of the current Ix and Iz can be discussed with the help of the following equation
i.e. the various dominant parameters of a CC-II circuit can be determined with the help of the
following equations i.e.
          2 I in                                             1                               gm gm2
  Vin =            + ∆Vth + V '              (4)     Rin ≈               (5)        Rout ≈              (6)
           β1                                                gm                              gd gd 2

where β, gm, gd, gm2 and gd2 are th e various usual dominant parameters that are required to
discuss the performance of a CC-II circuit.

                                                                                L4 I bias1 
                        Z y = γ WLCox                        (7) V ' = nVt ln                        (8)
                                                                               W4 I DO 4 
And the parameter V’ in terms of the biasing aspect can be given as by equation 8:

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ISSN 0976 – 6375(Online) Volume 3, Issue 1, January- June (2012), © IAEME

 II.   BASIC CURRENT CONVEYOR CIRCUITS
The current conveyor circuits realizable in the integrated circuits especially, using the CMOS
approach has got a considerable role in the development of the analog and mixed signal
processing applications [8, 11]. The CC-II is basically a three element device, which is defined
with the help of three basic equations given above.




                                                                                  Z y = γ WLCox           (9)
                                                                        ro + RZ LOAD   1
                                                                Zx ≅                 ≅          ,   if   ro>>RZLOAD
                                                                          1 + g m ro   gm
                                                                                             (10)
                                                                             Z z = ro + (1 + g m ro ) RXLOAD    11)



       Fig: 4 Basic CC-II Circuit Approach using CM Equations of the respective Impedance of the Circuit

The CC-II has been introduced in the research field as natural building blocks in the design of
analog signal processing circuits. It has been observed that the signal applied to the y node (MOS
gate) is almost equal to that obtained at the X node (source of the MOS). Similarly, the ratio of
the currents Ix and Iz is also approximately equal to 1 and is determined with the help of a
constant parameter β. The impedance behavior of the circuit at Y node can be determined as the
gate capacitance of the MOS which is quite high as per the required parameters. Practically, γ
being a constant parameter whose theoretical value is 2/3 in saturation region, otherwise 1, W and
L i.e. width and length of the MOS transistor respectively, Cox being the unitary gain capacitance,
these can be related in the following manner i.e. [12]. In the CC-II circuit as shown in fig: 4, it is
assumed that the two biasing currents are required to be equal. It is also assumed that the product
gmro has a value much greater than unity, then the voltage characteristic og the circuit is given as:

                             Vx                   1                                      (12)
                       a =      =                                       ≅1
                             Vy                       1
                                  1+
                                       ( g m 3 + g m 4 )( ro 3 ro 4 )

This is why in many situations the CCII-based solution can reduce the system complexity with
respect to more traditional implementations that utilize the commercial integrated circuits as the
voltage OAs. Since that time‚ hundreds of presentations and articles have witnessed the evolution
of the first CC concept‚ demonstrating the universality of the element in the synthesis of almost
all the active functions. It means that simply by maintaining the matrix characteristics‚ CCII
evolution has regarded its internal topology‚ so to enhance the performance and then the utility of
the CCII block. Certainly‚ the first implementations of the integrated CC-IIs presented in the
literature or as commercial products were realized in bipolar technology [13, 14]. The advent of
MOS transistors‚ however‚ has pushed the most of actual integrated solutions (in particular‚
those related to mixed analog - digital electronics) towards the use of CMOS technology‚ which
shows a higher design simplicity and also a very low power consumption‚ particularly attractive
in low-voltage portable-system applications. Even if CMOS devices suffer from other problems‚
such as body effect‚ threshold voltage mismatch between nMOS pMOS and lower Gm values‚ its
low cost especially for a standard technology represents a decisive feature towards its success

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International Journal of Computer Engineering and Technology (IJCET), ISSN 0976 – 6367(Print),
ISSN 0976 – 6375(Online) Volume 3, Issue 1, January- June (2012), © IAEME

and utilization. The use of CC in the implementation of analog basic function is very spread.
With respect to commercial solutions with OAs‚ CCII-based ones are often simpler in
structure and more versatile‚ especially for those circuits which involve high impedance
current output capabilities [15, 16]. Furthermore‚ through the use of CCIIs‚ the heavy OA
limitation of the constant gain-bandwidth product is definitely overcome. The main
characteristics that play a dominant role in the performance of a CC-II circuit can be summarized
in the below given table 1. With these values of the parameters, we can have a CC-II circuit that
provides wide bandwidth, low biasing currents that ensure a high performance current conveyor
circuit.

III.   PROPOSED CURRENT CONVEYOR CIRCUIT (CC-II)

With basic CC-IIs‚ it is possible to implement a number of analog applications such as voltage
and current amplifiers‚ current differentiators and integrators‚ capacitance multipliers‚ impedance
simulators and converters‚ bi-quadratic filters [17, 24]‚ voltage-to-current and current-to-voltage
converters‚ instrumentation amplifiers‚ oscillators and waveform generators‚ etc.. Number of
solutions are available in the literatures that has been used in the past but the new possibilities
with high performance can be certainly considered for the future‚ especially at lower supply
voltages and with more reduced dissipation. An important aspect of the discussion can be done
with the implementation of basic current conveyor‚ having an in the operation and behavior of its
non-ideal characteristics (input and output real and imaginary parasitic impedances‚ current and
voltage transfer functions‚ etc.). This approach leads us in the direction of an enhanced and
modified model for the CC-II device [25, 26]. Moreover‚ the development of novel architectures
able to implement analog functions with a lower number of basic elements can be of certain
interest for the researchers with new fields of applications for the CC-II‚ i.e. the development of
current-mode sensor interface circuits. The proposed circuit consists of four current mirrors, one
biasing resistor and a translinear section composed of two current quasi-mirrors (blocks which are
topologically similar to current mirrors, but their behavior is slightly different. The choice of the
type of current mirror to be used depends on the application for which the circuit is designed and
the which need output voltages in excess of the threshold voltage to operate properly. The current
conveyor with basic and simple current mirrors is implemented with a smaller number of
transistors, which influences the bandwidth of the circuit, i.e. allows operation at higher
frequencies. For biasing of a smaller number of transistors, a smaller power supply voltage is
needed and the power consumption is reduced. If all the CMOS transistors have matched
characteristics and infinite output resistances M6 and M8 have equal currents and gate-source
voltages i.e.
                     iD 6 = iD8 = I bias             (13)            vGS 6 = vGS 8           (14)

It means that the current iy=0 i.e. the desired performance of the circuit is achieved. When the
current ix is zero (the quiescent point) then drain currents iD7, iD9 are equal to the currents iD6 and
iD8, i.e. all drain currents of transistors in the translinear sections are equal to Ibias. Now when ix≠0,
then we can have
                         iD 7 + ix = iD 9                (15)
Again, if all the CMOS transistors are matched and since the complete current conveyor is
symmetrical, then the following relationship holds for ix << Ibias i.e.
                                    1                                                 1
                     iD 7 ≈ I bias − ix                  (16)          iD 9 ≈ I bias + ix        (17)
                                    2                                                 2
Thus, with the help of above mathematical relations, the proposed circuit fulfils all the required
conditions to behave as a current conveyor with the best possible performance and hence can be
utilized in the realization of the various analog signal processing applications.


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ISSN 0976 – 6375(Online) Volume 3, Issue 1, January- June (2012), © IAEME




                        Fig: 5 Proposed Cascoded CMOS based CC-II Circuit

 IV. SIMULATION RESULTS
The proposed CC-II circuit has been simulated for level 3 parameters at 0.2µm CMOS
technology. In this simulation, the performance of the proposed circuit has been discussed on the
basis of transient analysis, performance or noise analysis and dc analysis of the current conveyor
circuit, with the use of modeled parameters. The above fig: 6 show the transient analysis of the
proposed circuit with the desired performance. It shows that as per the theoretical concepts, this
circuit exactly replicated the input with a accepted level of delay and with a minimum possible
deterioration of the desired signal. The fig: 7 gives us the performance analysis of the circuit in
respect of the gain and the phase analysis upto the desired limits. And the fig: 8 show the dc
analysis of the circuit, with the perfect replication of the input signal at the output of the system.
The noise performance of the circuit was evaluated and the noise gain was found to be almost
near to zero. The power consumption of the proposed structure increases marginally from its
rated value.




Fig: 6 Transient Analysis of CC-II   Fig: 7 Performance Analysis of CC-II Circuit   Fig: 8 DC Analysis
                                                                                      of CC-II Circuit
 V.    CONCLUSION

In this paper, we have presented the design of an innovative high performance current conveyor
circuit that is capable of operating at fraction of volts. The proposed CC-II is capable of operating
at 1.0 V and has a power dissipation of 3mW. It has a bandwidth of 60 MHz. The input current
range extends from -300 pA to 300 pA. This structure could be easily modified to function as
CCI, CCII or CCIII. This circuit finds applications in generating mathematical functions used in
the various algorithms of the signal processing. This CMOS based cascoded CC-II circuit
realizations put forward a circuit that provide a rail to rail swinging capability with excellent
linearity. Since this circuit requires no compensating capacitors, they have a wide bandwidth
which is independent of the gain. The operation of the given circuits is insensitive to the threshold
voltage variation resulting from the body effect. PSpice simulations based on level-3 parameters
obtained through CMOS are in excellent agreement with the expected results. This CC-II circuit
has better features ans performance than the known ones.

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ISSN 0976 – 6375(Online) Volume 3, Issue 1, January- June (2012), © IAEME

ACKNOWLEDGEMENT
The authors are thankful to Prof. D. S. Chauhan (Vice Chancellor, UTU) for providing the
environment for this work, Mr. Aseem Chauhan (Additional President, RBEF), Major General K.
K. Ohri, AVSM, Retd. (Director General, AUUP, Lucknow campus), Prof. S. T. H. Abidi
(Director, ASET) and Brig. Umesh K. Chopra, Retd. (Dy. Director, ASET) for their kind
cooperation, motivation, kind and most valuable suggestions.
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