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WIDE-FREQUENCY-RANGE CMOS VOLTAGE CONTROLLED OSCILLATOR FOR PHASE LOCK LOOP – A REVIEW

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WIDE-FREQUENCY-RANGE CMOS VOLTAGE CONTROLLED OSCILLATOR FOR PHASE LOCK LOOP – A REVIEW Powered By Docstoc
					          INTERNATIONAL Communication OF ELECTRONICS AND
International Journal of Electronics and JOURNALEngineering & Technology (IJECET), ISSN 0976
– 6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 1, January- June (2012), © IAEME
 COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)

ISSN 0976 – 6464(Print)
ISSN 0976 – 6472(Online)
Volume 3, Issue 1, January- June (2012), pp. 10-16
                                                                       IJECET
© IAEME: www.iaeme.com/ijecet.html                                  ©IAEME
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www.jifactor.com



  WIDE-FREQUENCY-RANGE CMOS VOLTAGE CONTROLLED
     OSCILLATOR FOR PHASE LOCK LOOP – A REVIEW
                    Ms.Rashmi K Patil                Prof (Ms).Vrushali G Nasre
                   Asst.Prof.,B.D.C.E,           Asst.Prof.PG Dept of Electronics,
                   Sevagram,Wardha                 B.D.C.E, Sevagram,Wardha
                  Addr- Snehal Nagar,                    Addr-Ram Nagar,
               Wardha-442001,(MH)India             Wardha-442001,(MH)India
                Mobile no.-9096412073                  Mobile no.-9373201856
                rashmikpatil@gmail.com                vrushnasre@gmail.com


ABSTRACT

This paper describes a performance and comparison of a ring oscillator based VCO and
an LC oscillator based VCO.The VCO is intended to operate in a PLL to generate local
oscillator frequency (LO) for an acquisition system. This work proposes a differential
VCO design that has a wide operating frequency tuning range with reduced area, low
power consumption, , better phase-noise performance and good linearity between the
frequency and control voltage. The circuit is to be designed and simulated in 0.18µm
IBM CMOS technology.
Keywords
Voltage controlled oscillator, ring oscillator, CMOS, frequency stability, power
consumption.

1. INTRODUCTION

Phase-Locked Loops (PLLs) are widely used for clock generation in high-speed digital
systems. A Voltage-Controlled Oscillator (VCO) is a key component of

PLLs and is one of the most important basic building blocks in analog and digital circuits.
There are two different implementations of VCOs: a voltage-controlled ring oscillator
(ring VCO) and a voltage-controlled LC oscillator (LCVCO). A ring VCO has been
considered to be a better choice, because of its low power consumption, small chip area
and wide tunable frequency range. Recent increase in clock speed and the latest multi-

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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976
– 6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 1, January- June (2012), © IAEME
GHz serial link circuits, however, requires rigid jitter performance. The main reason of
ring oscillator popularity is a direct consequence of its easy integration. Due to their
integrated nature, ring oscillators have become an essential building block in many digital
and communication systems. A ring oscillator based VCO, is commonly used in the clock
generation subsystem. They are used as voltage controlled oscillators (VCO’s) in
applications such as clock recovery circuits for serial dat a communication [multi-GHz
serial link circuits, however, requires rigid jitter performance. The main reason of ring
oscillator popularity is a direct consequence of its easy integration. Due to their integrated
nature, ring oscillators have become an essential building block in many digital and
communication systems. A ring oscillator based VCO, is commonly used in the clock
generation subsystem. They are used as voltage controlled oscillators (VCO’s) in
applications such as clock recovery circuits for serial dat a communication[1], [2], disk-
drive read channels [3], on-chip clock distribution [4], and integrated frequency
synthesizers [5], [6]. The problem of designing a ring oscillator is in focus of our interest
in this paper. This paper proposes a suitable method for wide frequency range with
reduced area CMOS ring VCO.
   The rest of the text is organized as follows. In Section 2, we give a brief review of PLL
architecture. CMOS VCO review is given in Section 3. In addition we present the
comparative study and comparison between RING VCO and LC VCO in section 4 and
section 5.Proposed Methodology is given in section .6 Finally, conclusion is given in
Sections 7.

2. PLL ARCHITECTURE

The PLL architecture under our study is shown in Fig.1. A PLL is a closed-loop feedback
system that sets fixed phase relationship between its output clock phase and the phase of
a reference clock. A PLL tracks the phase changes that are within the bandwidth of the
PLL. A PLL also multiplies a low-frequency reference clock, to produce a high-
frequency clock. A PLL is a negative feedback control system circuit. As the name
implies, the purpose of a PLL is to generate a signal in which the phase is the same as the
phase of a reference signal. This is done after many iterations of comparing the reference
and feedback signals. The overall goal of the PLL is to match the reference and feedback
signals in phase, this is the lock mode. After this, the PLL continues to compare the two
signals but since they are in lock mode, the PLL output is constant.
It is composed of five major blocks: a phase-frequency detector (PFD), a charge pump, a
second order loop filter, a voltage controlled oscillator (VCO) and a divider. All the
components including the loop filter and the output buffer are integrated.




                                 Figure 1 PLL Architecture


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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976
– 6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 1, January- June (2012), © IAEME
The phase frequency detector (comparator) produces an error output signal based on the
phase difference between the phase of the feedback clock and the phase of the reference
clock. Over time, small frequency differences accumulate as an increasing phase error. If
there is a phase difference between the two signals, it generates “up” or “down”
synchronized signals to the charge pump/ low pass filter. If the error signal from the PFD
is an “up” signal, then the charge pump pumps charge onto the LPF capacitor which
increases the control voltage control V. On the contrary, if the error signal from the PFD
is a “down” signal, the charge pump removes charge from the LPF capacitor, which
decreases control V. Control V is the input to the VCO. Thus, the LPF is necessary to
only allow DC signals into the VCO and is also necessary to store the charge from the
CP. The purpose of the VCO is to either speed up or slow down the feedback signal
according to the error generated by the PFD. If the PFD generates an “up” signal, the
VCO speeds up. On the contrary, if a “down” signal is generated, the VCO slows down.
The frequency of oscillation is divided down to the feedback clock by a frequency
divider. The phase is locked when the feedback clock has a constant phase error and the
same frequency as the reference clock. Because the feedback clock is a divided version of
the oscillator‘s clock frequency, the frequency of oscillation is N times the reference
clock.

The designed ring VCO and LCVCO are shown in Fig. 2 and Fig. 3 respectively. The
ring VCO is five-stage differential inverters. The LCVCO is an NMOS cross-coupled
differential oscillator composed of two square-shaped spiral inductor and a differential
diode varactor.




                            Figure 2 Differential Ring Oscillator




                             Figure 3 Differential LC oscillator

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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976
– 6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 1, January- June (2012), © IAEME


3. CMOS VCO REVIEW
A Design Technique for low-voltage LC voltage-controlled oscillator (LCVCO) with a
wide tuning range and low sensitivity to process, voltage, and temperature (PVT)
variations [7] .For wide tuning range, a switched tuning scheme is employed coupled
with voltage-boosting techniques in a manner that improves the quality factor and tuning
range of a switched capacitor array. To minimize the design overhead required for a
robust VCO, an adaptive body-biasing technique is proposed, which relaxes the start-up
constraint and increases the VCO’s immunity to PVT variations. The proposed VCO is
implemented in 0.18µm CMOS technology and operates at 2.4 GHz. It achieves phase
noise of -117 dBc/Hz at 1MHz offset and a tuning range 20% while consuming 0.365mW
of power. The figure-of-merit with the tuning range is-197dBc/Hz, which is the lowest
among recent state-of-the-art low-voltage VCOs.[7]
A circuit topology suitable for low-power Colpitts LC voltage-controlled oscillators
(LCVCOs) [8] by employing the proposed voltage-to-current positive-feedback network;
the required transconductance for VCO start up can be reduced, leading to the minimized
dc power for sustaining VCO oscillation. Moreover, the Q factor enhanced varactor is
used in this VCO design for phase noise improvement. Based on the proposed
architecture, the fabricated VCO in standard 0.18 µm CMOS exhibits a 3.58% tuning
range. Operating at 1.35V supply voltage, the VCO core consumes 3.3mW dc power. The
measured phase noise is -110.82dBc/Hz at 1 MHz offset from 18.9 GHz oscillation
frequency. Compared with the recently published K-band 0.18µm CMOS VCOs, it is
observed that the proposed Colpitts VCO exhibits comparable circuit performance under
low dc power consumption.[8]
A digital phase-locked loop (DPLL) is designed [9] and is shown to have 1GHz operation
with lock time of 643.36ns .The ring VCO is composed of 7 cascaded inverters; the
inverter schematic. The lock time was reduced by adjusting the charge pump current and
the loop filter capacitor. There was a trade-off between the lock time, loop filter
capacitor, and ripples on the output of the VCO.[9]
A two-stage CMOS differential voltage-controlled ring oscillator (VCO) [10] is intended
to operate as a frequency synthesizer in a PLL to generate local oscillator frequency (LO)
for an acquisition system, providing in-phase/Q-phase outputs. This work proposes a
differential VCO design that has a wide operating frequency tuning range with low power
consumption, better phase-noise performance and good linearity between the frequency
and control voltage. The circuit is implemented in 0.18 µm CMOS Process operates at
frequency: 186 MHz to 1.58 GHz. The DC Supply of 1.8 V is applied and dissipates
11.38 mW of power. The Phase noise is -113.5 dBc/Hz.[10]
A low-phase-noise ring-VCO-based PLL (frequency tuning range: 0.65-1.6 GHz ) with
subharmonic injection locking was realized [11] (PLL area: 0.1 mm2) by adopting
0.18µm CMOS technology and combining pMOS resistive loads with a circuit for
shifting bias levels; this makes the rail-to-rail range of voltages usable as control
voltages. For a 90-MHz input reference signal, without injection locking, the 0.2MHz-
offset phase noise was -108 dBc/Hz (PLL output frequency: 1.44GHz = 16 X 90MHz);

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 International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976
 – 6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 1, January- June (2012), © IAEME
 with injection locking, the noise was -122 dBc/Hz (spurious level: -35 dBc; power
 consumption from a 1.8V power supply: 39mW.[11]


 4. COMPARATIVE STUDY
                                              Table.1
Parameters        [7]          [8]            [9]             [10]           [11]

Technology     0.18µm       0.18µm          0.18µm          0.18µm         0.18µm

Frequency      2.4GHz      18.95GHz          1GHz         186MHz-         1.44GHz
                                                          1.s58GHz

I/P Tuning      0-0.5V        0-2V          0-0.9V          0-1.8V         0-1.8V
  Range

  Power        0.365m        3.3mw             -           11.38mw          39mw
Dissipation       w

   Area         0.31m      0.239mm2          Small        0.00252m         0.1mm2
                  m2                                         m2

Phase Noise       -            -               -              -              -
               117dBc      110.82dB                       113.5dBc/      122dBc/Hz
                 /Hz         c/Hz                            Hz



 5. Comparison between RING VCO based PLL and LC VCO based PLL
 Tuning range: In RING VCO Tuning range is very wide due to current variation while
 in LC based VCO it is narrow, proportional to the square root of varactor tuning.
 Phase noise: In RING VCO phase noise is very poor, while in LC based VCO it is very
 good, filtering inherent to LC tank.
 Power consumption: In RING VCO Power consumption can vary greatly. Higher power
 is needed for good phase noise. While in LC based VCO power consumption is greater
 than ring VCO with equivalent frequency coverage but consumes lower power for same
 phase noise.
 Gain: In RING VCO it is high, sensitive to power supply noise injection, not suitable for
 SONET transmit clocks, poor stability at high frequency. While in LC based VCO it is
 Low, very sensitive to supply source variations and noise injection.
 Layout: In RING VCO area is small while LC based VCO requires large area due to the
 requirement of inductor. Also it requires a lot of characterization, poor integration and
 more complicated to design.



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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976
– 6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 1, January- June (2012), © IAEME




Figure 4 Approximate area required for LC and Ring VCO

6. PROPOSED METHEDOLOGY


In 0.18µm technology, design VCO using CMOS differential voltage-controlled ring
oscillator for finding the area efficient CMOS ring VCO to reduce the overall area of
PLL. O/P Frequency of VCO must up to 1GHz for tuning the PFD. Also to avoid large
area, the W/L ratio of transistor can be varied to minimize the severity of problem.
Implementation can be done by the available tools like Tanner, ADS, etc. Later on
verification and testing will be done by matching the mathematical calculation and the
result of the simulation.
7. CONCLUSION

RING VCO is a common approach for digital chips. There are many ways to control
frequency, multiphase clock generation, wide frequency tuning range, Low power/area at
low frequency while in LC based VCO it is common approach for RF design .It is having
Good stability. The tunable and flexible bandwidth criterion combined with low-noise
Characteristics, low power, and small-area properties are the main concern of industrial
engineers in designing and choosing a proper resonator topology suitable for their
respective applications.
The design goal of a wide range, low power consumption VCO can be successfully
achieved. Therefore, a robust VCO can be designed for reliable operation. The techniques
proposed in this paper can be applied to other low voltage analog and RF circuits to
improve their performance.




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International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976
– 6464(Print), ISSN 0976 – 6472(Online) Volume 3, Issue 1, January- June (2012), © IAEME
REFERENCES

[1] C. H. PARK, O. KIM, B. KIM, A 1.8-GHz self-calibrated phase locked loop with
precise I/Q matching, IEEE J. Solid-State Circuits, vol. 36, (2001), 777-783.

[2] L. SUN AND T. A. KWASNIEWSKI, A 1.25-GHz 0.35- m monolithic CMOS PLL
based on a multiphase ring oscillator, IEEE J. Solid-State Circuits, vol. 36, (2001), 910-
916.

[3] J. SAVOJ AND B. RAZAVI, A 10-Gb/s CMOS clock and data recovery circuit with
a half-rate linear phase detector, IEEE J. Solid-State Circuits, vol. 36, (2001), 761-767

[4] C. K. K. YANG, R. FARJAD-RAD, M. A. HOROWITZ, A 0.5- m CMOS 4.0-Gbit/s
serial link transceiver with data recovery using oversampling, IEEE J. Solid-State
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[5] M. ALIOTO, G. PALUMBO,”Oscillation frequency in CML and ESCL ring
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[6] B. RAZAVI, A 2-GHz 1.6-mW phase-locked loop, IEEE J. Solid-State Circuits, vol.
32,(1997), 730-735.

[7] Dongmin Park, et al, “Design techniques for low voltage VCO with wide tuning range
and low sensitivity to environmental variations”, in IEEE Transaction on Microwave
Theory and Techniques, vol. 57, no. 4, April 2009, pp 767 – 774.

[8] To-Po Wang, “A k-band low power colpitts VCO with voltage to current positive
feedback network in 0.18 µm CMOS,” in IEEE on Microwave and Wireless Components
Letters, vol. 21, no. 4, April 2011, pp 218 – 220.
[9] Haripriya Janardhan,Mahmoud Fawzy Wagdy, “Design of a 1GHz Digital PLLUsing
0.18µm CMOS Technology” in IEEE 2006 Third International Conference on
Information Technology: New Generations (ITNG'06)
[10] Luciano Severino de Paula, Eric Fabris, Sergio Bampi, Altamiro Amadeu Susin,” A
High Swing Low Power CMOS Differential Voltage-Controlled Ring Oscillator”in 2007
IEEE Computer Society Annual Symposium on VLSI(ISVLSI'07)

[11] Sang_yeop Lee, Shuhei Amakawa, Noboru Ishihara, and Kazuya Masu,” Low-
Phase-Noise Wide-Frequency-Range Ring-VCO-Based Scalable PLL with Subharmonic
Injection Locking in 0.18 µm CMOS”,in,IEEE2010.




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