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					                                    Design Essentials
               Design Rules Proposed - Transistor Level
                 Design Rules Proposed - Circuit Level
                              LDPC Analogue Decoder
                                          Conclusions




       Design Rules for Subthreshold MOS Circuits

                         Jorge Pérez Chamorro, Cyril Lahuec,
                         Fabrice Seguin and Michel Jézéquel




                 5th Analogue Decoding Workshop, Torino, Italy


J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                  Design Rules Proposed - Circuit Level
                               LDPC Analogue Decoder
                                           Conclusions


Outline
    1    Design Essentials
           Motivation
           Models for Circuit Simulation
           Substrate Bias (VSB ) and Other Parameters
    2    Design Rules Proposed - Transistor Level
           Setting VSB to 0
           Fabrication Process
    3    Design Rules Proposed - Circuit Level
           Topology’s Choice: Current or Voltage Mode?
           Symmetry
           Fixing Voltages
    4    LDPC Analogue Decoder
           Subthreshold MOS Gilbert-based Cells
           The Decoder
 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Motivation
                  Design Rules Proposed - Circuit Level    Models for Circuit Simulation
                               LDPC Analogue Decoder       Substrate Bias (VSB ) and Other Parameters
                                           Conclusions


Outline
    1    Design Essentials
           Motivation
           Models for Circuit Simulation
           Substrate Bias (VSB ) and Other Parameters
    2    Design Rules Proposed - Transistor Level
           Setting VSB to 0
           Fabrication Process
    3    Design Rules Proposed - Circuit Level
           Topology’s Choice: Current or Voltage Mode?
           Symmetry
           Fixing Voltages
    4    LDPC Analogue Decoder
           Subthreshold MOS Gilbert-based Cells
           The Decoder
 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                    Design Essentials
               Design Rules Proposed - Transistor Level   Motivation
                 Design Rules Proposed - Circuit Level    Models for Circuit Simulation
                              LDPC Analogue Decoder       Substrate Bias (VSB ) and Other Parameters
                                          Conclusions


Why Analogue CMOS?


           Why Analogue?
                  Better performance than digital counterparts.
                  No iterations and parallelism.
                  Simpler implementation of basic operators.
           Why Subthreshold MOSFET?
                  Less consuming than forward-biased BJT.
                  Low-voltage supply and nano-currents.
                  Easier and cheaper fabrication.
           But . . .
                  Hard to control and to interconnect.



J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                    Design Essentials
               Design Rules Proposed - Transistor Level   Motivation
                 Design Rules Proposed - Circuit Level    Models for Circuit Simulation
                              LDPC Analogue Decoder       Substrate Bias (VSB ) and Other Parameters
                                          Conclusions


Why Analogue CMOS?


           Why Analogue?
                  Better performance than digital counterparts.
                  No iterations and parallelism.
                  Simpler implementation of basic operators.
           Why Subthreshold MOSFET?
                  Less consuming than forward-biased BJT.
                  Low-voltage supply and nano-currents.
                  Easier and cheaper fabrication.
           But . . .
                  Hard to control and to interconnect.



J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                    Design Essentials
               Design Rules Proposed - Transistor Level   Motivation
                 Design Rules Proposed - Circuit Level    Models for Circuit Simulation
                              LDPC Analogue Decoder       Substrate Bias (VSB ) and Other Parameters
                                          Conclusions


Why Analogue CMOS?


           Why Analogue?
                  Better performance than digital counterparts.
                  No iterations and parallelism.
                  Simpler implementation of basic operators.
           Why Subthreshold MOSFET?
                  Less consuming than forward-biased BJT.
                  Low-voltage supply and nano-currents.
                  Easier and cheaper fabrication.
           But . . .
                  Hard to control and to interconnect.



J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Motivation
                  Design Rules Proposed - Circuit Level    Models for Circuit Simulation
                               LDPC Analogue Decoder       Substrate Bias (VSB ) and Other Parameters
                                           Conclusions


Outline
    1    Design Essentials
           Motivation
           Models for Circuit Simulation
           Substrate Bias (VSB ) and Other Parameters
    2    Design Rules Proposed - Transistor Level
           Setting VSB to 0
           Fabrication Process
    3    Design Rules Proposed - Circuit Level
           Topology’s Choice: Current or Voltage Mode?
           Symmetry
           Fixing Voltages
    4    LDPC Analogue Decoder
           Subthreshold MOS Gilbert-based Cells
           The Decoder
 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level     Motivation
                  Design Rules Proposed - Circuit Level      Models for Circuit Simulation
                               LDPC Analogue Decoder         Substrate Bias (VSB ) and Other Parameters
                                           Conclusions


Models for Circuit Simulation
BSIM3v3 vs. MM9 - Average Errors between Measurements and Simulations [3]

            BSIM3 is a public-domain set conceived at the University
            of California, Berkeley [1].
            MOS Model 9 is an analytical model for analogue
            applications developed by Philips [2].

                               Model                                         BSIM3v3               MM9
                          subthreshold                     VSB = 0V           11.6%                8.0%
                             region                        VSB = 0V           17.6%               17.0%
        NMOS            substrate current                                     29.8%               23.0%
                          subthreshold                     VSB = 0V           10.1%                6.0%
                             region                        VSB = 0V           20.0%               17.0%
        PMOS            substrate current                                     50.3%               25.0%

 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                    Design Essentials
               Design Rules Proposed - Transistor Level   Motivation
                 Design Rules Proposed - Circuit Level    Models for Circuit Simulation
                              LDPC Analogue Decoder       Substrate Bias (VSB ) and Other Parameters
                                          Conclusions


MOS Model 9




                 MM9 inside
           Philips Semiconductors


J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Motivation
                  Design Rules Proposed - Circuit Level    Models for Circuit Simulation
                               LDPC Analogue Decoder       Substrate Bias (VSB ) and Other Parameters
                                           Conclusions


Outline
    1    Design Essentials
           Motivation
           Models for Circuit Simulation
           Substrate Bias (VSB ) and Other Parameters
    2    Design Rules Proposed - Transistor Level
           Setting VSB to 0
           Fabrication Process
    3    Design Rules Proposed - Circuit Level
           Topology’s Choice: Current or Voltage Mode?
           Symmetry
           Fixing Voltages
    4    LDPC Analogue Decoder
           Subthreshold MOS Gilbert-based Cells
           The Decoder
 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level                   Motivation
                  Design Rules Proposed - Circuit Level                    Models for Circuit Simulation
                               LDPC Analogue Decoder                       Substrate Bias (VSB ) and Other Parameters
                                           Conclusions


Substrate Bias (VSB )
Calculated and measured NMOS subthreshold characteristics [4]

                                   10-3


                                   10-4

                                                                                                     VSB=5V
                                   10-5


                                   10-6
                    IDS_NMOS[A]




                                   10-7


                                   10-8                        VSB=2V


                                   10-9                                                              VDS=1.0V

                                                                                                         VDS=3.5V
                                  10-10
                                                                                                         VDS=6.0V
                                  10-11         VSB=0V


                                  10-12
                                          0.1      0.3   0.5        0.7          0.9     1.1       1.3              1.5
                                                                   VGS_NMOS[V]



 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level                  Motivation
                  Design Rules Proposed - Circuit Level                   Models for Circuit Simulation
                               LDPC Analogue Decoder                      Substrate Bias (VSB ) and Other Parameters
                                           Conclusions


Substrate Bias (VSB )
Calculated and measured PMOS subthreshold characteristics [4]

                                    10-4


                                    10-5


                                    10-6


                                    10-7
                    -IDS_PMOS[A]




                                    10-8

                                                                                                 VDS=-1.0V
                                    10-9

                                                                                                 VDS=-3.5V
                                   10-10
                                                                                                 VDS=-6.0V

                                   10-11

                                                 VSB=0V         VSB=-2V
                                   10-12


                                   10-13
                                           0.5     0.7    0.9   1.1       1.3     1.5      1.7        1.9    2.1
                                                                  -VGS_PMOS[V]



 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Motivation
                  Design Rules Proposed - Circuit Level    Models for Circuit Simulation
                               LDPC Analogue Decoder       Substrate Bias (VSB ) and Other Parameters
                                           Conclusions


Other Effects and Relevant Parameters



       1    Spreading Effect
       2    Subthreshold Slope (m)
       3    Drain-Induced Barrier Lowering (DIBL) Effect
       4    VDS




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Motivation
                  Design Rules Proposed - Circuit Level    Models for Circuit Simulation
                               LDPC Analogue Decoder       Substrate Bias (VSB ) and Other Parameters
                                           Conclusions


Other Effects and Relevant Parameters


       1    Spreading Effect :
                   Vertical shifts of IDS due to changes of VDS .
                   Horizontal shifts of IDS due to changes of VSB .
                   Inversely Proportional to Channel Doping.
       2    Subthreshold Slope (m)
       3    Drain-Induced Barrier Lowering (DIBL) Effect
       4    VDS




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Motivation
                  Design Rules Proposed - Circuit Level    Models for Circuit Simulation
                               LDPC Analogue Decoder       Substrate Bias (VSB ) and Other Parameters
                                           Conclusions


Other Effects and Relevant Parameters



       1    Spreading Effect
       2    Subthreshold Slope (m)
       3    Drain-Induced Barrier Lowering (DIBL) Effect
       4    VDS




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Motivation
                  Design Rules Proposed - Circuit Level    Models for Circuit Simulation
                               LDPC Analogue Decoder       Substrate Bias (VSB ) and Other Parameters
                                           Conclusions


Other Effects and Relevant Parameters


       1    Spreading Effect
       2    Subthreshold Slope (m) :
                   Variation of the depletion charge with respect to the surface
                   potential.
                   Constant if and only if VSB = 0.
       3    Drain-Induced Barrier Lowering (DIBL) Effect
       4    VDS




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Motivation
                  Design Rules Proposed - Circuit Level    Models for Circuit Simulation
                               LDPC Analogue Decoder       Substrate Bias (VSB ) and Other Parameters
                                           Conclusions


Other Effects and Relevant Parameters



       1    Spreading Effect
       2    Subthreshold Slope (m)
       3    Drain-Induced Barrier Lowering (DIBL) Effect
       4    VDS




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Motivation
                  Design Rules Proposed - Circuit Level    Models for Circuit Simulation
                               LDPC Analogue Decoder       Substrate Bias (VSB ) and Other Parameters
                                           Conclusions


Other Effects and Relevant Parameters


       1    Spreading Effect
       2    Subthreshold Slope (m)
       3    Drain-Induced Barrier Lowering (DIBL) Effect :
                   Reduction of VT due to an increase of VDS .
                   Short Channel Effect.
                   Relates: the oxide thickness, the substrate doping, the
                   junction depth and the channel length.
       4    VDS




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Motivation
                  Design Rules Proposed - Circuit Level    Models for Circuit Simulation
                               LDPC Analogue Decoder       Substrate Bias (VSB ) and Other Parameters
                                           Conclusions


Other Effects and Relevant Parameters



       1    Spreading Effect
       2    Subthreshold Slope (m)
       3    Drain-Induced Barrier Lowering (DIBL) Effect
       4    VDS




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Motivation
                  Design Rules Proposed - Circuit Level    Models for Circuit Simulation
                               LDPC Analogue Decoder       Substrate Bias (VSB ) and Other Parameters
                                           Conclusions


Other Effects and Relevant Parameters



       1    Spreading Effect
       2    Subthreshold Slope (m)
       3    Drain-Induced Barrier Lowering (DIBL) Effect
       4    VDS is related to:
                   The depletion charge under the drain end of the channel.
                   The drain current and its saturation voltage.




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Motivation
                  Design Rules Proposed - Circuit Level    Models for Circuit Simulation
                               LDPC Analogue Decoder       Substrate Bias (VSB ) and Other Parameters
                                           Conclusions


Other Effects and Relevant Parameters



       1    Spreading Effect
       2    Subthreshold Slope (m)
       3    Drain-Induced Barrier Lowering (DIBL) Effect
       4    VDS




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                           Setting VSB to 0
                  Design Rules Proposed - Circuit Level
                                                           Fabrication Process
                               LDPC Analogue Decoder
                                           Conclusions


Outline
    1    Design Essentials
           Motivation
           Models for Circuit Simulation
           Substrate Bias (VSB ) and Other Parameters
    2    Design Rules Proposed - Transistor Level
           Setting VSB to 0
           Fabrication Process
    3    Design Rules Proposed - Circuit Level
           Topology’s Choice: Current or Voltage Mode?
           Symmetry
           Fixing Voltages
    4    LDPC Analogue Decoder
           Subthreshold MOS Gilbert-based Cells
           The Decoder
 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                           Setting VSB to 0
                  Design Rules Proposed - Circuit Level
                                                           Fabrication Process
                               LDPC Analogue Decoder
                                           Conclusions


First, some equations


                                                                       ηm
                    m = 1 + mo                φb / VSB + φb                            (1)
                                                                    ηγ
        ∆VT ,DIBL = −γoo                   VSB + φb / φb                 VDS           (2)
                    IS = 2mµo Cox (W /L) φ2
                                          T                                            (3)
                   IC = IDS /IS                                                        (4)
                                    W       Vgt2                                 VDS
                  IDS = φT µ          Q exp                          1 − exp −         (5)
                                    L iO    mφT                                  φT




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                           Setting VSB to 0
                  Design Rules Proposed - Circuit Level
                                                           Fabrication Process
                               LDPC Analogue Decoder
                                           Conclusions


First, some equations


                                                                       ηm
                    m = 1 + mo                φb / VSB + φb                            (1)
                                                                    ηγ
        ∆VT ,DIBL = −γoo                   VSB + φb / φb                 VDS           (2)
                    IS = 2mµo Cox (W /L) φ2
                                          T                                            (3)
                   IC = IDS /IS                                                        (4)
                                    W       Vgt2                                 VDS
                  IDS = φT µ          Q exp                          1 − exp −         (5)
                                    L iO    mφT                                  φT




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                           Setting VSB to 0
                  Design Rules Proposed - Circuit Level
                                                           Fabrication Process
                               LDPC Analogue Decoder
                                           Conclusions


First, some equations


                                                                       ηm
                    m = 1 + mo                φb / VSB + φb                            (1)
                                                                    ηγ
        ∆VT ,DIBL = −γoo                   VSB + φb / φb                 VDS           (2)
                    IS = 2mµo Cox (W /L) φ2
                                          T                                            (3)
                   IC = IDS /IS                                                        (4)
                                    W       Vgt2                                 VDS
                  IDS = φT µ          Q exp                          1 − exp −         (5)
                                    L iO    mφT                                  φT




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                           Setting VSB to 0
                  Design Rules Proposed - Circuit Level
                                                           Fabrication Process
                               LDPC Analogue Decoder
                                           Conclusions


First, some equations


                                                                       ηm
                    m = 1 + mo                φb / VSB + φb                            (1)
                                                                    ηγ
        ∆VT ,DIBL = −γoo                   VSB + φb / φb                 VDS           (2)
                    IS = 2mµo Cox (W /L) φ2
                                          T                                            (3)
                   IC = IDS /IS                                                        (4)
                                    W       Vgt2                                 VDS
                  IDS = φT µ          Q exp                          1 − exp −         (5)
                                    L iO    mφT                                  φT




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                           Setting VSB to 0
                  Design Rules Proposed - Circuit Level
                                                           Fabrication Process
                               LDPC Analogue Decoder
                                           Conclusions


First, some equations


                                                                       ηm
                    m = 1 + mo                φb / VSB + φb                            (1)
                                                                    ηγ
        ∆VT ,DIBL = −γoo                   VSB + φb / φb                 VDS           (2)
                    IS = 2mµo Cox (W /L) φ2
                                          T                                            (3)
                   IC = IDS /IS                                                        (4)
                                    W       Vgt2                                 VDS
                  IDS = φT µ          Q exp                          1 − exp −         (5)
                                    L iO    mφT                                  φT




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                           Setting VSB to 0
                  Design Rules Proposed - Circuit Level
                                                           Fabrication Process
                               LDPC Analogue Decoder
                                           Conclusions


First, some equations


                                                                       ηm
                    m = 1 + mo                φb / VSB + φb                            (1)
                                                                    ηγ
        ∆VT ,DIBL = −γoo                   VSB + φb / φb                 VDS           (2)
                    IS = 2mµo Cox (W /L) φ2
                                          T                                            (3)
                   IC = IDS /IS                                                        (4)
                                    W       Vgt2                                 VDS
                  IDS = φT µ          Q exp                          1 − exp −         (5)
                                    L iO    mφT                                  φT




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                           Setting VSB to 0
                  Design Rules Proposed - Circuit Level
                                                           Fabrication Process
                               LDPC Analogue Decoder
                                           Conclusions


Setting VSB to 0.


                                 Simplifying the Physics,
                                 not the Model:

                                                  m = 1 + mo                (6)
                                       ∆VT ,DIBL = −γoo VDS                 (7)




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                           Setting VSB to 0
                  Design Rules Proposed - Circuit Level
                                                           Fabrication Process
                               LDPC Analogue Decoder
                                           Conclusions


Setting VSB to 0.


                                 Simplifying the Physics,
                                 not the Model:

                                                  m = 1 + mo                (6)
                                       ∆VT ,DIBL = −γoo VDS                 (7)




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                           Setting VSB to 0
                  Design Rules Proposed - Circuit Level
                                                           Fabrication Process
                               LDPC Analogue Decoder
                                           Conclusions


Setting VSB to 0.

                                 Simplifying the Physics,
                                 not the Model:

                                                  m = 1 + mo                (6)
                                       ∆VT ,DIBL = −γoo VDS                 (7)




                                 Result
                                 Optimal equations non
                                 dependent on VSB nor φB .


 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                              Setting VSB to 0
                  Design Rules Proposed - Circuit Level
                                                              Fabrication Process
                               LDPC Analogue Decoder
                                           Conclusions


Setting VSB to 0.

Simplifying the Physics,                                   Determining the transistor’s size,
not the Model:                                             a clear equation:

                 m = 1 + mo                   (6)            W              IDSMAX
                                                                =                            (8)
     ∆VT ,DIBL = −γoo VDS                     (7)            L     2IC (1 + mo ) µo Cox φ2
                                                                                         T
                                                                            µ o φT
                                                               fTmax,weak <                  (9)
                                                                             πL2


Result
Optimal equations non
dependent on VSB nor φB .


 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                              Setting VSB to 0
                  Design Rules Proposed - Circuit Level
                                                              Fabrication Process
                               LDPC Analogue Decoder
                                           Conclusions


Setting VSB to 0.

Simplifying the Physics,                                   Determining the transistor’s size,
not the Model:                                             a clear equation:

                 m = 1 + mo                   (6)            W              IDSMAX
                                                                =                            (8)
     ∆VT ,DIBL = −γoo VDS                     (7)            L     2IC (1 + mo ) µo Cox φ2
                                                                                         T
                                                                            µ o φT
                                                               fTmax,weak <                  (9)
                                                                             πL2


Result                                                     Result
Optimal equations non                                      IDSMAX , IC and fTmax,weak became the
dependent on VSB nor φB .                                  only design variables.


 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                           Setting VSB to 0
                  Design Rules Proposed - Circuit Level
                                                           Fabrication Process
                               LDPC Analogue Decoder
                                           Conclusions


Outline
    1    Design Essentials
           Motivation
           Models for Circuit Simulation
           Substrate Bias (VSB ) and Other Parameters
    2    Design Rules Proposed - Transistor Level
           Setting VSB to 0
           Fabrication Process
    3    Design Rules Proposed - Circuit Level
           Topology’s Choice: Current or Voltage Mode?
           Symmetry
           Fixing Voltages
    4    LDPC Analogue Decoder
           Subthreshold MOS Gilbert-based Cells
           The Decoder
 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                           Setting VSB to 0
                  Design Rules Proposed - Circuit Level
                                                           Fabrication Process
                               LDPC Analogue Decoder
                                           Conclusions


Choosing the Fabrication Process
QUBiC4 CMOS Transistors’ Parameters


            Possibility of independent bulk-source connections.
            Maximal channel doping produces minimal spreading
            effect.
      Constant                     (units)                             NMOS         PMOS
         γoo                         (-)                             36.67E-3     18.11E-3
        Cox                          (F)                              5.75E-3      5.57E-3
         mo                          (-)                            374.60E-3    536.70E-3
         Ns                    (cm−3 ), a > 1                               X          aX
        W /L              IC = 0.03, IDSMAX = 1µA                        67.7         62.5
      fTmax,weak                 L = 0.4µm                           4.78GHz      4.78GHz



 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                           Setting VSB to 0
                  Design Rules Proposed - Circuit Level
                                                           Fabrication Process
                               LDPC Analogue Decoder
                                           Conclusions


Choosing the Fabrication Process
QUBiC4 CMOS Transistors’ Parameters


            Possibility of independent bulk-source connections.
            Maximal channel doping produces minimal spreading
            effect.
      Constant                     (units)                             NMOS         PMOS
         γoo                         (-)                             36.67E-3     18.11E-3
        Cox                          (F)                              5.75E-3      5.57E-3
         mo                          (-)                            374.60E-3    536.70E-3
         Ns                    (cm−3 ), a > 1                               X          aX
        W /L              IC = 0.03, IDSMAX = 1µA                        67.7         62.5
      fTmax,weak                 L = 0.4µm                           4.78GHz      4.78GHz



 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                           Setting VSB to 0
                  Design Rules Proposed - Circuit Level
                                                           Fabrication Process
                               LDPC Analogue Decoder
                                           Conclusions


Choosing the Fabrication Process
QUBiC4 CMOS Transistors’ Parameters


            Possibility of independent bulk-source connections.
            Maximal channel doping produces minimal spreading
            effect.
      Constant                     (units)                             NMOS         PMOS
         γoo                         (-)                             36.67E-3     18.11E-3
        Cox                          (F)                              5.75E-3      5.57E-3
         mo                          (-)                            374.60E-3    536.70E-3
         Ns                    (cm−3 ), a > 1                               X          aX
        W /L              IC = 0.03, IDSMAX = 1µA                        67.7         62.5
      fTmax,weak                 L = 0.4µm                           4.78GHz      4.78GHz



 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                                              Setting VSB to 0
                  Design Rules Proposed - Circuit Level
                                                                              Fabrication Process
                               LDPC Analogue Decoder
                                           Conclusions


The Transistors
L = 0.4µm, WN = 27.1µm, WP = 25.0µm, fTmax = 4.78GHz

                                                                    -VGS_PMOS[V]
                                         0.0            0.2   0.4                  0.6        0.8           1.0
                                  10-3                                                                             10-3


                                  10-4                                                                             10-4


                                  10-5                                                                             10-5
                                               IDSMAX
                                    -6
                                  10                                                                               10-6
                   IDS_NMOS[A]




                                                                                                                          -IDS_PMOS[A]
                                  10-7                                                   NMOS, V_DS=0.1V           10-7
                                                                                         NMOS, V_DS=0.2V
                                                               NMOS                      NMOS, V_DS=0.3V
                                  10-8                                                   NMOS, V_DS=0.4V           10-8
                                                                                         NMOS, V_DS=0.5V
                                                  PMOS                                   NMOS, V_DS=0.6V
                                  10-9                                                   PMOS, V_DS=-0.1V          10-9
                                                                                         PMOS, V_DS=-0.2V
                                                                                         PMOS, V_DS=-0.3V
                                 10-10                                                   PMOS, V_DS=-0.4V         10-10
                                                                                         PMOS, V_DS=-0.5V
                                                                                         PMOS, V_DS=-0.6V
                                 10-11                                                                            10-11


                                 10-12                                                                            10-12
                                         0.0            0.2   0.4                  0.6        0.8           1.0
                                                                    VGS_NMOS[V]



 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                           Setting VSB to 0
                  Design Rules Proposed - Circuit Level
                                                           Fabrication Process
                               LDPC Analogue Decoder
                                           Conclusions


A PMOS Topology
Why?



        Half the NMOS’ γoo then Half variation on VT
        caused by DIBL.




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                           Setting VSB to 0
                  Design Rules Proposed - Circuit Level
                                                           Fabrication Process
                               LDPC Analogue Decoder
                                           Conclusions


A PMOS Topology
Why?



        Half the NMOS’ γoo then Half variation on VT
        caused by DIBL.

        Maximum Channel doping then minimum spreading effect.




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                           Setting VSB to 0
                  Design Rules Proposed - Circuit Level
                                                           Fabrication Process
                               LDPC Analogue Decoder
                                           Conclusions


A PMOS Topology
Why?



        Half the NMOS’ γoo then Half variation on VT
        caused by DIBL.

        Maximum Channel doping then minimum spreading effect.

        Independent bulk-source connections possible
        for all transistors so VSB = 0.




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                           Setting VSB to 0
                  Design Rules Proposed - Circuit Level
                                                           Fabrication Process
                               LDPC Analogue Decoder
                                           Conclusions


A PMOS Topology
Why?



        Half the NMOS’ γoo then Half variation on VT
        caused by DIBL.

        Maximum Channel doping then minimum spreading effect.

        Independent bulk-source connections possible
        for all transistors so VSB = 0.

        Minimum expected error between Measurements
        and Simulations using the MM9.



 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                  Design Rules Proposed - Circuit Level    Symmetry
                               LDPC Analogue Decoder       Fixing Voltages
                                           Conclusions


Outline
    1    Design Essentials
           Motivation
           Models for Circuit Simulation
           Substrate Bias (VSB ) and Other Parameters
    2    Design Rules Proposed - Transistor Level
           Setting VSB to 0
           Fabrication Process
    3    Design Rules Proposed - Circuit Level
           Topology’s Choice: Current or Voltage Mode?
           Symmetry
           Fixing Voltages
    4    LDPC Analogue Decoder
           Subthreshold MOS Gilbert-based Cells
           The Decoder
 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                  Design Rules Proposed - Circuit Level    Symmetry
                               LDPC Analogue Decoder       Fixing Voltages
                                           Conclusions


Current Mode - Existing Topologies




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                  Design Rules Proposed - Circuit Level    Symmetry
                               LDPC Analogue Decoder       Fixing Voltages
                                           Conclusions


Current Mode - Existing Topologies




        Many domain changes required.




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                  Design Rules Proposed - Circuit Level    Symmetry
                               LDPC Analogue Decoder       Fixing Voltages
                                           Conclusions


Current Mode - Existing Topologies




        Many domain changes required.
        Renormalisation is mandatory.




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                  Design Rules Proposed - Circuit Level    Symmetry
                               LDPC Analogue Decoder       Fixing Voltages
                                           Conclusions


Current Mode - Existing Topologies




        Many domain changes required.
        Renormalisation is mandatory.
        Hard memory effect.




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                  Design Rules Proposed - Circuit Level    Symmetry
                               LDPC Analogue Decoder       Fixing Voltages
                                           Conclusions


Current Mode - Existing Topologies




        Many domain changes required.
        Renormalisation is mandatory.
        Hard memory effect.

        Easy CMOS implementation.



 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                  Design Rules Proposed - Circuit Level    Symmetry
                               LDPC Analogue Decoder       Fixing Voltages
                                           Conclusions


Voltage Mode - Existing Topologies




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                  Design Rules Proposed - Circuit Level    Symmetry
                               LDPC Analogue Decoder       Fixing Voltages
                                           Conclusions


Voltage Mode - Existing Topologies




        Bipolar generally.




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                  Design Rules Proposed - Circuit Level    Symmetry
                               LDPC Analogue Decoder       Fixing Voltages
                                           Conclusions


Voltage Mode - Existing Topologies




        Bipolar generally.
        Inaccurate if only CMOS.




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                  Design Rules Proposed - Circuit Level    Symmetry
                               LDPC Analogue Decoder       Fixing Voltages
                                           Conclusions


Voltage Mode - Existing Topologies




        Bipolar generally.
        Inaccurate if only CMOS.
        Subthreshold MOS transistors quite hard to control.




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                  Design Rules Proposed - Circuit Level    Symmetry
                               LDPC Analogue Decoder       Fixing Voltages
                                           Conclusions


Voltage Mode - Existing Topologies




        Bipolar generally.
        Inaccurate if only CMOS.
        Subthreshold MOS transistors quite hard to control.

        No renormalisation needed.




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                  Design Rules Proposed - Circuit Level    Symmetry
                               LDPC Analogue Decoder       Fixing Voltages
                                           Conclusions


Voltage Mode - Existing Topologies




        Bipolar generally.
        Inaccurate if only CMOS.
        Subthreshold MOS transistors quite hard to control.

        No renormalisation needed.
        Weaker memory effect.



 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                    Design Essentials
               Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                 Design Rules Proposed - Circuit Level    Symmetry
                              LDPC Analogue Decoder       Fixing Voltages
                                          Conclusions


Proposed Topology

       Voltage Mode.




J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                    Design Essentials
               Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                 Design Rules Proposed - Circuit Level    Symmetry
                              LDPC Analogue Decoder       Fixing Voltages
                                          Conclusions


Proposed Topology

       Voltage Mode.
       Subthreshold CMOS.




J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                    Design Essentials
               Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                 Design Rules Proposed - Circuit Level    Symmetry
                              LDPC Analogue Decoder       Fixing Voltages
                                          Conclusions


Proposed Topology

       Voltage Mode.
       Subthreshold CMOS.


       Low-voltage supply.




J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                    Design Essentials
               Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                 Design Rules Proposed - Circuit Level    Symmetry
                              LDPC Analogue Decoder       Fixing Voltages
                                          Conclusions


Proposed Topology

       Voltage Mode.
       Subthreshold CMOS.


       Low-voltage supply.
       Domain Changes kept at the minimum.




J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                    Design Essentials
               Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                 Design Rules Proposed - Circuit Level    Symmetry
                              LDPC Analogue Decoder       Fixing Voltages
                                          Conclusions


Proposed Topology

       Voltage Mode.
       Subthreshold CMOS.


       Low-voltage supply.
       Domain Changes kept at the minimum.
       No renormalisation - No convergence to 0.




J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                    Design Essentials
               Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                 Design Rules Proposed - Circuit Level    Symmetry
                              LDPC Analogue Decoder       Fixing Voltages
                                          Conclusions


Proposed Topology

       Voltage Mode.
       Subthreshold CMOS.


       Low-voltage supply.
       Domain Changes kept at the minimum.
       No renormalisation - No convergence to 0.
       Weak memory effect.




J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                    Design Essentials
               Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                 Design Rules Proposed - Circuit Level    Symmetry
                              LDPC Analogue Decoder       Fixing Voltages
                                          Conclusions


Proposed Topology

       Voltage Mode.
       Subthreshold CMOS.


       Low-voltage supply.
       Domain Changes kept at the minimum.
       No renormalisation - No convergence to 0.
       Weak memory effect.
       Accuracy.


J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                  Design Rules Proposed - Circuit Level    Symmetry
                               LDPC Analogue Decoder       Fixing Voltages
                                           Conclusions


Outline
    1    Design Essentials
           Motivation
           Models for Circuit Simulation
           Substrate Bias (VSB ) and Other Parameters
    2    Design Rules Proposed - Transistor Level
           Setting VSB to 0
           Fabrication Process
    3    Design Rules Proposed - Circuit Level
           Topology’s Choice: Current or Voltage Mode?
           Symmetry
           Fixing Voltages
    4    LDPC Analogue Decoder
           Subthreshold MOS Gilbert-based Cells
           The Decoder
 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                    Design Essentials
               Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                 Design Rules Proposed - Circuit Level    Symmetry
                              LDPC Analogue Decoder       Fixing Voltages
                                          Conclusions


Dummy transistors for Dummy currents


Keep the same quantity of
transistors over the different
paths of a circuit’s stage to keep
similar VDS for all transistors.


Then . . .
VDS constrained by the
topology.



J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                    Design Essentials
               Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                 Design Rules Proposed - Circuit Level    Symmetry
                              LDPC Analogue Decoder       Fixing Voltages
                                          Conclusions


Dummy transistors for Dummy currents


Keep the same quantity of
transistors over the different
paths of a circuit’s stage to keep
similar VDS for all transistors.


Then . . .
VDS constrained by the
topology.



J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                    Design Essentials
               Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                 Design Rules Proposed - Circuit Level    Symmetry
                              LDPC Analogue Decoder       Fixing Voltages
                                          Conclusions


Dummy transistors for Dummy currents


Keep the same quantity of
transistors over the different
paths of a circuit’s stage to keep
similar VDS for all transistors.


Then . . .
VDS constrained by the
topology.



J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                    Design Essentials
               Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                 Design Rules Proposed - Circuit Level    Symmetry
                              LDPC Analogue Decoder       Fixing Voltages
                                          Conclusions


Dummy transistors for Dummy currents


Keep the same quantity of
transistors over the different
paths of a circuit’s stage to keep
similar VDS for all transistors.


Then . . .
VDS constrained by the
topology.



J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                  Design Rules Proposed - Circuit Level    Symmetry
                               LDPC Analogue Decoder       Fixing Voltages
                                           Conclusions


Outline
    1    Design Essentials
           Motivation
           Models for Circuit Simulation
           Substrate Bias (VSB ) and Other Parameters
    2    Design Rules Proposed - Transistor Level
           Setting VSB to 0
           Fabrication Process
    3    Design Rules Proposed - Circuit Level
           Topology’s Choice: Current or Voltage Mode?
           Symmetry
           Fixing Voltages
    4    LDPC Analogue Decoder
           Subthreshold MOS Gilbert-based Cells
           The Decoder
 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                  Design Rules Proposed - Circuit Level    Symmetry
                               LDPC Analogue Decoder       Fixing Voltages
                                           Conclusions


Fixing Voltages
How to do it?

 According to Vittoz [5], the supply
 voltage required by a subth. MOS
 should be greater than 4φT or
 10φT , for a digital or an analogue
 application respectively.
 Then . . .
             ∼
     VCCMIN =(10A + 4B )φT                                                                               (10)
             ∼ V − 4B φT + j4φT
      VBIASi =i CC                                                                                       (11)
                   A




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                  Design Rules Proposed - Circuit Level    Symmetry
                               LDPC Analogue Decoder       Fixing Voltages
                                           Conclusions


Fixing Voltages
How to do it?

 According to Vittoz [5], the supply
 voltage required by a subth. MOS
 should be greater than 4φT or
 10φT , for a digital or an analogue
 application respectively.
 Then . . .
             ∼
     VCCMIN =(10A + 4B )φT                                                                               (10)
             ∼ V − 4B φT + j4φT
      VBIASi =i CC                                                                                       (11)
                   A




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                  Design Rules Proposed - Circuit Level    Symmetry
                               LDPC Analogue Decoder       Fixing Voltages
                                           Conclusions


Fixing Voltages
How to do it?

 According to Vittoz [5], the supply
 voltage required by a subth. MOS
 should be greater than 4φT or
 10φT , for a digital or an analogue
 application respectively.
 Then . . .
             ∼
     VCCMIN =(10A + 4B )φT                                                                               (10)
             ∼ V − 4B φT + j4φT
      VBIASi =i CC                                                                                       (11)
                   A




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level   Topology’s Choice: Current or Voltage Mode?
                  Design Rules Proposed - Circuit Level    Symmetry
                               LDPC Analogue Decoder       Fixing Voltages
                                           Conclusions


Fixing Voltages
How to do it?

 According to Vittoz [5], the supply
 voltage required by a subth. MOS
 should be greater than 4φT or
 10φT , for a digital or an analogue
 application respectively.
 Then . . .
             ∼
     VCCMIN =(10A + 4B )φT                                                                               (10)
             ∼ V − 4B φT + j4φT
      VBIASi =i CC                                                                                       (11)
                   A




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                           Subthreshold MOS Gilbert-based Cells
                  Design Rules Proposed - Circuit Level
                                                           The Decoder
                               LDPC Analogue Decoder
                                           Conclusions


Outline
    1    Design Essentials
           Motivation
           Models for Circuit Simulation
           Substrate Bias (VSB ) and Other Parameters
    2    Design Rules Proposed - Transistor Level
           Setting VSB to 0
           Fabrication Process
    3    Design Rules Proposed - Circuit Level
           Topology’s Choice: Current or Voltage Mode?
           Symmetry
           Fixing Voltages
    4    LDPC Analogue Decoder
           Subthreshold MOS Gilbert-based Cells
           The Decoder
 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                           Subthreshold MOS Gilbert-based Cells
                  Design Rules Proposed - Circuit Level
                                                           The Decoder
                               LDPC Analogue Decoder
                                           Conclusions


Equality Node
Schematic




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                                                                      Subthreshold MOS Gilbert-based Cells
                  Design Rules Proposed - Circuit Level
                                                                                                      The Decoder
                               LDPC Analogue Decoder
                                           Conclusions


Equality Node
Performance

                                           4.5


                                           3.5


                                           2.5


                                           1.5
                                                                                                                                          PIN(1)=0.93
                    log(POUT(0)/POUT(1))




                                                         PIN(1)=0.01
                                           0.5                                               PIN(1)=0.50
                                                                   PIN(1)=0.07

                                           -0.5                                                                        PIN(1)=0.99


                                           -1.5


                                           -2.5

                                                                                                                            Expected
                                           -3.5                                                                             Post-layout Simulation


                                           -4.5
                                                  -2.2      -1.8       -1.4   -1.0    -0.6     -0.2     0.2     0.6         1.0     1.4       1.8       2.2
                                                                                 log(PVARYING_INPUT(0)/PVARYING_INPUT(1))



 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                           Subthreshold MOS Gilbert-based Cells
                  Design Rules Proposed - Circuit Level
                                                           The Decoder
                               LDPC Analogue Decoder
                                           Conclusions


Parity-Check Node
Schematic




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                                                                               Subthreshold MOS Gilbert-based Cells
                  Design Rules Proposed - Circuit Level
                                                                                                               The Decoder
                               LDPC Analogue Decoder
                                           Conclusions


Parity-Check Node
Performance

                                           2.0

                                                                    PIN(1)=0.01
                                           1.6


                                           1.2


                                           0.8           PIN(1)=0.93
                    log(POUT(0)/POUT(1))




                                           0.4

                                                                                          PIN(1)=0.50
                                           0.0


                                           -0.4

                                                         PIN(1)=0.07
                                           -0.8


                                           -1.2

                                                                                                     Expected
                                           -1.6                     PIN(1)=0.99                      Post-layout Simulation


                                           -2.0
                                                  -2.2       -1.8      -1.4       -1.0       -0.6       -0.2     0.2    0.6     1.0   1.4   1.8   2.2
                                                                                         log(PVARYING_INPUT(0)/PVARYING_INPUT(1))



 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                           Subthreshold MOS Gilbert-based Cells
                  Design Rules Proposed - Circuit Level
                                                           The Decoder
                               LDPC Analogue Decoder
                                           Conclusions


Outline
    1    Design Essentials
           Motivation
           Models for Circuit Simulation
           Substrate Bias (VSB ) and Other Parameters
    2    Design Rules Proposed - Transistor Level
           Setting VSB to 0
           Fabrication Process
    3    Design Rules Proposed - Circuit Level
           Topology’s Choice: Current or Voltage Mode?
           Symmetry
           Fixing Voltages
    4    LDPC Analogue Decoder
           Subthreshold MOS Gilbert-based Cells
           The Decoder
 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                           Subthreshold MOS Gilbert-based Cells
                  Design Rules Proposed - Circuit Level
                                                           The Decoder
                               LDPC Analogue Decoder
                                           Conclusions


(3,6) LDPC Decoder.
Tanner Graph




    A. Snoeren, “On the practicality of Low-Density Parity-Check codes,”
    MIT Lab for Computer Science, pp. 1–14, June 2001.


 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                               Subthreshold MOS Gilbert-based Cells
                  Design Rules Proposed - Circuit Level
                                                               The Decoder
                               LDPC Analogue Decoder
                                           Conclusions


(3,6) LDPC Decoder.
Convergence to a New Codeword, SNR=3dB, Input [1. . . 10]: 1011001001

                                1.0


                                0.9


                                0.8

                                                                                      Bit1
                                0.7                                                   Bit2
                                                                                      Bit3
                                                                                      Bit4
                   P(Bit i=1)




                                0.6
                                                                                      Bit5
                                                                                      Bit6
                                0.5                                                   Bit7
                                                                                      Bit8
                                                                                      Bit9
                                0.4                                                   Bit10


                                0.3


                                0.2


                                0.1


                                0.0
                                      50   51   52         53          54        55           56
                                                           Time (us)



 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                                                               Subthreshold MOS Gilbert-based Cells
                  Design Rules Proposed - Circuit Level
                                                               The Decoder
                               LDPC Analogue Decoder
                                           Conclusions


(3,6) LDPC Decoder.
Convergence to a New Codeword, SNR=3dB, Input [1. . . 10]: 1011001001

                                1.0


                                0.9


                                0.8

                                                                                      Bit1
                                0.7                                                   Bit2
                                                                                      Bit3
                                                                                      Bit4
                   P(Bit i=1)




                                0.6
                                                                                      Bit5
                                                                                      Bit6
                                0.5                                                   Bit7
                                                                                      Bit8
                                                                                      Bit9
                                0.4                                                   Bit10


                                0.3


                                0.2


                                0.1


                                0.0
                                      50   51   52         53          54        55           56
                                                           Time (us)



 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                    Design Essentials
               Design Rules Proposed - Transistor Level
                 Design Rules Proposed - Circuit Level
                              LDPC Analogue Decoder
                                          Conclusions


Conclusions and Outlook

           The essentials for properly controlling subthreshold MOS
           circuits were described.
           A simple and accurate CMOS-only voltage-mode circuit
           solution was provided for analogue decoders using the
           Sum-Product algorithm.
           The proposed rules were shown to work properly. As they
           are physics-based, they are expected to be easily adapted
           for any subthreshold MOS circuit.
           An LDPC decoder was successfully simulated, but . . . a
           chip is yet needed as proof of concept.


J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                    Design Essentials
               Design Rules Proposed - Transistor Level
                 Design Rules Proposed - Circuit Level
                              LDPC Analogue Decoder
                                          Conclusions


Conclusions and Outlook

           The essentials for properly controlling subthreshold MOS
           circuits were described.
           A simple and accurate CMOS-only voltage-mode circuit
           solution was provided for analogue decoders using the
           Sum-Product algorithm.
           The proposed rules were shown to work properly. As they
           are physics-based, they are expected to be easily adapted
           for any subthreshold MOS circuit.
           An LDPC decoder was successfully simulated, but . . . a
           chip is yet needed as proof of concept.


J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                    Design Essentials
               Design Rules Proposed - Transistor Level
                 Design Rules Proposed - Circuit Level
                              LDPC Analogue Decoder
                                          Conclusions


Conclusions and Outlook

           The essentials for properly controlling subthreshold MOS
           circuits were described.
           A simple and accurate CMOS-only voltage-mode circuit
           solution was provided for analogue decoders using the
           Sum-Product algorithm.
           The proposed rules were shown to work properly. As they
           are physics-based, they are expected to be easily adapted
           for any subthreshold MOS circuit.
           An LDPC decoder was successfully simulated, but . . . a
           chip is yet needed as proof of concept.


J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                    Design Essentials
               Design Rules Proposed - Transistor Level
                 Design Rules Proposed - Circuit Level
                              LDPC Analogue Decoder
                                          Conclusions


Conclusions and Outlook

           The essentials for properly controlling subthreshold MOS
           circuits were described.
           A simple and accurate CMOS-only voltage-mode circuit
           solution was provided for analogue decoders using the
           Sum-Product algorithm.
           The proposed rules were shown to work properly. As they
           are physics-based, they are expected to be easily adapted
           for any subthreshold MOS circuit.
           An LDPC decoder was successfully simulated, but . . . a
           chip is yet needed as proof of concept.


J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                    Design Essentials
               Design Rules Proposed - Transistor Level
                 Design Rules Proposed - Circuit Level
                              LDPC Analogue Decoder
                                          Conclusions


Conclusions and Outlook

           The essentials for properly controlling subthreshold MOS
           circuits were described.
           A simple and accurate CMOS-only voltage-mode circuit
           solution was provided for analogue decoders using the
           Sum-Product algorithm.
           The proposed rules were shown to work properly. As they
           are physics-based, they are expected to be easily adapted
           for any subthreshold MOS circuit.
           An LDPC decoder was successfully simulated, but . . . a
           chip is yet needed as proof of concept.


J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                     Design Essentials
                Design Rules Proposed - Transistor Level
                  Design Rules Proposed - Circuit Level
                               LDPC Analogue Decoder
                                           Conclusions


Thanks for your attention.




                              Do you have
                             any questions?



 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                   For Further Reading
                               MOS Differential Pair AUX
                                   Fixing Voltages AUX



For Further Reading I


           (2005, July) Bsim3 homepage. The Device Group
           Department of EECS UC Berkeley. [Online]. Available:
           http://www-device.eecs.berkeley.edu/$\sim$bsim3/
           D. K. R. Velghe and F. Klaassen, “Compact MOS modeling
           for analogue circuit simulation,”
           velghe_mm9_iedm1993.pdf, Philips Research, Tech. Rep.
           IEDM Techn. Digest, 1993. [Online]. Available:
           http://www.semiconductors.philips.com/Philips_Models/mos_
           models/model9/



 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                   For Further Reading
                               MOS Differential Pair AUX
                                   Fixing Voltages AUX



For Further Reading II

           K. M. S. Healey and D. Klaassen, “Comparison of BSIM3v3
           and MOS MODEL 9,” ur027_97.ps, Philips Research, Tech.
           Rep. Nat. Lab. Unclassified Report 002/97, 1997. [Online].
           Available: http://www.semiconductors.philips.com/Philips_
           Models/mos_models/model9/
           MOS Model, level 903, m903.pdf, Philips Semiconductors,
           Oct. 2004. [Online]. Available: http://www.semiconductors.
           philips.com/Philips_Models/mos_models/model9/
           E. Vittoz, “Weak inversion in analog and digital circuits,” in
           Competence Center for Circuit Design Workshop 2003,
           Oct. 2003.

 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                   For Further Reading
                               MOS Differential Pair AUX
                                   Fixing Voltages AUX



Inputs and Outputs
MOS Differential Pair - Subthreshold Region


                                                           Log-Likelihood Ratio

                                                                             P (uk = 1)
                                                               L(uk ) = ln                 (12)
                                                                             P (uk = 0)

                                                           Designing with the proposed rules
                                                           guarantees:

                                                                   ∼
                                                                                    IDS1
                                                               Vuk = (1 + mo )φT ln        (13)
                                                                                    IDS0




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                   For Further Reading
                               MOS Differential Pair AUX
                                   Fixing Voltages AUX



Fixing Voltages
How to do it?

 According to Vittoz [5], the supply
 voltage required by a subth. MOS
 should be greater than 4φT or
 10φT , for a digital or an analogue
 application respectively.
 Then . . .
             ∼
     VCCMIN =(10A + 4B )φT                                 (14)
             ∼ V − 4B φT + j4φT
      VBIASi =i CC                                         (15)
                   A




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel
                                   For Further Reading
                               MOS Differential Pair AUX
                                   Fixing Voltages AUX



Fixing Voltages
How to do it?

 According to Vittoz [5], the supply
 voltage required by a subth. MOS
 should be greater than 4φT or
 10φT , for a digital or an analogue
 application respectively.
 Then . . .
             ∼
     VCCMIN =(10A + 4B )φT                                 (14)
             ∼ V − 4B φT + j4φT
      VBIASi =i CC                                         (15)
                   A




 J. Pérez Chamorro, C. Lahuec, F. Seguin and M. Jézéquel

				
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