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Optimal State Assignment to Spare Cell inputs for Leakage Recovery

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					 Oct. 31                                   IJASCSE Vol 1 Issue 3, 2012




    Optimal State Assignment to Spare Cell inputs for
                   Leakage Recovery
 Vasantha Kumar B.V.P         N. S. Murthy Sharma             K. Lal Kishore               A. Rajakumari
 Synopsys (India) Pvt. Ltd   BVCE College, Odalarevu,   JNT University, Ananthapur,     B.V.R.I.T, Narsapure,
    Hyderabad, India             India, 533210.              Hyderabad, India             Hyderabad, India



Abstract— This work presents a novel                      models to minimize leakage power of spare
leakage recovery method based on optimal                  cells. The proposed method was tested on
state assignment to spare cells in the                    standard cell based LVDS layout created
layout during post placement stage of the                 using Synopsys SAED 32/28nm and other
physical design flow. As the technology                   available Synopsys Design Ware 65nm,
continues to shrinks, leakage power is                    45nm, 40nm & 28nm standard cell libraries.
growing at exponential rate due to the                    With the proposed method we could
aggressive scaling trends of channel                      observe 48% to 30% reduction in spare cell
lengths, gate oxide thickness, and doping                 leakage power and 3.8% to 0.7% reduction
profiles combined with an increasing                      in overall design leakage power.
number of transistors packaged in a single
chip. For the high speed designs with multi                  Keywords-Spare Cells; State dependent
threshold libraries leakage recovery is the               leakage power; Engineering Change Order
biggest challenge apart from meeting                      (ECO);Constant       Insertion;   Liberty
timing goals. There is a need for reducing                Standard; Subthreshold Leackage Power;
leakage power where ever possible in                      Power Recovery.
various stages of the design flow. During
                                                                             I.   INTRODUCTION
the physical implementation stages VLSI
designs often needs be corrected due to                       Minimization of power is one of the most
the changes in specification or design rule               important performance metrics in the design of
constraints violations. This correction                   portable systems and wireless communication
process is called Engineering Change                      devices. On the other hand the demand for
Order (ECO). Spare cells are redundant                    greater integration, higher performance, and
cells introduced in the layout during early               lower dynamic power dissipation drives scaling
physical design stage whose inputs are                    of CMOS devices. In nanoscaled CMOS
traditionally tied to Power (VDD) or Ground               devices leakage currents have increased
(VSS) and will be used during ECO                         dramatically leading to higher static power
changes. However these spare or ECO                       dissipation. There are many leakage sources.
cells in stand-by mode also contributes to a              Among them the three major contributors are
significant sub-threshold leakage power in                gate oxide tunneling based leakage (~54.79
lower technology nodes. In this paper we                  percent),    subthreshold   leakage     (~44.5
are proposing a method which involves                     percent), and Band-To-Band-Tunneling (BTBT)
assigning optimal standby at every input of               based leakage (~0.68 percent) for 45 nm Bulk-
spare cell gate based on state dependent                  CMOS [1]. Other components of leakage
leakage power tables available in library                 include Gate Induced Drain Leakage (GIDL),
                                                          Drain Induced Barrier Lowering (DIBL), etc.,




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                                                     implementations is to meet timing with the
                                                     lowest possible leakage. Various system and
                                                     architectural strategies are available to reduce
[2]. The magnitude of each leakage component         overall power but there still remains the
depends on the process technology used.              challenge of arriving at the optimal library cell
However use of high-K dielectric gate helps          mix for at-speed lowest power.
reduce gate oxide leakage current. But, when
high-K dielectric is used, the channel mobility      A.   Multi-threshold libraries cells
degrades leading to reduced performance.
SiGe layer has been used to strain Si to             Multi-threshold libraries are used to achieve
overcome reduced carrier mobility to improve         the optimal library cell mix for at-speed lowest
performance. This, however, causes an                power design. These libraries are released with
increase in subthreshold and BTBT leakage            multiple versions typically called as high Vt
current [3]. For 65nm and below scaled CMOS          (HVT), standard Vt (SVT) and low Vt(LVT) cells
devices the most important sources of leakage        which are differentiated by gate length and/or
are: subthreshold leakage, gate leakage, and         gate implant thus providing a variety of trade-
the reversed bias junction BTBT leakage.             offs in performance versus leakage. SVT cells
Subthreshold current rises due to lowering of        refers to the cell with standard threshold for the
threshold voltage which is scaled to maintain        given process technology. The HVT cells refer
transistor ON current on the face of falling         to cells with higher threshold voltage than the
power supply voltage. Gate leakage current           standard for that process technology. Similarly,
density is increasing due to scaling of oxide        the LVT cells are faster than SVT cells but the
thickness resulting in rising tunneling current.     leakage is also correspondingly high. Typically
In fact, gate leakage is expected to increase at     in high speed CPU design, the percentage of
least by 10 times for each of the future             LVT cells from Synthesis netlist can be up to
generations [4].                                     99% as the designs are first synthesized using
                                                     LVT cells to meet speed target. Even in
Reverse-biased       tunneling      band-to-band     physical design stage since performance target
leakage is increasing due to reduction in            is most critical requirement designers put more
junction depletion width that is necessary to        effort on timing optimization from placement
contain transistor short channel effects (SCE).      through post routing optimization. However
In previous CMOS technologies, dynamic               power optimization during placement stages is
power easily wins over leakage power but as          done optionally or incrementally if critical timing
shown in Figure. 1, ITRS road map predicted          can be met with small total negative slack
that this trend is coming to an end [5]. As          (TNS). Final stage leakage power recovery is
technologies scales down, percentage of              only done at ECO stages by swapping LVT
leakage power to total power is gradually going      cells with HVT cells on positive slack paths.
up with every node as shown in Figure.2.
Leakage is an unwanted byproduct and                 B.   Spare (or) ECO Cells leakage
substantially reduces the operational time of
the devices thereby rendering such devices              Design leakage is of particular importance
uncompetitive. It is, therefore, absolutely          not only to data path combinational logics,
necessary to eliminate leakage, wherever it is       memory blocks and sequential elements but
possible. As leakage becomes increasingly            also to standby circuit connections of ECO or
significant in overall power consumption with        spare cells. In this paper we are focusing on
feature size reduction, the goal of many             standby leakage elimination in spare cells.




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Spare cells are redundant cells or extra cells
distributed in the design as backup cells to
implement any ECOs that may be required in
the design, at a later stage. Spare cells do not
play any active role in the IC operation. But
some of these cells can be selectively
connected to the normally functioning
electronic components, during revising or
rerouting process of IC. This process is often
referred to as an ECO, and the spare cells can
be alternatively referred to as ECO cells.
                                                      Figure 1. ITRS road map showing static power surpassing dynamic power
Based on the performance of the design and
switching       activity    involved    different
combinations of HVT, SVT and LVT cells will                                     900

be sprinkled in the design core as spare cells.                                 800

Spare cell not only occupy more chip areas                                      700

causing substantial impact on the profit but are
                                                         Power Consumption[W]
                                                                                600

also responsible for the more leakage power                                     500

[6]. The goal of the spare cell is to provide                                   400

sufficient resources for ECO at every possible                                  300
location so they are evenly distributed over the                                200
whole layout. Spare cells contribute to 5-20%                                   100
of the total cell count in an IC [7]. As all the
                                                                                 0
spare cells are not used by the additional
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design revisions, significant amount of power                                                              Switching Power, Logic               Switching Power, Memory

leakage exists throughout the life time of the                                                             Leakage Power, Logic                 Leakage Power, Memory

                                                          Figure 2. SYSD11 SOC Consumer Stationary Power Consumption
chip due to cells which are not the part of the                               Trends(from ITRS)
logic. In traditional design flows unused spare
cells inputs are connected to VDD and VSS             by foundry. To demonstrate the leakage
supply rails, which is called constant insertion      recovery form ECO cells we have shown
technique and they will draw static or leakage        experimental results on LVDS design using
current [8]. But this method of always tying          Synopsys SAED 32/28nm library and other
inputs of spare cells to GND or VCC will not          available Synopsys Design Ware 65nm, 45nm,
ensure less leakage.                                  40nm & 28nm standard cell libraries [9, 10].
                                                      This paper is organized in to six sections.
  So, to address this issue we proposed an            Section II talks about various ECO techniques
optimal state assignment technique to spare           along with prior work to reduce leakage power
cell inputs to reduce their leakage power based       in spare cells. Section III talks about state
on state dependent leakage table given                dependent leakage power, Section IV talks
                                                      about proposed method for reducing spare
                                                      cells leakage, Section V talks about
                                                      experimental     results   and    Section  VI
                                                      conclusions.




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                                                       after the SoC is fabricated and issues are
                                                       caught during its post silicon validation (i.e very
                                                       late design change request). As, the mask
     II.   SPARE CELL BASED ECO’S AND MOTIVATION
                                                       generation cost for the base layers is multiple
     Design changes are inevitable and are             times the mask generation cost for the metal
increasing in complexity due to rapid growth in        layers so addition/deletion or movement of any
Very Large Scale Integrated (VLSI) design              standard cell requires the base layer change
size. When these changes occur towards the             hence any of such activity is avoided and some
end of the design cycle, where the design has          extra unused or redundant standard cells are
converged after significant efforts, it is             added in the design for this purpose known as
infeasible to go through the top down design           Spare Cells [12, 13, 14, 15, 16, 17, 18]. Spare
flow again. This demands a method called               cells are the extra functional cells kept in the
Engineering Change Order (ECO) to keep                 design for ECO. The number of spare cells and
these changes local to avoid any need to do            their type depends on the design complexity
re-synthesis of the whole design. Since the            and functionality, but it is advisable to use
ECOs are done very close to tape out, these            universal gates so that we can get most of the
are time critical missions and any inefficiency        functionality or from the design functionality.
in implementation will directly impact the cost        The most commonly useful type of spare cells
of the product. ECOs can be functional and             are INV, BUF, NAND and NOR, while the
nonfunctional. Functional ECOs deal with               complex gates like XOR are rarely used [19].
making logical changes to the design. The core
objective of a functional ECO is to                    B.  Prior Work and motivation
accommodate RTL changes without major                       There are some techniques developed to
perturbation to the converged design.                  reduce leakage in the circuit level, like
Nonfunctional ECOs deal with changes that              programmable spare cells which will separate
affect signal integrity, Design Rule Verification      power rail from cell structure proposed by
(DRV) or routing.                                      Anubhav Srivastava [6] and spare cell with two
                                                       power supply rails proposed by Yung-Chin Hou
A.     Implementing ECOs                               [20]. This approach involves altering design
                                                       cells layout (or) creating new libraries which
     There are two types of functional ECO             requires significant changes to traditional flows.
flows       during    physical     design    flow.     Also metal-configurable-gate-array spare cell
Unconstrained ECO (Non-Freeze Silicon ECO)             ECO flows are becoming popular in recent
flow and Freeze silicon ECO flow [11].                 technologies which needs gate array cells
Unconstrained ECO flow is used if the design           library provided by library vendor separately
has not been taped out yet or before the mask          [21]. During the re-spin these cells can be
preparations of the chip. In this flow there is        programmed by metal mask changes for ECO
flexibility of addition/deletion of standard cells     implementation, thus reducing mask cost.
while doing the change. These changes are              These above mentioned methods are not
first implemented logically with any type or           flexible for re-spin designs and methodologies
number of standard cells and then these cells          like gate array eco requires new libraries with
are placed and routed incrementally as part of         entirely different flows. Engineering change
physical implementation. This do not impact            order (ECO) is a highly constrained design
the mask cost for the SoC as all the masks are         optimization based on an existing design with
prepared after database is sent to Fab and no          tight design schedules due to time to market
spare cells are required in the design. Freeze         consideration [22]. Because of these reasons
silicon ECO flow is used if cell placement is          designers do not tend to change their design
fixed or the changes are required to be done




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                                                    multiplied with its probability. (Here the
                                                    probability refers to the chances that the net
                                                    "A" and "B" would be in such a state that the
flows quickly to adopt these new flows which        Boolean condition is satisfied). So the total
involves process changes. Also most of the re-      leakage power would be the summation of all
spin designs with uses spare cell methodology       these "when" conditions multiplied with their
for ECOs also require a smart of way of             probability. This can be formulated as shown
reducing spare cell leakages with minimum           below:
changes to lower metals. So there is a need for
a smart approach with very minimum changes                   Pr(when1)*Val1 + Pr(when2)*Val2 + [1 - Pr(when1) -
                                                             Pr(when2)]*Total_Val                          (1)
to existing design flows to address spare cell
leakage.                                            Pr (when1), Indicates the probability that the
      III.   STATE DEPENDENT LEAKAGE POWER          first condition will occur (i.e. "! A*B" will be
                                                    true). Pr(when2), Indicates the probability that
      The CMOS gates leakage power                  the second condition will occur (i.e"A*!B" will be
consumption would depend on the different           true). The signal probability values Pr(A),
states taken by the inputs of the gates [23].       Pr(B), and so on will be obtained from the net
This is referred as state dependent leakage         switching activity file provided as the input to
power consumption of the CMOS gates. For a          the EDA tools. General formula for calculation
gate which has “n” inputs, there can be 2n          of state dependent leakage power can be
states for which the leakage power                  given as follows:
consumption is found using the simulation
models of the circuit and is stored in a format              Pr(when1)*Val1+Pr(when2)*Val2+…
which can used by the EDA tools to estimate                  Pr(when2n)*Val2n+[1-Pr(when1)-Pr(when2)-
the state dependent leakage power of those                   …Pr(when2n)]*Total_Val                            (2)
gates. Every cell would contribute to the state     Where “n” stands for the no of inputs of the gate and
dependent leakage power including the spare
cells in the design. The silicon vendor models               Total_Val= cell_leakage_power                     (3)
these state dependent leakage tables in the
form of .lib (liberty) format [24]. Below is an
example of state dependent leakage values
                                                                    IV.    PROPOSED METHOD
specified in .lib for AND gate:
                                                        For illustration let’s assume that the AND
        cell_leakage_power : 1.0 ;                  gate in above example .lib is a spare cell. This
             leakage_power() {
                when : "!A B" ;
                                                    gate can have 4 different combinations (C1,
                value : 1.5 ;                       C2, C3 and C4) of the A and B and hence four
               }                                    different state dependent leakage power
             leakage_power() {                      values. If the state dependent leakage power
                when : "A !B" ;                     table of this AND gate would be summarized
                value : 2.0 ;
               }
                                                    as shown in Table 1. As per the traditional
                                                    approach, if A and B inputs of the AND gate
   The EDA tools will calculate the total           are tied to ground, C4 would be evaluated to
leakage power consumption using above               be true and the leakage value would be V4 as
power models for leakage power optimization         per the table and the probability of occurrence
of functional paths. In the above power model       of other conditions C1, C2 and C3 will be zero.
example there are two "when" conditions; each       Now from equation (2) Pr(C1), Pr(C2), Pr(C3) is
"when" condition will be evaluated and              zero as A and B of the AND gate is tied to




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  Oct. 31                                                IJASCSE Vol 1 Issue 3, 2012


                                                                        Vds2=(nkT/q(1+2+))*ln((A1/A2)eqVdd/nkT+1)                   (8)

                                                                        Vds(i)=(nkT/q(1+2+))*ln(1+(Ai-1/Ai)(1-eqVds(i-1)/nkT))      (9)
ground and it’s leakage power can be given
as:                                                                     Vdd is the power supply voltage. Vg, Vd, and
        Psdlp of AND gate =Pr(whenC4)*V4 =1*V4= V4              (4)
                                                                        Vs are the gate voltage, drain voltage, and
                                                                        source voltage of the CMOS transistor
Pr(whenC4) = 1 as the inputs are tied to                                respectively. The bulk is connected to ground.
ground and hence when this condition will be                            Vth is the zero bias threshold voltage.  is the
evaluated to be true. But the leakage value V4                          body effect coefficient.  is the DIBL
may not be the lowest value of power in the                             coefficient, representing the effect of Vds
table. This is the problem with the traditional                         (Vds=Vd-Vs) on threshold voltage. C’ox is the
approach of connecting all spare cell inputs to                         gate oxide capacitance. 0 is the zero bias
ground. So we propose a state dependent                                 mobility. n is the subthreshold swing coefficient
leakage optimization method to idle spare cells                         of the transistor. Considering the stacking
where we assign a optimal state to inputs                               effect equation (8) shows Vds2 in terms of Vdd
which will guarantee lowest possible leakage.                           and equation (9) shows Vds(i) in terms of Vds(i-
In the proposed algorithm or flow we would be                           1) by equating the currents.
finding out the minimum leakage value Vmin for
the spare gate and find the corresponding input                         TABLE I.       STATE DEPENDENT LEAKAGE POWER OF 2-INPUT AND GATE
condition Cmin from .lib models and tie the
                                                                                When Condition              Leakage Power Value
spare cell inputs based on this condition. If a
spare master gate say “spareN” has n input
                                                                                    C1(A, B)                          V1
pins, then there can be 2n when conditions or
states in the power model table and 2n values
                                                                                   C2(A!, B)                          V2
of the leakage power values. So the minimum
state dependent leakage power of the spare
                                                                                   C3(A, B!)                          V3
master as per the proposed flow would be:
   P[minsdlp,spareN] = Pr(whenCmin) * Vmin                      (5)                C4(A! B!)                          V4

As the inputs of the spare master “spareN” are
tied to always evaluate condition Cmin,
P[minsdlp,spareN] = Vmin for the spare master                           A.  Problem formation and algorithm
“spareN”. If there are “m” instances of this
                                                                             Now our problem is defined as follows:
spare master “spareN” in the design then as
                                                                        Given a set of placed spare cell instances in a
per the proposed flow the total minimum
                                                                        layout, our objective is to find the optimal state
leakage power consumption would be:
                                                                        which gives minimum leakage value form state
          Total P[sdlp,spareN] = m * P[minsdlp,spareN]          (6)     dependent leakage power table of the
                                                                        corresponding .lib (liberty) files and tie them
The total standby power in equation (6) can be                          accordingly to their inputs. Our algorithm
represented by model proposed in [25] as                                SDLPT_Based_Sparecell_Connection_Algorith
follows.                                                                m is shown in Figure 3.            This proposed
                                                                        algorithm is written using tcl in order to be used
Isub=Aeq(Vg-Vs-Vth-Vs+Vds)/nkT (1-e-qVds/kT)                   (7)    in placement or post routing stages of physical
                                                                        design flow. The physical implementation flow
          where A=0C’ox(W/Leff)(kT/q)2e1.8                             for the proposed method is shown in Figure 4.




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                                                                                          V.    EXPERIMENTAL RESULTS


                                                                              Our algorithm was used to tie the spare
                                                                          cells inputs with optimal state which promises
                                                                          low standby leakage on Low Voltage
                                                                          Differential Signalling (LVDS) design. We have
                                                                          used




Figure 3. SDLPT_Based_Sparecell_Connection_Algorithm


     TABLE II.          LEAKAGE RECOVERY IN LVDS DESING IMPLEMENTED USING HVT CELLS ACROSS VARIOUS TECHNOLOGIES WITH PROPOSED METHOD


                                                                             % of                                    % of
                                                                                                                                  %
                                                            Spare Cell    Spare Cell    Spare Cell       %       Spare Cell
                                      Spare                                                                                   Reduction
                             Total               Overall     Leakage      Leakage in     Leakage     Reduction   Leakage in
           Technology                 Cells                                                                                     in the
    S.No                      Cell                Design       with         Design        with        in Spare     Design
           (HVT cells)                Count                                                                                    overall
                             Count               Leakage    Traditional      with       Proposed        Cells        with
                                       (%)                                                                                      Design
                                                               Flow       Traditional     Flow        Leakage     proposed
                                                                                                                               leakage
                                                                             Flow                                    Flow
     1           65nm         291    30(10.3)   23.454nW      1.051nW      4.48111      691.515pW    34.20409      2.99428    -1.48111
     2           45nm         382     30(7.8)    6.508uW    325.125nW      4.99577      250.049nW    23.09143      3.88702    -1.09577
     3           40nm         547     50(9.1)   192.856nW     8.518nW      4.41677        6.987nW     17.9737       3.6519    -0.71677
     4           32nm         372     30(8.0)   26.196uW    878.018nW      3.35173      793.798nW     9.59206        3.04     -0.35173
     5           28nm         608     50(7.3)    4.376uW     85.092nW      1.94452       54.222nW    36.27838      1.24788    -0.74452

     TABLE III.         LEAKAGE RECOVERY IN LVDS DESING IMPLEMENTED USING SVT CELLS ACROSS VARIOUS TECHNOLOGIES WITH PROPOSED METHOD


                                                                             % of                                   % of
                                                                                                                                  %
                                                            Spare Cell    Spare Cell    Spare Cell       %       Spare Cell
                                      Spare                                                                                   Reduction
                             Total               Overall     Leakage      Leakage in     Leakage     Reduction   Leakage in
           Technology                 Cells                                                                                     in the
    S.No                      Cell                Design       with         Design        with        in Spare     Design
           (SVT cells)                Count                                                                                    overall
                             Count               Leakage    Traditional      with       Proposed        Cells        with
                                       (%)                                                                                      Design
                                                               Flow       Traditional     Flow        Leakage     proposed
                                                                                                                               leakage
                                                                             Flow                                   Flow
     1       65nm             289    30(10.3)   305.601nW    15.953nW      5.22021       10.597nW    33.57362      3.52945    -1.72021
     2       45nm             383     30(7.8)   21.488uW      1.096uW      5.10052      774.427nW     29.3406      3.65875    -1.40052
     3       40nm             546     50(9.1)    1.191uW     49.799nW      4.18128       36.356nW    26.99452      3.08741    -1.08128
     4       32nm             378     30(7.9)   87.164uW      3.694uW      4.23799        3.332uW     9.79968      3.83862    -0.43799
     5       28nm             553     50(9.0)   35.303uW    789.896nW      2.23748      406.740nW    48.50715      1.16478    -1.03748

     TABLE IV.          LEAKAGE RECOVERY IN LVDS DESING IMPLEMENTED USING LVT CELLS ACROSS VARIOUS TECHNOLOGIES WITH PROPOSED METHOD




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                                                                            % of                                       % of
                                                                                                                                     %
                                                           Spare Cell    Spare Cell     Spare Cell        %        Spare Cell
                                    Spare                                                                                        Reduction
                          Total                Overall      Leakage      Leakage in      Leakage      Reduction    Leakage in
            Technology              Cells                                                                                          in the
    S.No                   Cell                 Design        with         Design         with         in Spare      Design
            (LVT cells)             Count                                                                                         overall
                          Count                Leakage     Traditional      with        Proposed         Cells         with
                                     (%)                                                                                           Design
                                                              Flow       Traditional      Flow         Leakage      proposed
                                                                                                                                  leakage
                                                                            Flow                                       Flow
      1        65nm        290     30(10.3)    1.204uW      61.769nW      5.13032        40.283nW     34.78444       3.40656     -1.73032
      2        45nm        383      30(7.8)   47.422uW       2.145uW      4.52322         1.510uW     29.60373       3.22739     -1.32322
      3        40nm        407      50(12)     2.970uW     224.308nW      7.55246       151.559nW     32.43264       5.23113     -2.35246
      4        32nm        340      30(8.8)   578.984uW     31.447uW      5.43141        22.198uW     29.41139        3.8962     -1.53141
      5        28nm        560      50(8.9)   123.511uW      2.729uW      2.20952         1.483uW     45.65775       1.21294     -1.00952

TABLE V.      LEAKAGE RECOVERY IN LVDS DESING IMPLEMENTED USING OPTIMIAL LIBRARY CELL MIX FOR AT-SPEED LOWEST POWER WITH PROPOSED METHOD

                                                                             % of                                      % of
                                                                                                                                      %
             Technology                                    Spare Cell     Spare Cell     Spare Cell        %        Spare Cell
                                                                                                                                  Reduction
                Node       Total    Spare      Overall      Leakage       Leakage in      Leakage      Reduction    Leakage in
                                                                                                                                    in the
     S.No      (Mix of      Cell    Cells       Design        with          Design         with         in Spare      Design
                                                                                                                                   overall
             HVT, SVT      Count    Count      Leakage     Traditional       with        Proposed         Cells         with
                                                                                                                                    Design
             & LVT %)                                         Flow        Traditional      Flow         Leakage      proposed
                                                                                                                                   leakage
                                                                             Flow                                      Flow
      1         65nm        298    30(10.0)   50.242nW        6.018nW      11.97803        3.993nW      33.64905      8.28131      -3.69672
      2         45nm        385     30(7.7)    6.161uW      931.709nW      15.12269      669.898nW      28.10008     11.35576      -3.76693
      3         40nm        493    50(10.1)   586.520nW      68.188nW      11.62586       47.649nW      30.12114      8.41883      -3.20703
      4         32nm        417     30(7.1)   30.655uW        1.817uW      5.92725         1.640uW      9.74133       5.38093      -0.54632
      5         28nm        540     50(7.3)   59.705uW      895.802nW      1.50038       481.001nW      46.30499      0.81127      -0.68911

                                                                         design suits. First 15 sets of layouts as shown
                                                                         in Table-II, Table-III & Table-IV are
                                                                         implemented for each threshold (VT) cells
                                                                         across all mentioned technology libraries
                                                                         separately to observe the leakage variation.
                                                                         The second set of 5 layouts as shown in Table-
                                                                         V are created using all combinations of HVT,
                                                                         SVT & LVT cells to demonstrate real design
                                                                         scenario with optimal library cell mix for at-
                                                                         speed lowest power design. After synthesis we
                                                                         have done the floorplan, placement and
                                                                         placement optimizations using Synopsys IC
                                                                         Compiler®. At this point we inserted various
                                                                         spare cells into the layout and sprinkled them
            Figure 4. Proposed Leakage Minimization Flow                 evenly across the layout. We have inserted 7
Synopsys SAED 32nm Multi-threshold library                               to 12% of total design cells as spare cells in
and 65nm, 45nm, 40nm & 28nm Synopsys                                     these layouts. Figure 5 shows the spare cells
Design     Ware    Multi-threshold   libraries                           distribution in LVDS design which are
consisting of HVT, SVT & LVT cells. For this                             highlighted in white throughout the layout. We
we carried out synthesis on LVDS RTL using                               have selected spare cells based on
these technology logical libraries using                                 conclusions made in [9] with majority of INV,
Synopsys’s Design Compiler® to get gate level                            BUF, NAND, OR and few NOR gates. We have
netlist. We have implemented for sets of                                 also included few scanable flops per each




www.ijascse.in                                                                                                                          Page 8
 Oct. 31                              IJASCSE Vol 1 Issue 3, 2012

                                                     with proposed flow and it is consistent across
                                                     different VT cells. This results in 1.7 to 0.7% of
                                                     overall designs leakage recovery which is very
clock group. In the second set of layouts in         significant for any handheld device chip. The
Table-II the combination of HVT, SVT & LVT           results from Table-III shows real design
cells are maintained as per the timing               scenario with mix of different VT cells shows
requirements and number of LVT spare cells           an overall designs leakage recovery of 3.7% to
are restricted up to 20% of total spare cells.       0.7% with proposed spare cell connections.
Only for 28nm technology 14% LVT cells and           Also with the recent enhancements in routing
67% of SVT cells are used during synthesis for       technology to handle special power cells comb
meeting timing. For the remaining technologies       routing of spare cells as per proposed method
LVT cells percentage is restricted to below 2%       is not an issue. The input connections made by
and SVT cell to below 30% of total design cells      the tool during the routing as per the proposed
count. HVT cells are used to primarily to            optimal inputs states for the spare cells OR
reduce the leakage power by maintain design          and XNOR in SAED 32nm layout is shown in
time and total negative slack (TNS). At this         Figure 6.
point we have made two copies of these
layouts in each design directory for
demonstrating variation in overall design
leakage due to spare cells when they are
connected in traditional (constant insertion
method) versus proposed methods. After
spreading spare or ECO cells in to the layout at
placement stage we have used our tcl based
algorithm to assign optimal states derived from
state dependent leakage tables to the input of
spare cells. Similarly other set of layout spare
cell inputs are connect to ground (VSS). After
                                                       Figure 5. Spare Cells Distribution across the layout in LVDS design
this we proceeded to clock tree synthesis and
finished routing and routing optimizations using
IC Compiler® on all layouts.            For this
implementation starting form Synthesis we
have used fast process, high temperature and
high voltage corner which is the worst case
PVT corner for leakage where the leakage
values trend will as expected and without
leakage inversion. Now finally at this point to
analyze the leakage power of the design and
spare cells contribution toward designs
leakage in all layouts we have used
Synopsys’s PrimeTime-PX® signoff power
analysis tool. The result in Table-II shows the          Figure 6. Spare Cells OR and XNOR connections after routing
comparison between the spare cell leakage
power numbers between traditional and
proposed flows and their contributions to                                  VI.    CONCLUSIONS
overall design leakage. Nearly 48% to 30% of             In this paper we proposed a new state
leakage recovery in spare cells is observed          dependent leakage tables based connections




www.ijascse.in                                                                                                      Page 9
  Oct. 31                                      IJASCSE Vol 1 Issue 3, 2012

                                                                     future", IEEE International Conference on
                                                                     Microelectronic Systems Education, 2009, pp. 20-
                                                                     24
                                                              [10]   Goldman R., Bartleson K., Wood T., Kranen K., Cao
                                                                     C., Melikyan V., "Synopsys' Interoperable Process
to ideal spare cell inputs which ensures                             Design       Kit",    European      Workshop       on
minimum leakage power when compared to                               Microelectronics Education, 2010
traditional constant insertion method where all               [11]   State Dependent Leakage Power Calculation
                                                                     [Online]. Available: https://solvnet.synopsys.com
inputs will be tied to power or ground. The                   [12]   Kuan-Hsien Ho, Yen-Pin Chen, Jia-Wei Fang, Yao-
method of using state dependent leakage                              Wen Chang, “ECO timing optimization using spare
                                                                     cells and technology remapping”. IEEE TCAD, vol.
tables to compute standard cells leakage has                         29, no. 5, pp. 697-710, May 2010.
been explored much earlier. However its                       [13]   Shao-Yun Fang, Tzuo-Fan Chien, Yao-Wen Chang, “
                                                                     Redundant-wires-aware ECO timing and mask-cost
application to spare cells is new. The proposed                      optimization” In Proc. ICCAD, pp. 381-386,Nov.
method was tested on post placed layouts                             2010.
using 65nm and below technologies and                         [14]   Kuan-Hsien Ho, Jiang, J.-H.R., Yao-Wen Chang,
                                                                     “TRECO: dynamic technology remapping for timing
results after routing shows that there is a huge                     engineering change orders”, In Proc. ASP-DAC pp.
reduction of 48 to 30 percent standby leakage                        331-336, Jan. 2010.
                                                              [15]   Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang,
power of spare cells and 1.7 to 0.7% reduction                       Marek-Sadovvska, M, “Engineering change using
in total standby leakage of IC. The proposed                         spare cells with constant insertion”. In Proc. ICCAD,
                                                                     pp. 544-547, Nov.2007.
method can be easily adapted to new or re-                    [16]   N. Modi and M. Marek-Sadowska, “ECO-map:
spin designs with very minimum changes to                            technology remapping for post-mask ECO using
                                                                     simulated annealing”, In Proc. ICCD, pp. 652-657,
design flows.                                                        Oct. 2008.
                                                              [17]   Jiang, I.H.-R., Hua-Yu Chang, Liang-Gi Chang, Huang-
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