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Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com Volume 1, Issue 3, September – October 2012 ISSN 2278-6856 Reversible and Fault Tolerant Reversible Gates Jaspreet Kaur1, Harpreet Kaur2 and Sheenu Thapar3 1,3 Assistant Professor Department of ECE CIET, Jalvehra, Fatehgarh Sahib,Punjab, India 2 Assistant professor Department of ECE BBSBEC, Fatehgarh Sahib, Punjab, India Abstract: Reversible Logic is becoming more and more reversible. This approach is a radical departure from both prominent technology having its applications in Low Power traditional logic design and traditional low energy design CMOS, Nanotechnology, and Optical Computing. techniques. Reversible logic has emerged as one of the most important For the computation to be physically reversible, and approaches for the power optimization with its application in low power VLSI design. In contrast to conventional gates, therefore not dissipate any energy, the computing engine reversible logic gates have the same number of inputs and must be logically reversible and implemented in a outputs, each of their output function is equal to 1 and their physically reversible technology [7]. Any system that fan-out is always equal to 1. It is interesting to compare both transitions from a state A to state B is physically reversible and conventional gates. It allows any fault that reversible if the state B uniquely determines state A, affects no more than a single signal readily detectable at the implying that the transition was logically reversible, and circuit’s primary outputs. In addition to this there are few the energy is available to make the reverse transition, families of reversible gates which offer fault tolerant technique. The paper is focused on the major VLSI implying that the transition was made in a physically limitations like delay and area of different reversible logic reversible technology. Logical reversibility imposes gates which are simulated in Xilinx8.1li and by writing the architectural constraints not met by conventional code in VHDL HDL and also compared reversible gates to processors. A conventional computing engine performs conventional gates. irreversible computations. These computations destroy Keywords: Reversible gate, Fault tolerant, delay, power information, and the second law of thermodynamics requires minimum energy dissipation when a bit of 1. INTRODUCTION information is discarded. In the decimal arithmetic Quantum computation has come to the forefront of domain it is receiving significant attention as the theoretical and applied research. Investigation into financial, commercial, and internet-based applications reversibility and reversible circuits is assumed to have a cannot tolerate errors generated by conversion between more prevalent role; because reversibility is a decimal and binary formats [8]. precondition of quantum computation. Fortuitously, the restrictive nature of reversibility induces a structure on 2. MOTIVATION the circuits such as a microprocessor design much more Logic computation in computers erases bit information; amenable to analysis; both within the framework of this is done inefficiently and heat dissipates while erasing reversible circuit design as well as for circuit complexity bit. According to Landauer, KTln 2 energy is dissipated in general. Reversible circuits [1-3] and reversible per bit operation, where k is Boltzmann’s constant, and T computation [4, 5] constrain every gate and every step of is the absolute temperature of the environment. At room the computation to be completely reversible, so that no temperature the dissipating heat is very small but not information may be lost at any step of the computation negligible. This computation procedure is irreversible. It and this does not contribute to heat dissipation in circuits. is true that high degree of integration and advancement in Therefore, they potentially help to solve at least two fabrication process have helped in better hardware; but problems: overheating and power saving, which implies this energy loss due to irreversible computation will be a longer life for batteries. The reversible logic solution may great impediment in the next decade. Bennett [4] showed be especially important in low-voltage designs of mobile that zero energy dissipation would be possible if the systems, where both power saving and overheating are network consists of reversible gates only. Thus very important due to the need for light weight and reversibility will be an essential property for the future independent power supply. Computing devices such as circuit design. The power loss due to irreversible gates is processors can be designed that do not require energy negligible for current logic technologies using adiabatic dissipation [4, 6], but only if the computation is logically design. But the information that is lost because of Volume 1, Issue 3, September – October 2012 Page 236 Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com Volume 1, Issue 3, September – October 2012 ISSN 2278-6856 irreversible circuits is not recoverable. Thus, it is good low cost there are design approaches and tools that motivation for any researcher to design using reversible incorporate them separately or in combination with each logic. other. The main differences of synthesizing a circuit with reversible gates, as compared to synthesizing a standard circuit are as follows: > The number of outputs of a logic gate is equal to the number of inputs. It is possible to find solutions (a) Feyman Gate (b) Peres Gate sacrificing one or more gate outputs for garbage, but such solution is of less value. > A heavy price is paid for every garbage output if the garbage output is left unattended. > In reversible logic, fan out of any gate output is not c) Toffoli Gate allowed; every output can be used only once. Figure 1 Few preferred Reversible Gates For example- Feynman gate is good solution for copying circuit. However, inclusion of Feynman gate definitely 3.2. Parity Preserving Reversible Gates increases the delay and cost but emerging technologies Fault tolerance is the property that enables a system to continue operating properly in the event of the failure of asks for power reduction. some its components. If the system itself made of fault One of the major constraints in reversible logic is to tolerant components, then the detection and correction of minimize the number of reversible gates used and faults become easier and simple. In communication and garbage outputs produced (Garbage output refers to the many other systems, fault tolerance is achieved by parity. output that is not used for further computations). Any Therefore, parity preserving reversible circuits will be the reversible gate performs the permutation of its input future design trends to the development of fault tolerant patterns only and realizes the functions that are reversible systems in nanotechnology. And a gating reversible. If a reversible gate has k inputs, and therefore network will be parity preserving if its individual gate is k outputs, then it is a k*k reversible gate. Any reversible parity preserving [13]. circuit design includes only the gates that are reversible. An efficient design should keep the number of garbage outputs to minimum. Parity checking is one of the widely used error detection mechanisms in digital logic and data communication systems. This is because most of the arithmetic functions is not parity preserving. If the parity of the input data is maintained throughout the (a) Feyman Double Gate (F2G) (b) Fredkin Gate (FRG) computation, no intermediate checking would be required Figure 2 Parity preserving reversible Gates [9]. A sufficient requirement for parity preservation of a A few parity preserving logic gates have been proposed in reversible circuit is that each gate be parity preserving the literature. Among them 3*3 Feynman Double gate [9]. Thus, we need parity preserving reversible logic gates (F2G) [10] depicted in Fig. 2(a) and 3*3 Fredkin gate to construct parity preserving reversible circuits. This (FRG) [13] depicted in Fig. 2(b) are one-through gates, paper presents few existing parity preserving reversible which means one of the inputs is also output. gates. Such gates can be used to realize any arithmetic module such as ripple carry adder, carry look-ahead Table 1: Table of Parity Preserving Feyman Double Gate adder, carry-skip logic, and multiplier/divisors. (F2G) The paper is organized as follows: the section II covers the detail on some reversible gates followed by fault tolerant gates. Section III covers the simulation results of fault tolerant gates. Section IV is the results and discussion part followed up by conclusion in section V. 3. REVERSIBLE GATES 3.1. Basic Reversible Gates There exist many reversible gates in the literature. Among them 2*2 Feynman gate (FG) [10], depicted in Fig. 1(a), 3*3 Peres gate (PG) [11], depicted in Fig. 1(b), Table 2: Table of Parity Preserving Fredkin Gate (FRG) 3*3 Toffoli gate (TG) [12], depicted in Fig. 1(c), have been studied extensively. Because of their simplicity and Volume 1, Issue 3, September – October 2012 Page 237 Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com Volume 1, Issue 3, September – October 2012 ISSN 2278-6856 From Table 1 and 2, it can be seen that the gates F2G and FRG are parity preserving respectively; since they satisfy A B C P Q R and any k*k reversible logic gate where the EX-OR of the inputs matches the EX-OR of the outputs will be parity preserving. Figure 5 Simulation result for toffoli gate 4. SIMULATION RESULTS The reversible & fault tolerant reversible architectures is modeled using VHSIC hardware description language (VHDL). The coding is done on Xilinx ISE8.2i for Virtex 4 target device: 4vlx60ff668-12. For simulation purpose the Modelsim6.2h has been used. Figure 3 Simulation result for feyman gate Figure 6 Simulation result for feyman double gate Figure 4 Simulation result for peres gate Figure 7 Simulation result for fredkin gate Volume 1, Issue 3, September – October 2012 Page 238 Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com Volume 1, Issue 3, September – October 2012 ISSN 2278-6856 The simulation result for reversible gates is shown in Fig. [4] Charles H.Bennett, "Logical Reversibility of 3, Fig. 4, and Fig. 5 for feyman, peres, and toffoli gate Computation," IBM Journal of Research and respectively. The simulation results shown in Fig. 6, and Development, vol. 17, no. 6, pp. 525 532, 1973. Fig. 7 corresponds to fault tolerant reversible feyman [5] Charles H.Bennett, "Time/Space Trade Offs for double gate, and fredkin gate respectively. The Reversible Computation," SIAM Journal of comparison table for reversible gates is detailed in table 3 Computation, vol. 18, pp. 766 776, 1989. [6] Rolf Landauer, "Uncertainty principle and Table3. Comparison table for Reversible gates minimal energy dissipation in the computer," Reversible Delay (nS) Slice 4-i/p Nature International Journal of Theoretical Physics, vol. 21, Gates LUT no. 3/4, pp. 283 297, 1982. Feyman 5.120 1 1 ----- [7] Charles H.Bennett, "The Thermodynamics of (4.156 logic, Computation A Review," International Journal of 0.964 route) Theoretical Physics, vol. 21, no. 12, pp. 905 940, Peres 5.133 1 2 ------ 1982. (4.156 logic, [8] M.F. Cowlishaw, “Decimal Floating-Point: 0.977 route) Algorithm for Computers”, Proc. 16th IEEE Symp. Toffoli 5.133 1 1 ------ Computer Arithmetic, pp. 104-111, June, 2003. (4.156 logic, [9] B. Parhami , “Fault tolerant reversible circuits”, 0.977 route) in Proceedings of 40th Asimolar Conf. Signals, Feyman 5.120 1 2 Fault Systems, and Computers, Pacific Grove, CA, pp. Double (4.156 logic, Tolerant 1726-1729, October 2006. 0.964 route) [10] R. Feynman, “Quantum mechanical computers”, Fredkin 5.132 1 2 Fault Optical News, vol. 11, 1985, pp. 11-20. (4.156 logic, Tolerant [11] A. Peres, “Reversible logic and quantum 0.967 route) computers”, Physical Review: A, vol. 32, no. 6, pp. . 3266-3276, 1985. [12] T. Toffoli, “Reversible computing”, In Automata, 5. CONCLUSION Languages and Programming, Springer-Verlag, pp. 632-644, 1980. Computer hardware has grown in power at an amazing [13] E. Fredkin and T. Toffoli, “Conservative logic”, pace ever since. One of the most important computational Intl. Journal of Theoretical Physics, pp. 219-253, resources is energy. The energy consumption in 1982. computation turns out to be deeply linked to the [14] R. Landauer, “Irreversibility and Heat Generation reversibility of the computation [14-18]. A computation is in the Computational Process”, IBM Journal of called reversible if its inputs can always be deduced from Research and Development, 5, pp. 183-191, 1961. its outputs. The primary objective of this paper was to [15] C.H. Bennett , “Logical Reversibility of gain insight into the Reversible Computation and its use Computation”, IBM J. Research and Development, for making devices energy efficient for long life. All pp. 525-532, November 1973. computations can be done, in principle, for zero cost in [16] M. S. Islam, and M. Rafiqul Islam, “Minimization energy. Using reversible gates & having parity preserving of reversible adder circuits”, Asian Journal of nature can help to build arithmetic circuits for energy Information Technology, vol. 4, no. 12, pp. 1146- efficient processor design with easy debugging nature. 1151, 2005. [17] D. Maslov, G. W. Dueck, and D. M. Miller, "Synthesis of Fredkin-Toffoli reversible networks," REFERENCES IEEE Trans. VLSI Systems, vol. 13, no. 6, pp. 765- [1] Rolf Landauer, "Irreversibility and Heat 769, 2005. Generation in the Computing Process," IBM Journal [18] J. W. Bruce, M. A. Thornton, L. Shivakumaraiah, of Research and Development, vol. 5, pp. 183 191, P.S. Kokate, X. Li, “Efficient adder circuits based on 1961. a conservative reversible logic gates”, In Proceedings [2] Tommaso Toffoli, "Reversible Computing," of IEEE Computer Society Annual Symposium on Automata, Languages and Programming, 7th VLSI, Pittsburg, PA, pp. 83-88, 2002. Colloquium of Lecture Notes in Computer Science, vol. 85, pp. 632 644, 1980. [3] Edward Fredkin and Tommaso Toffoli, "Conservative Logic," International Journal of Theoretical Physics, vol. 21, pp. 219 253, 1982. Volume 1, Issue 3, September – October 2012 Page 239