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					Versatile Calculator

                By:
           Dilip Patlolla
         Roopa Channappa
  Electrical and Computer Engineering
         University of Tennessee
                 Knoxville
        Abstract-Versatile Calculator

This Project deals with the design of a block, which is part of the
MIPS (Micro Computer without Interlocked Pipeline Stages)
Processor architecture. In this project, a Data Path and Control Unit
are implemented to carry the design. The block is designed to work
as a calculator where the user provides the instruction and the data
on which the operation is to be performed.
It involved the design, simulation, and demonstration using Xilinx
and Altera technologies using Field Programmable Gate Arrays
(FPGA). The system was described in Very High speed integrated
circuit Description (VHDL) and was synthesized using Synplicity
tools. After this post simulation was done and the design was placed
and routed on a SPARTAN-3 board using Xilinx and Altera tools.
                                                Design Flow
                            System Requirements



                       Architectural Specifications



   Behavioral Description                      Structural Description



                              Pre Simulation




Libraries                       Synthesis



                                Simulation


                        Placement and Routing


                       Physical Implementation
                     Specifications
Instruction Memory
Splitter
Register
ALU
Display Controller
BIST
Clock
                                                  Block Diagram

                                                                     BIST


input
                                Control Unit    opcode



 go


                                                                                  digit
 do
                   opcode               data1               carry
RESET
        Instruction Data 2                                  borrow    Display
                             Register                 ALU
          splitter                                                   Controller
BIST                Data 1
                                         MUX                result
                                                                                  seg




clock      CLOCK                        Result to memory
                                      System Requirements

                  Address(3:0)
                                  4             8
Slide switches(k13,k14,j13,J14)
                    Clock (T9)
                                  1
                                  1
                         BIST                   8     Seven
                     DO(M13)
                                  1
                                         FPGA         Segment
                                                      Display
                      Go(M14)
                                  1
                                                8
                                  1
                        RESET
Instruction Set Memory
                                Instruction set

15                10   9            4             0

       DATA 2              DATA 1        Opcode

     The instruction set is of 16 bit width
     With three parts
     DATA 1 of 6 bit length
     DATA 2 of 6 bit length
     Opcode of 4 bit length
                                            Opcodes
Operations

0000 – add       – {data 1 + data 2}
0001 – subtract  – {data 1 – data 2}
0010 – increment – {data1 + 1}
0011 – decrement – {data1 - 1}
0100 – complement – not {data1}
0101 – and        – { data 1 and data 2}
0110 – or         – { data1 nor data2}

1000 – add       – {result + data 1}
1001 – subtract   – {result - data 1 }
1010 – increment – {result+ 1}
1011 – decrement – {result - 1}
1100 – complement – not {result}
1101 – and        – { result and data 1 }
1110 – or         – { result or data 1}
                      Instruction Splitter




This block splits the instruction set into the three
parts of data1, data2 and op code
                                                      Splitter

                                                              BIST

RESET                    Control Unit

 go


                                                                           digit
 do
          opcode                                     carry

        Instruction
          Data 1                                     borrow    Display
Input                 Register                 ALU
          splitter                                            Controller
BIST
                                  MUX                result
                                                                           seg
          Data 2



clock      CLOCK                 Result to memory
Register
                                                              Register

                                                                       BIST
                                 Control Unit
input
                                 Control Unit    opcode



 go                                Reg_write
                                           s
                                           e
                                           L                                        digit
 do
                   opcode                                     carry
RESET
        Instruction Data 2
                         1                                    borrow    Display
                             Register
                             Register                   ALU
                                                       ALU
          splitter                                                     Controller
BIST               Data 2
                   Data 21
                                           MUX
                                          MUX                 result
                                                                                    seg




clock      CLOCK                         Result to memory
                                       Multiplexer
Sends the output based on the select input received from
Control Unit
                                                       Multiplexer

                                                                           BIST




                                          Sel-1
                                          Sel-0
                                 Control Unit
                                                  opcode
input


 go                    Reg_write

                                                                                        digit
 do
                   opcode                                         carry
RESET
        Instruction Data 1                                        borrow    Display
                             Register                       ALU
          splitter                                                         Controller
                   Data 2
                                           MUX                    result
                                                                                        seg
BIST               Data 2



clock      CLOCK                         Result to memory
Arithmetic & Logic Unit
                              Arithmetic Logic Unit

                                                                 BIST


input
                                  Control Unit




                                                        opcode
 go


                                                                              digit
 do
                    opcode               Reg_out1        carry
RESET
        Instruction                                               Display
                             Register                   ALU
                                                        - Sign
          splitter                            MUX-out            Controller
BIST
                                        MUX                                   seg
                                                        result


clock       CLOCK
                                ALU
Computes the result.
Indicates the Carry or ‘–’ sign based on
the operation result
Output is zero when reset
                                 Control Unit
Sends operation codes to ALU
Sends the required control codes to the Multiplexer and
Memory based on the input opcode
                                                       Control Unit

                                                                          BIST


input                  O
                                  Control Unit
                       P




                                                        opcode
                       C




                                                 SEL
 go                    O
                       D             Reg_write
                       E
                                                                                       digit
 do
                      opcode                                     carry
RESET
        Instruction                                              borrow    Display
                               Register                 ALU
          splitter                                                        Controller
BIST
                                             MUX                 result
                                                                                       seg




clock      CLOCK
                           Display Controller
Accepts a 6-bit binary number between 0 and 63 (output of
the ALU)
Converts binary number to a 2-digit BCD representation
Generates appropriate logic levels to drive 7-segment display
                              Display Controller


                                        Digit-1
input                              8
                                                  Result
          carry
 go
                       Display     8    Digit-2
        ALU
          - sign
 do
                      Controller
          result                   8
RESET
                                        Digit-3

                                       [- Sign]
BIST



clock
              CLOCK
Final Single Block Diagram
Simulation-Part1
Simulation-Part2
RTL Block Diagram
RTL Schematics-ALU
RTL Schematics-BCD Display
RTL Schematics-DisplayController
RTL Schematics-Instruction Set
RTL Schematics-MUX
RTL Schematics-Register
RTL Schematics-Splitter
Xilinx Layout
Altera Layout
                 Flow Charts
ALU Flow chart
              Flow charts
BCD Display
               Flow charts
Control Unit
                     Flow charts
Display Controller
                  Flow charts
Instruction Set
      Flow charts
MUX
            Flow charts
Registers
           Flow charts
Splitter
                                 Block Diagram
Left part of Block Diagram generated
                              Block diagram-2
Right part of the block diagram
Single Block Diagram
               Post Simulation
Using Xilinx
Design Summary
Ucf File
  Device Utilization Summary


Number   of   BUFGMUXs          3 out of 8       37%
Number   of   External IOBs    29 out of 173     16%
Number   of   LOCed IOBs       29 out of 29     100%
Number   of   Slices          159 out of 1920     8%
Number   of   SLICEMs           0 out of 960       0%
MIPS Processor
             Scope for Development
These cores can be mixed with add-in units such
as SIMD systems, various input/output devices,
etc.
MIPS cores have been commercially successful,
now being used in many consumer and
industrial applications. MIPS cores can be found
in newer Cisco and Linksys routers, cable
modems and ADSL modems, smartcards, laser
printer engines, set-top boxes, robots, handheld
computers, Sony PlayStation 2 and Sony
PlayStation Portable.
              Summary and Conclusion

      This is an approximate basic sub part of a MIPS processor which
is shown to work as a calculator which can be further developed into a
ready to use core in MIPS architecture.
                          References
551 Homeworks and handouts
www.Google.com
http://en.wikipedia.org/wiki/MIPS_architect
ure

				
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posted:11/16/2012
language:English
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