ADC and Software Defined Radio

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Software-Defined Radio and Wideband ADCs



October, 2012




TI Information – Selective Disclosure
Agenda

                                  1     Introduction to Software-Defined Radio

                                  2     Applications & benefits of SDR

                                  3     SDR ADC requirements

                                  4     JESD204B

                                  5     TI’s wideband ADCs for SDR

                                  6     TI’s complete SDR signal path solution


TI Information – Selective Disclosure                                            2
Delivering MORE Together




Introduction to Software-Defined Radio




TI Information – Selective Disclosure
What is Software-Defined Radio (SDR)?
                                        SDR Typical Input Signal Conditions
                                                                     Undesired
         Undesired                                        Desired     Channels Desired
          Channels                                        Channel              Channel


                                                                                            fIN
                                    Input Bandwidth
                                                          Channel Bandwidth
                                         • Channel bandwidth << input bandwidth
 Characteristics
                                         • Multiple channels received simultaneously
                                         • Any application requiring wide input bandwidth
                                         • Any application with frequency flexibility
     Example
                                         • Any application with multiple mixing stages
    Applications
                                         • Any application processing multiple signals
                                         • Any combination of above…
TI Information – Selective Disclosure                                                             4
SDR Applies to Many Applications

     Military                           Consumer           Comms            SDR, T&M
         Radar                          Media Servers /   uWave Backhaul
                                             STB



                                          Auto Radar
                                                                               Data Acq.
Comms & SIGINT                                                Basestation




                                        Game Systems


                                                                            Test equipment
                                                          FTTH


TI Information – Selective Disclosure                                                      5
What Market Trends are Driving SDR?

       Multiple                                    • Smaller detectors
      Channels                           Radar         • Better resolution
                                                       • 1000s of channels
  Demand for
Programmability                                    • More TVs per home / bldg
                                        Gateways
                                                   • More services
Increased Data
    Traffic
                                          Sat
                                                   • Greater data capacity
      Better                            Comms
    Resolution
                                                   • More users
     The Usual                            BTS
                                                   • Greater data demands
     Suspects

TI Information – Selective Disclosure                                           6
What Market Trends are Driving SDR?

       Multiple
                                                   • Frequency hopping
      Channels                           Radar
                                                   • Variable waveforms

  Demand for
Programmability                                    • Upgrade/downgrade service
                                        Gateways
                                                   • Change channels
Increased Data
    Traffic
                                         SigInt    • Scan comms bands
      Better
    Resolution
                                                   • Universal 2G/3G/4G platform
     The Usual                            BTS
                                                   • Increase/decrease capacity
     Suspects

TI Information – Selective Disclosure                                         7
What Market Trends are Driving SDR?

       Multiple
      Channels                           uWave
                                                   • Increased wireless data
                                        Backhaul
  Demand for
Programmability                                    • Demand greater data-
                                        Gateways     handling capacity
Increased Data
    Traffic
                                         Cable     • Increased wireless data
                                        Backhaul   • Increased cable services
      Better
    Resolution

     The Usual                            BTS      • Increased data usage
     Suspects

TI Information – Selective Disclosure                                           8
What Market Trends are Driving SDR?

       Multiple
                                          Auto     • Resolve smaller objects
      Channels
                                         LIDAR     • Better motion information

  Demand for
Programmability                                    • Higher-order modulation in
                                        Gateways     next-gen standards
Increased Data
    Traffic
                                         Optical   • Higher-order modulation for
                                        Backhaul     greater capacity
      Better
    Resolution
                                                   • Increased coverage
     The Usual                            BTS
                                                   • Increased capacity
     Suspects

TI Information – Selective Disclosure                                            9
What Market Trends are Driving SDR?

       Multiple
                                         Lower     • EnergyStar, CoC
      Channels
                                         Power     • Operational expenses

  Demand for
Programmability                         Smaller    • Lower complexity
                                         Area      • Cheaper boards
Increased Data
    Traffic
                                         Reduce    • Common RF design across
                                        Redesign     platforms
      Better
    Resolution
                                         Lower
     The Usual                                     • Eliminate components
                                         Costs
     Suspects

TI Information – Selective Disclosure                                       10
TI’s Wideband ADCs
Enable Software Defined Radio Architectures
                            Traditional Hardware-Defined Radio Solution
                                                          Narrowband
                                                          Digital Signal



                                                                           DSP


                                                                                 DIGITAL
  ANALOG




TI Information – Selective Disclosure                                                11
Disadvantages of HDR

           High analog                  System requires numerous splitters, oscillators,
           complexity                    narrowband filters, and other components


       RF interference                  Oscillators interfere, requiring shielding



              High cost                 High component count forces large board area


                                        Adding/moving channels requires analog re-
     Limited flexibility
                                         design or tuning


  Poor power scaling                    Analog power scales with channel count



TI Information – Selective Disclosure                                                12
TI’s Wideband ADCs
Enable Software Defined Radio Architectures
                            Traditional Hardware-Defined Radio Solution
                                                                Narrowband
                                                                Digital Signal



                                                                                 DSP


                                                                                                  DIGITAL
  ANALOG


                                   Software-Defined Radio (SDR) Solution
                                                                                 Narrowband
  ANALOG                                                                         Digital Signal
                                           DIGITAL

                                                Wideband
                                          TI   Digital Signal
                                                                                                  DSP
                                        ADC




            Lower cost, lower power, smaller size, & fully flexible radio
TI Information – Selective Disclosure                                                                 13
Advantages of SDR

            Low analog                  Solution eliminates mixers, oscillators, amplifiers,
            complexity                   splitters, and filters

  No RF interference,                   Oscillators and channel filters implemented in
  higher performance                     digital


               Low cost                 Low component count allows small board area


                                        Adding channels requires no analog re-design
  Unlimited flexibility
                                        Moving channels requires no analog tuning

      Excellent power                   Analog power constant for 2 or 200 channels
          scaling                       Reduces system power requirements

TI Information – Selective Disclosure                                                  14
Delivering MORE Together




Example Applications of SDR




TI Information – Selective Disclosure
SDR for Basestations, Repeaters, SIGINT
Reduces Component Count: Integrated Solution
                  IF-Sampling Subsystem


                                                                              DSP



   Old: IF-Sampling
   New: RF-Sampling                                                          Benefits
                                                                      • Fewer components
                                                                      • Smaller board
                                                Time

                                                                      • Lower power
                                               Area




                                                                DSP   • Flexible digital mixing
                                        Cost




                                                                        & filtering
                                                                      • Less interference
                                                                      • Up to 2.5-GHz Nyquist
TI Information – Selective Disclosure
                                                       RF ADC
                                                                                        16
SDR for Military Radar, Data Acquisition
Reduces Size, Weight, & Power



                                        x100 to 1000   Analog Ctrl
 HDR                                                                             DSP
Solution

                                                       Analog Ctrl

      Large Nyquist zone enables                          High-IF/RF-Sampling enables
      • Combine multiple channels                         • Eliminate freq conv stage
                                                          • Digital control of freq



 SDR
Solution                                 x10 to 100           Ctrl in DSP       DSP

                                                                       RF ADC
                                                                       RF ADC
TI Information – Selective Disclosure                                             17
SDR for Cable/Sat/RFoG STBs & Gateways
Lower Power, Lower Cost, More Flexible
                                        Traditional Solution




                                                                          Proc




                                         TI’s SDR Solution


                                                                          Proc


                    Move signal processing from analog into digital
                  Lower power, lower cost, smaller size, more flexible
TI Information – Selective Disclosure                                       18
SDR for Media STB & Gateway
Fully Flexible DOCSIS3.0
       Video      DOCSIS Band                          Video




• DOCSIS Today                                                   f
     – Channels bonded in contiguous, reserved band
     – Limited by current DOCSIS tuners




                                                                 f
• Fully Flexible DOCSIS
     – No limit on number of DOCSIS channels or their location
            • Greater bandwidth & greater efficiency


TI Information – Selective Disclosure                            19
SDR for Microwave Backhaul (I)
Reduce Size to Enable ODU/IDU Integration



  Old                                                                   DSP
Solution


                            Outdoor Unit                          Indoor Unit



                                                             SDR enables
                                                          • Eliminate freq conv
 SDR                                                        stage
Solution                                            DSP   • Integrate ODU and
                                                            IDU into single unit

                                           TI ADC
                            Outdoor Unit
TI Information – Selective Disclosure                                     20
  SDR for Microwave Backhaul (II)
  Increase Data Capacity with Wider Channels
            Excellent noise & distortion                          • Increase modulation order
            Nyquist zone up to 2.5 GHz                            • Increase channel bandwidth
                         increases Data Capacity

4096-QAM
                           Increased Modulation




1024-QAM

256-QAM
                                                                                   TI ADCs for SDR
 64-QAM                                                                                  Capability
 16-QAM
                                                   Increased Channel BW Increases Data Capacity
 DPQPSK
                       28MHz 56MHz 112MHz 250MHz                           500MHz     750MHz 1250MHz
                    Traditional band channels                               E-band channels
  TI Information – Selective Disclosure                                                           21
SDR for Spectrum Analyzer
Reduce Frequency Sweep Time, Size, Cost, & Power
                                        Traditional Solution


                                                                          Proc


                                                             Frequency
                                                             sweep ctrl

                                         TI’s SDR Solution


                                                                          Proc



                         Eliminate or reduce analog frequency sweeping
                            Lower power, lower cost, faster response

TI Information – Selective Disclosure                                            22
SDR for Multi-band Wireless Comms
                                        Traditional Solution

 1920-1980 MHz


                                                                      Proc
 2500-2570 MHz



                                         TI’s SDR Solution


                                                                      Proc
1920-2570 MHz

               Move signal processing from analog into digital
            Reduce # of filters, lower cost, smaller size, more flexible
TI Information – Selective Disclosure                                       23
SDR for Satellite TV Distribution
                                          Traditional Solution


                                                                              to in-bldg
                                                f1                              cable
                        M:N
    LNB                                                             Analog
                       Analog
                                                                     Sum
                        Mux


                                               fN

                                              TI’s SDR Solution
                                                                             to in-bldg
                                        Dig                       Dig          cable
          LNB
                                        Mux                       Sum


                      Eliminate analog signal processing
             Lower power, lower cost, much higher channel capacity
TI Information – Selective Disclosure                                                24
SDR in 60 Seconds




                                   Move up   • Digitize closer to the input of the system
                                    ADC      • Requires very high BW, high-fS ADCs


TI Information – Selective Disclosure                                                       25
SDR in 60 Seconds




                          Eliminate analog        • Remove analog frequency-conversion,
                             processing             gain, and filtering stages



                                   Move up   • Digitize closer to the input of the system
                                    ADC      • Requires very high BW, high-fS ADCs


TI Information – Selective Disclosure                                                       26
SDR in 60 Seconds




           Implement signal processing                  • Build frequency-conversion, gain,
                in digital domain                         and filtering in DSP/FPGA



                          Eliminate analog        • Remove analog frequency-conversion,
                             processing             gain, and filtering stages



                                   Move up   • Digitize closer to the input of the system
                                    ADC      • Requires very high BW, high-fS ADCs


TI Information – Selective Disclosure                                                       27
SDR in 60 Seconds

                                                             •   Lower power
                                                             •   Smaller area
                        Reap the rewards!                    •   Programmable/configurable
                                                             •   Lower cost


           Implement signal processing                  • Build frequency-conversion, gain,
                in digital domain                         and filtering in DSP/FPGA



                          Eliminate analog        • Remove analog frequency-conversion,
                             processing             gain, and filtering stages



                                   Move up   • Digitize closer to the input of the system
                                    ADC      • Requires very high BW, high-fS ADCs


TI Information – Selective Disclosure                                                       28
Summary
ADC Trends to Address SDR

               ADC Trend                            SDR Benefit

                                          Larger data bandwidth, increased
      Higher Sampling Rate
                                                 frequency flexibility

                                        Easier filtering, increased flexibility in
     Larger Input Bandwidth
                                                          digital

                 Input Buffers          Relax high-fS ADC driver requirements

                                          Reduce pin count, system design
           Serialized Outputs
                                                    complexity

        Lower Power, Better               Reduce pin count, system design
           Performance                              complexity
TI Information – Selective Disclosure                                            29
Delivering MORE Together




SDR ADC Requirements




TI Information – Selective Disclosure
    The Challenge


                 “What is the ENOB?”



                                                                          First response to SDR
                                                                          proposal
                                                                          - Many, many customers




• http://www.eetimes.com/design/microwave-rf-design/4208799/Software-Defined-Radio--Don-t-Talk-to-Me-about-ENOBs--Part-1-of-2
• http://www.eetimes.com/design/microwave-rf-design/4208799/Software-Defined-Radio--Don-t-Talk-to-Me-about-ENOBs--Part-2-of-2




     TI Information – Selective Disclosure                                                                         31
ADC Performance Specifications for SDR
Noise

     Noise                              • Determines overall system sensitivity
  Performance
                                        • What is the smallest signal that can be
    Traditional                           received
    ADC Spec                                Max Input


 Limitations of
Traditional Spec

                                            Min Input
                                                         Noise
      Correct
     ADC Spec                                           Ch BW



TI Information – Selective Disclosure                                             32
ADC Performance Specifications for SDR
Noise

     Noise                              • Signal-to-noise ratio (SNR)
  Performance
                                          – Integrate noise over entire Nyquist
                                            bandwidth
    Traditional
    ADC Spec


 Limitations of
Traditional Spec


      Correct
     ADC Spec                                              Ch BW                  fS/2



TI Information – Selective Disclosure                                                    33
ADC Performance Specifications for SDR
Noise

     Noise                              • SNR is irrelevant for SDR
  Performance
                                          – Channel bandwidth << Nyquist bandwidth

    Traditional
    ADC Spec


 Limitations of
Traditional Spec                                 Don’t              Don’t
                                                 Care               Care
      Correct
     ADC Spec                                            Ch BW               fS/2



TI Information – Selective Disclosure                                                34
ADC Performance Specifications for SDR
Noise

     Noise                              • Noise density / floor
  Performance
                                          – Reflects noise only in the channel
                                            bandwidth
    Traditional
    ADC Spec


 Limitations of
Traditional Spec
                                          Noise density
      Correct                               in-band
     ADC Spec                                              Ch BW



TI Information – Selective Disclosure                                            35
Correct ADC Noise Spec
ADC12D1800RF has “16-bit” Noise Floor

                  16-bit, 160-MSPS              12-bit, 3.6-GSPS




     Noise floor                            Noise floor
                   -157 dBFS/Hz                  -154 dBFS/Hz

                        ADC16DV160               ADC12D1800RF

                       “12-bit” ADC12D1800RF only 3-dB worse
                        noise floor than “16-bit” ADC16DV160
TI Information – Selective Disclosure                              36
ADC Performance Specifications for SDR
Distortion

   Distortion                           • Determines overall system sensitivity
  Performance
                                          – Measures impact of harmonic distortion
                                          – Measures impact of interferers and adjacent
    Traditional                             channels (intermod products)
    ADC Spec
                                                                          Harmonic
                                                Adjacent Ch
                                                                            Dist
 Limitations of
                                                          Desired
Traditional Spec


      Correct
     ADC Spec                            Intermod Dist   Ch BW                  fS/2



TI Information – Selective Disclosure                                                  37
ADC Performance Specifications for SDR
Distortion

   Distortion                           • Spurious-free dynamic range (SFDR)
  Performance
                                          – Measure spurious content over the entire
                                            Nyquist bandwidth
    Traditional
    ADC Spec
                                                                      Third Harmonic is
                                                                      often highest tone
 Limitations of
Traditional Spec


      Correct
     ADC Spec                                            Ch BW                   fS/2



TI Information – Selective Disclosure                                                   38
ADC Performance Specifications for SDR
Distortion

   Distortion                           • SFDR is irrelevant for SDR
  Performance
                                          – Channel bandwidth << Nyquist bandwidth
                                          – Can frequency-plan to keep worst spurs
    Traditional                             out-of-band
    ADC Spec


 Limitations of
Traditional Spec                                 Don’t             Don’t
                                                 Care              Care
      Correct
     ADC Spec                                            Ch BW               fS/2



TI Information – Selective Disclosure                                                39
ADC Performance Specifications for SDR
Distortion

   Distortion                           • Intermodulation distortion (IMD)
  Performance                             – Reflects spurious content that may fall in-band
                                            due to adjacent channels/interferers
                                        • Higher-order harmonics & interleaving
    Traditional                           – Artifacts of unique ADC architecture can be
    ADC Spec                                reduced by frequency planning
                                        • Noise-power ratio (NPR)
                                          – Reflects spurious and noise content in a notch of
 Limitations of                             a fully-loaded spectrum
Traditional Spec

                                              In-band
      Correct                                distortion
     ADC Spec                                               Ch BW



TI Information – Selective Disclosure                                                         40
Frequency Planning Example
RF-Sampling UMTS FDD Band 3 Uplink




                              Band of Interest = 1710 to 1785 MHz
                                  Choose fS = 2457.6 MSPS
TI Information – Selective Disclosure                               41
Delivering MORE Together




JESD204B




TI Information – Selective Disclosure
Introduction to JESD204B
• Standard that defines serial link between data converters (ADCs & DACs) and
  other devices such as FPGAs, DSPs, ASICs and clocking devices
• Primary objective is to simplify the digital data interface between devices.
• Data clock is embedded in the data stream

      Dual 14bit ADC                                                        Dual 14bit ADC
      • DDR LVDS                                                            • JESD204B
      • 15 diff pairs                                                       • 4 diff pairs
        (14 data + clock)




                                        Significantly reduce output pin &
                                         trace count, simplifying design
TI Information – Selective Disclosure                                                    43
The Benefits of JESD204B

                                        Simplify board routing with fewer lanes


                                        Reduce # of pins, allowing for smaller packages

                                        Simplify layout with embedded clock – no need
                                        to match LVDS trace lengths

                                        Flexible and scalable solution (multi devices)




TI Information – Selective Disclosure                                                     44
JESD204B Evolution

                                                 Support for
                                                accurate multi-
                                                 device sync

                           Support lanes up    Support lanes up
                            to 3.125 Gbps       to 12.5 Gbps

                            Support multiple   Support multiple
                              converters         converters

                            Support multiple   Support multiple
                                lanes              lanes
                               JESD204A          JESD204B
                                        2008         2011



TI Information – Selective Disclosure                             45
JESD204 Feature: 8b/10b encoding
• Vital for clock recovery – 20% overhead ensures there will always be a min
  amount of data transitions even if a long string of 0s or 1s are being
  transmitted.
• Ensures digital data is DC balanced allowing AC-coupling which virtually can
  accommodate any common mode voltage.
• Built in error detection from the 8b/10b look up table




                                        Example Encoding
               8bit Data                                   10bit Data
               0000 0000                                   10 0111 0100
               0000 0001                                   01 1101 0100




TI Information – Selective Disclosure                                          46
Synchronization – Subclass x
Multiple transmitters and receivers can be synchronized to obtain a deterministic
latency across multiple devices.


• Subclass 0:
   – No support for deterministic latency, same as JESD204A
• Subclass 1:
   – Uses external SysRef signal for synchronization
   – TI currently supports subclass1 for high-speed ADCs and DACs
• Subclass 2:
   – Uses external SYNC~ signal for synchronization and alignment




TI Information – Selective Disclosure                                          47
Subclass 1 SysRef: Example
• Multiple ADCs and DACs can be synchronized across a system using the
  SysRef signal
• SysRef signals and device clocks need to be distributed with matched length to
  all devices in order for the internal “local multi frame clocks (LMFC)” to be
  synchronized properly. This ensures that the SysRef signal gets processed at
  the same instant across all devices.
• JESD204B traces don’t have to be length matched




TI Information – Selective Disclosure                                        48
JESD204B Signals
There are three basic signals pertaining to the TI JESD204B interface:
• SysRef:                           Used for synchronization and alignment
• SYNCb:                            Used for initial lane alignment between transmitter and
                                    receiver on a JESD204B link
• D0/D1:                            Differential pair carrying the data to the DAC or from the ADC




TI Information – Selective Disclosure                                                            49
Basic Building Blocks Inside the JESD204B
• Transport Layer:
   – handles data mapping into 8bit packets
   – Includes mapping data across multiple data converters
• Scrambler:
   – Optional scrambling/descrambling of data using PRBS pattern
• Link Layer:
   – Handles link establishment and initial lane alignment




TI Information – Selective Disclosure                              50
JESD204B Frame Formatting
 JESD204B offers flexibility in formatting the frames
 • Ability to trade off serial data rate versus number of lanes
    – E.g. 16bit ADC runs at 250Msps: output data could be 2 lanes @ 2.5Gbps
      or 1 lane at 5Gbps
 • More efficiently pack frames
    – E.g. 12bit ADC at 250Msps: 4 samples can be packed into 6 octets thus
      reducing data rate by 25%: 1 lane at 3.75Gbps vs 5Gbps

                                                         LMFS = 4211                                                                                                                          LMFS = 3243                                                                           LMFS = 2221
Example:
                                              B 0[7:0] B 0[15:8] A0[7:0] A0[15:8]

                                                                                    B 1[7:0] B 1[15:8] A1[7:0] A1[15:8]

                                                                                                                          B 2[7:0] B 2[15:8] A2[7:0] A2[15:8]




                                                                                                                                                                B 1[15:8] A2[15:8] A0[15:8]



                                                                                                                                                                                                          B 2[15:8] B 0[15:8] A1[15:8]




                                                                                                                                                                                                                                                    B 0[15:8] A0[15:8]



                                                                                                                                                                                                                                                                                     B 1[15:8] A1[15:8]



                                                                                                                                                                                                                                                                                                                     B 2[15:8] A2[15:8]
                                                                                                                                                                                               A0[7:0]



                                                                                                                                                                                                                                         A1[7:0]




                                                                                                                                                                                                                                                                         A0[7:0]



                                                                                                                                                                                                                                                                                                          A1[7:0]



                                                                                                                                                                                                                                                                                                                                          A2[7:0]
Dual 16bit ADC                      La ne 0

Frame formatting

                                                                                                                                                                                               A2[7:0]



                                                                                                                                                                                                                                         B 0[7:0]




                                                                                                                                                                                                                                                                         B 0[7:0]



                                                                                                                                                                                                                                                                                                          B 1[7:0]



                                                                                                                                                                                                                                                                                                                                          B 2[7:0]
for 1 or 2 lanes per                La ne 1
ADC or 3 lanes per                                                                                                                                                                             B 1[7:0]



                                                                                                                                                                                                                                         B 2[7:0]
2 ADCs
                                    La ne 2


                                    La ne 3


 TI Information – Selective Disclosure                                                                                                                                                                                                                                                                                                          51
JESD204B Summary

                                                 Advantage                      Disadvantage


                                             Simplified IO routing        More focus on signal integrity
  Board/System Design
                                              and board design              especially with >3Gbps


                                         Smaller packages and routing      Potentially more expensive
                  Cost                   require less board space and       FPGAs to accommodate
                                                  board layers                   SERDES links

                                           May save power at slower
                                                                          Higher power consumption
    Power Consumption                    sampling rates when using less
                                                                          per lane than parallel LVDS
                                        lanes (e.g. 2 ADCs on one lane)




TI Information – Selective Disclosure                                                              52
LMK04828
JESD204B Compliant Clock Jitter Cleaner

Features
Dual Loop PLLatinum PLL Architecture                                    1 Output of
                                                                        Buffered VCXO
Holdover mode when input clock is lost
                                                                                   Dual VCO
 VCO to support 2457.6 and 2949.12 MHz
Option of using external VCO for MC GSM applications
                                                                 PLL         PLL
Supports Device clocks and SYSREF as per JESD204B
Digital Delay, Analog Delay and 0-delay mode                     SPI

15 differential outputs:                                         SYNC
• 14 from PLL2 (LVDS, LVPECL, HSDS): 7 dev, 7 sys
• 1 from PLL1 (LVDS, LVPECL, LVCMOS)                                       Dist
2 inputs
Output Clock Amplitude @ 1536 MHz = 700 mVOD (LVPECL16, 240 Ω)
Output Clock Amplitude @ 3072 MHz = 470 mVOD (LVPECL16, 240 Ω)
                                                                      7 output pairs
                                                                  14 outputs in 7 pairs
Output Clock Amplitude @ 3072 MHz = 620 mVOD (LVPECL16, 120 Ω)      provide 14 outputs
                                                                  Pairs configurable as:
3.15 V to 3.45 V power supply voltage                            (DevCLK, SYSREF) or
                                                                   (DevCLK, DevCLK)
Package LLP64
                                                                   DevCLKs in a pair
                                         Samples: Now               share frequency

TI Information – Selective Disclosure                                                53
Delivering MORE Together




TI Wideband ADCs for SDR




TI Information – Selective Disclosure
TI’s Wideband ADCs for SDR
Complete Product Portfolio

                              16V370
16-bit
                  ADS42x69


14-bit            ADS42x49ADS5474


                                               ADS                   12D1800/                       12D1800/
12-bit                               ADS540x   5400                       RF                             RF
ADC                                 ADS    12D1000/            12D1600/ 12D1000/            12D1600/ 12D2000
                                54(RF)63         RF                 RF        RF                 RF        RF

10-bit
                                              10D1000          10D1500          10D1000   10D1500
ADC
                                                                                         08D15x0
7/8-bit                                                        08D15x0                              ADC08xxx
                                    08Dx500   08D10x0                           08D10x0 08(B)3000           LM97600
                                                                                                     S700xxxx
 ADC                                                           07D1520                   07D1520
   Dual               250          500        1000   1500     2000 3000                              4000 5000
   Single                                         Sampling Rate (MSPS)
TI Information – Selective Disclosure                                                                           55
   (Products Highlighted in RED are New Arrivals, and Dark Grey are Roadmap Products)
Delivering MORE Together




Soon-To-Release Wideband ADCs for SDR




TI Information – Selective Disclosure
                                                                                                  Sampling now

 ADS5402/5404                                                                                     Production 1Q2013

 Dual 12-bit, 800/500MSPS ADC

Features                                                Benefits
• 800MSPS, 500MSPS
                                                        • 800Msps dual provides 800MHz linearization bandwidth
• 62dBFS SNR, 80dBc SFDR at 350MHz Fin                  in quadrature observation path
• 2x12-bit DDR LVDS Outputs                             • Improved receiver sensitivity in receivers and transmit

• Buffered Analog Inputs                                adjacent channel leakage ratio when used in pre-
                                                        distortion power amplifier feedback
• Optional 2x Decimation Filter
                                                        • Simple, common FPGA interface
• 3.3/1.8V Supplies, 950mW/ch total power
                                                        • Input buffer eliminates kick-back, aids impedance
• Low 1.1Vpp Analog Full-scale Inputs
                                                        matching, signal transfer and gain flatness
• 12x12mm 196ball BGA                                   • Over 60% power savings from 5V/3.3V ADS5400
                                                        • 1.1Vpp improves linearity of driving amplifier, while
Applications
                                                        also providing 4dB higher SNR at almost half the input
• Multi-mode, multi-standard wireless infrastructure,
  pre-distortion feedback ADC                           swing from ADS5400
• Wideband LOS Backhaul
• Test and measurement instrumentation
• Software defined radios
• Radar, Signals intelligence and jamming
• General purpose high speed digitizers



  TI Information – Selective Disclosure                                                                      57
                                                                                              Sampling now

  ADS42B49                                                                                    Production 4Q2012

  Dual 14-bit 250MSPS ADC with Buffered Inputs
Features                                     Benefits
• Buffered Inputs                            • High impedance input provides
• Low Power:                                         • better filter matching options
       • 415mW/channel LVDS Interface                • eliminates sample/hold kick-back
• 70 dBFS SNR and 85 dBc SFDR at 170MHz IF           • provides a flatter gain response across frequency
       • 93dBc typical non HD2/3             • High performance
• 6 dB gain in 1 dB steps                            • Enables 3G/LTE cellular base stations and repeaters
• 9x9mm, 64-pin QFN package                          to receive weak signals, reduce dropped-calls and
• Selectable DDR LVDS or CMOS outputs                improve data throughput.
• 3.3/1.8V Analog/Digital supplies
                                                                                                 LMK04800

                                                              LMH6521        ADS42B49               CLOCK
Applications                                                                      ADC

• Wireless communication:                                                         ADC

       • Basestation receivers                           IF (Heterodyne) Diversity Receiver
       • Diversity or Quadrature IQ           LMX2581                                          GC5330
                                              TRF3765
       • Wideband Power Amp Linearization                                                         DUC
                                                LO                    OR
• Software Defined Radios                                                                         DDC
• Test and measurement equipment                            Direct Conversion Receiver
                                                  Antenna
                                                             IQ DEMOD        ADS42B49
                                                                                  ADC
                                                                                  ADC

    TI Information – Selective Disclosure                                                               58
                                                                                                                            Samples Oct2012
ADS42JB69 / ADS42LB69 Dual 14/16-Bit 250 MSPS ADC
Low-Power, JESD204B / DDR/QDR LVDS
                                                                                 DDR/QDR LVDS                       JESD204B
Features
• Dual Channel 250Msps                                          14 bit           ADS42LB49                          ADS42JB49

• Pin/pin compatible 14 & 16bit ADCs                            16 bit           ADS42LB69                          ADS42JB69
• Low Power:
       • 775mW/ch (JESD)                                      ADS42JB69
                                                                                          Digital                                      DA0P/M
       • 740mW/ch (DDR / QDR LVDS)                   INAP/M
                                                                                16bit
                                                                                          Block
                                                                                                                JESD204B
                                                                                ADC                               Digital
                                                                                        Gain/Offset
                                                                                                                                       DA1P/M
• Analog Input Buffer with High Impedance Input                                         Correction

                                                                       Divide
                                                                                                        PLL
• Flexible Input Clock Buffer with /1,/2,/4        CLKINP/M              by
                                                                       1,2,4
                                                                                                      x10/x20
                                                                                                                                       SYNCP/M

• Aperture jitter: 80fs                           SYSREFP/M


• SNR at 170MHz IF: 73.3dBFS                                                              Digital
                                                                                          Block
                                                                                                                                       DB0P/M
                                                                                16bit                           JESD204B
                                                     INBP/M
                                                                                ADC                               Digital
• SFDR at 170MHz: 89dBc typ (HD2,3)                                                     Gain/Offset
                                                                                        Correction
                                                                                                                                       DB1P/M


           at 170 MHz: 100dBc typ, non HD2,3
                                                              Common                        Configuration
                                                      VCM
                                                               Mode                          Registers
• Crosstalk at 170MHz: 100dB
• Input full scale: 2.0-to-2.5Vpp




                                                                                           RESET
                                                                                             SEN
                                                                                            SCLK
                                                                                           SDATA
                                                                                           SDOUT
• JESD204B Digital Interface up to 3.2Gbps
       • Subclass 0, 1, 2
• 3.3V/1.8V Analog/Digital supplies
• 9x9mm, 64-pin QFN package
 TI Information – Selective Disclosure                                                                                            59
                                                                                                   Sampling now

    ADC16V370                                                                                    Production 4Q12


     Industry’s Fastest 16-bit ADC @ 370 MSPS
Features                                            Benefits
   Buffered inputs
   Input phase and amplitude mismatch correction      Industry’s fastest 16-bit ADC offers up to 185 MHz of
   3-dB BW @ 100 W: 579 MHz                            useable bandwidth, allowing for wideband receivers and
   Useable BW: 325 MHz                                 simplified input filtering
   Power: 1.8 W                                       Input buffer eases input filter impedance matching,
   SFDR @ 85 MHz: 90 dBFS                              reduces driver requirements
   Noise floor: -155 dBFS/Hz                          Programmable input phase & amplitude correction to
   DDR LVDS outputs                                    simplify input filter tolerances / matching
   Input full-scale range: 1.6 Vpp
   No external reference bypassing required
   Package: 68-pin QFN, 10 x 10mm
                                                                      ADC16V370 block diagram
Applications
 Multi-carrier, multi-standard/multi-mode
  basestations
 Digital pre-distortion (DPD)
 High-IF sampling receivers
 Medical imaging
 Test & measurement


    TI Information – Selective Disclosure                                                                61
Delivering MORE Together




Recently Released Wideband ADCs for SDR




TI Information – Selective Disclosure
    ADC12D2000/1800/1600/1000/800/500RF
    RF Sampling ADCs w/ Industry’s Largest Nyquist Zone


 Configurable:                                     RF-Sampling capability replaces entire IF- and
      4.0/3.6/3.2/2.0/1.6/1.0 GSPS interleaved      ZIF-sampling subsystems of mixers, LO
      2.0/1.8/1.6/1/0.8/0.5 GSPS dual ADC           synthesizers, filters, amplifiers, and ADCs
 Excellent performance beyond 2.7 GHz              Industry’s widest Nyquist zone of 2 GHz enables
 Excellent performance beyond 11th Nyquist zone     wideband software-defined radio (SDR) and allows
 Noise floor:                                       combining multiple channels into one
      TBD/-155/-154.6/-154/-152.2/-150.5dBm/Hz     Reduction in board area, cost, and complexity
 IMD3@2.7GHz:                                      Pin-compatible family allows range of resolution
      TBD/-64/-70/-69/-71/-69 dBFS                  and speed-grade end-products
 Power: 4.6/4.4/4.0/3.5/2.5/2.0W
 Autosync function for multi-ADC applications*
 Pin-compatible w/ ADC12D1x00 & ADC10D1x00



   3G/4G basestation receive & DPD
   Microwave backhaul
   RF-Sampling, wideband SDR
   T&M (scopes, data acquisition, analyzers)

                 EVM: ADC12D2000RFRB, ADC12D1800RFRB, ADC12D1600RFRB, ADC12D800RFRB
*Not available on ADC12D2000RF
TI Information – Selective Disclosure                                                        63
                                                                                                           Released!

  ADS4249
  Dual 14-bit 250MSPS ADC
Features                                       Benefits

• Low Power:                                   • 60% lower power than previous generation
                                               • Enables 3G/LTE cellular base stations and repeaters to receive
       • 235mW/channel CMOS Interface
                                               weak signals, reduce dropped-calls and improve data throughput.
       • 280mW/channel LVDS Interface
                                               • Support for 1Vpp full scale provides better system linearity
• 71.1 dBFS SNR and 80 dBc SFDR at 170MHz IF
                                               • Pin-for-pin 65/125/160/200/250MSPS family provides scale-ability
• 6 dB gain in 1 dB steps
                                               for the customer to easily upgrade bandwidths
• 9x9mm, 64-pin QFN package
                                               • Flexible digital interface is compatible with most FPGA/ASICs
• Selectable DDR LVDS or CMOS outputs          • Eliminates previous dual supply requirement of 3.3 and 1.8V,
• 1.8V Analog/Digital supplies                 while providing lower power consumption
                                                                                                     LMK04800

                                                                LMH6521        ADS4249                   CLOCK
Applications                                                                       ADC

• Wireless communication:                                                          ADC

       • Basestation receivers                            IF (Heterodyne) Diversity Receiver
       • Diversity or Quadrature IQ             LMX2581                                           GC5330
                                                TRF3765
       • Wideband Power Amp Linearization                                                             DUC
                                                  LO                    OR
• Software Defined Radios                                                                             DDC
       • Portable receivers                                   Direct Conversion Receiver
• Test and measurement equipment                    Antenna
                                                                               ADS4249
                                                               IQ DEMOD
       • Hand-held analysis
                                                                                   ADC
                                                                                   ADC

    TI Information – Selective Disclosure                                                                   64
LM97600
7.6-bit 5/2.5/1.25-GSPS 1/2/4-ch ADC

 Average output word size: 7.6 bits           Configurable 1/2/4-ch offers flexibility
 Configurable:                                Excellent power efficiency reduces end-unit power
      5/2.5/1.25-GSPS                          consumption
      1/2/4-ch                                Serial outputs reduce output pin count and simplify
 ENOB @ 1 GHz: 6.4 bits                        system board design
 SNR @ 1 GHz: 40.5 dBc                        High sampling rate offers large Nyquist zone for
 SFDR @ 1 GHz: 49 dBc                          frequency-planning flexibility
 8b/10b-encoded serial outputs                Test pattern outputs simplify output interface
 Test patterns                                Sync function enables external interleaving of
 Multi-ADC synchronization capability          multiple LM97600 devices
                                               Vin1+
 Power: 3W                                      Rterm                              8
                                                                                          Selective
                                                                                                        7.6

                                                                            8-bit                                           Lane 1
 292-pin TEBGA                                Vin1-
                                                                S/H
                                                                            ADC
                                                                                            LSB
                                                                                         Truncation
                                                                                                        7.6
                                                                                                                            Lane 2
                                               Vin2-
                                                                                                                            Lane 3
                                                 Rterm                Channel-A
                                                          M                                                                 Lane 4
                                                                                                               8B10B
                                               Vin2+                                                                        Lane 5
                                                          U                                                   Encoder
                                               Vin3+                                                            and         Lane 6
                                                                           Channel-C
                                                          X                                                   Serializer
 Microwave backhaul
                                                 Rterm                                                                      Lane 7

                                              Vin3-                                                                         Lane 8

 T&M (scopes, data acquisition, analyzers)   Vin4-
                                                                             Channel-D
                                                                                                                            Lane 9

 Optical communications                         Rterm
                                                                                                                           Lane 10
                                                                                Channel-B
                                              Vin4+
                                                                               Self-     Control/Status &
                                               CLK+
                                                                               CAL         Other Logic
                                                 Rterm           Clock         Logic
                                                              Management
                                              CLK-
                                                                                         Control      SPI
                                                                                          Pins

 TI Information – Selective Disclosure                                                                                 65
Delivering MORE Together




TI’s Complete Signal Path Portfolio




TI Information – Selective Disclosure
Delivering MORE Together




Clocks for SDR




TI Information – Selective Disclosure
Low-Jitter Highly-Flexible Clocks & Synthesizers
From specialized clock chips to simple clock buffers & distributors

         By unctionPortfolio
         Clocking

                                                                                         PLL            PLL
                                                           PLL
                                                                                               Synthesizers
                                             PLL                             Dist
                                                             Dist                                & PLLs
     PLL PLL
                                             Dist
                   Dist                                   Generation &    Distribution
                                                           Distribution    & Buffers
                                        Jitter Cleaning
    Jitter Cleaning /                   & Distribution
      Generation /
       Distribution



                             Wideband, high-IF/RF-sampling SDR
                                requires lowest noise / jitter


TI Information – Selective Disclosure                                                                         69
Delivering MORE Together




ADC Drivers for SDR




TI Information – Selective Disclosure
    LMH6521
    High Performance Dual DVGA


    • High linearity  48.5 dBm OIP3 @ 200MHz                  Excellent high frequency distortion performance 
    • Accurate gain/phase matching  ±0.04dB /                  Better receiver sensitivity
      ± 0.45deg                                                Accurate ch-to-ch gain/phase matching 
    • 31.5dB gain range with 0.5 dB step size                   Improves image rejection and increases SNR
    • 200Ω Resistive, differential input                        performance; minimal mismatches across wide
                                                                bandwidths
    • Low impedance, differential output
                                                               Drives low impedance filter loads  Improved
    • Parallel gain control; SPI compatible serial bus          system reliability & manufacturability
    • Two wire, pulse mode control
    • Quad-channel version: LMH6522                                           Block Diagram
    • Single 5V supply voltage; 32-pin LLP package
    • -3dB bandwidth of 1200MHz



   Differential ADC driver; Single-ended to diff converter
   Wideband and narrowband IF sampling receivers
   Wideband direct conversion; Digital pre-distortion
   Oscilloscopes, data acquisition
    EVM PART # (LMH6521EVAL)


TI Information – Selective Disclosure                                                                     83
                                                                                                         83
   LMH6882
   2.4 GHz Dual Wideband PDA for Wideband ZIF
            Key Spec                       Performance                         Key Features
FOM (IIP3-NF)                                         6.3 dBm
(200MHz, across all gain settings)
                                                                  • Accurate gain/phase matching
OIP3
(Pout = 0dBm/tone, max gain, 200MHz)
                                                    42 dBmamp     • Supports diff/single-ended inputs
OIP3                                                38 dBmamp
                                                                  • DC offset correction
(Pout = 0dBm/tone, max gain, 400MHz)
                                                                  • DC-coupling from mixer to ADC
HD2
(2Vpp output, 200MHz)
                                                       -65 dBc    • On-chip input termination
Gain range                                 20 dB (6 dB to 26dB)
                                                                  • Interface: SPI / muxed parallel /
                                                                  simultaneous parallel (no clk)
Gain step size                                         0.25 dB
                                                                  • 32-pin LLP
Gain/phase matching                        ±0.04 dB / ±0.45 deg
                                                                  • Single-ch version: LMH6881
0.1 dB gain flatness                                  500 MHz
3-dB Small-Signal BW                                   2.4 GHz
Noise figure                                            9.7 dB
(at max gain)

Total Power                                                1W                                    ADC




                                                                              ½ LMH6882


   TI Information – Selective Disclosure                                                                84
                    Wideband SDR Demo



TI Information – Selective Disclosure   89

				
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