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					Advanced VLSI Design

   Timing Issues


        EE141          1
 Architecture of the Motorola DSP
            56K family
• 24-bit general purpose Digital Signal
  Processors
• It has a dual Harvard architecture
  optimized for MAC operations.
• It features a three stage instruction
  pipeline, which is essentially invisible to
  the programmer
                      EE141                     2
          Harvard architecture
• Harvard architecture refers
  to a memory structure
  wherein the processor is
  connected to two
  independent memory banks
  via two independent sets of
  buses
• The key advantage of the
  Harvard architecture is that
  two memory accesses can
  be made during any one
  instruction cycle   EE141      3
    Major components of the central
          processing module
•   Data Buses
•   Address Buses
•   Data Arithmetic Logic Unit (data ALU)
•   Address Generation Unit (AGU)
•   Program Control Unit (PCU)
•   Memory Expansion (Port A)
•   On-Chip Emulator (OnCE™) circuitry
•                      (PLL) based clock
    Phase-locked LoopEE141                  4
    circuitry
           Synchronization
• Well defined ordering of switching events
  for circuit to operate correctly
• In synchronous system approach---all
  memory elements are simultaneously
  updated using a global clock.
• Register based clocking (robust, reliable) ,
  latch based clocking

                     EE141                       5
               Pipelining
• To accelerate the operation of data path,
  pipelining is used
• Computation is performed in assembly line
  like fashion
• Pipelined network outperforms original
  circuit with respect to speed
• Macro pipeline, micro pipeline
                     EE141                    6
Pipeline PCU— MACRO LEVEL




           EE141            7
        Pipelined
        datapath

        MICRO-LEVEL




EE141           8
            Timing Parameters
                 R1                              R2
       In                        Combinational
               D    Q                            D   Q
                                    Logic

        CLK              tCLK1                       tCLK2

                tc - q                tlogic
              tc - q, cd            tlogic, cd
              tsu, thold



• Assume positive edge triggered system


                                        EE141                9
      Timing Definitions

CLK
                                       t   Register
        tsu   thold                        D     Q

  D       DATA                                 CLK
         STABLE                        t
               tc 2   q

  Q                            DATA
                              STABLE   t




                          EE141                       10
          Timing constraint
• Ideal clock

             Minimum cycle time:
              T > tc-q + tsu + tlogic



            Hold time constraint:
            thold < t(c-q, cd) + t(logic, cd)



                             EE141              11
        Clock Non-idealities
• Clock skew
  – Spatial variation in arrival time of a clock
    transition.
  – It is caused by mismatches in clock path or clock
    load
  – It can be positive or negative depending upon
    routing direction and position of clock source
  – Clock skew does not result in clock period
    variation

                          EE141                         12
     Positive and Negative Skew
      R1                               R2                           R3
In                 Combinational                    Combinational
      D Q                             D Q                           D Q          •••
                      Logic                            Logic

CLK        tCLK1                            tCLK2                        tCLK3

                      delay                             delay
                               (a) Positive skew

      R1                               R2                           R3
In                 Combinational                    Combinational
      D Q                             D Q                           D Q          •••
                      Logic                            Logic

           tCLK1                            tCLK2                        tCLK3

                      delay                             delay        CLK
                              (b) Negative skew


                                        EE141                                          13
                  Positive Skew

                          TCLK + d
                             TCLK
         1                               3
CLK1
             d


  CLK2       2                               4
                 d + th



Launching edge arrives before the receiving edge

                                     EE141         14
Impact of positive clock skew
              R1                              R2
   In                         Combinational
            D    Q                            D   Q
                                 Logic

     CLK              tCLK1                       tCLK2

             tc - q                tlogic
           tc - q, cd            tlogic, cd
           tsu, thold


Minimum cycle time:
T +  = tc-q + tsu + tlogic
Worst case is when receiving edge arrives early (positive )

                                     EE141                     15
              Race condition
• Hold time constraint:


• thold +  < t(c-q, cd) + t(logic, cd)




                        EE141             16
               Negative Skew

                   TCLK - 
                      TCLK
           1                      3
CLK1



CLK2   2                      4
           



Receiving edge arrives before the launching edge

                         EE141                     17
Impact of negative clock skew
              R1                              R2
   In                         Combinational
            D    Q                            D   Q
                                 Logic

     CLK              tCLK1                       tCLK2

             tc - q                tlogic
           tc - q, cd            tlogic, cd
           tsu, thold


Minimum cycle time:
T -  = tc-q + tsu + tlogic
Worst case is when receiving edge arrives early (positive )

                                     EE141                     18
           No Race condition
• Probability of race condition is reduced or
  nil
• thold -  < t(c-q, cd) + t(logic, cd)


• System never fails as new data latched
  on to R1 never gets transferred to R2 as it
  would turn off
                        EE141               19
           Clock Non-idealities
• Clock jitter
   – Temporal variations of the clock period at a
     given point on the chip. i. e Clock period
     reduces or expands on a cycle by cycle basis
   – Absolute jitter (tjitter)---worst case variation of a
     clock edge at a given location with respect to
     an ideal clock.
   – Worst case--- Tclk reduces by 2t jitter
   – Cycle to cycle jitter (T jitter) ---deviation of
                           EE141                         20
     single clock period relative to ideal clock.
  Impact of Jitter---always slows down
                       TC LK                    

                                                  t j itter
CLK        
                                           -tji tte r 



                   REGS               Combinat ional
          In                             Logi c

               C LK                      t log ic
                  tc-q , tc-q,   cd      t log ic, cd
                  ts u, thold
                     tjitter




                                      EE141                     21
         Clock Non-idealities

• Variation of the pulse width
  – Important for level sensitive clocking




                       EE141                 22
            Combined Impact




•Minimum time available (neg skew)

Tclk -δ - 2tjitter ≥ tc-q + tlogic + t su
                  or
Tclk ≥ tc-q + tlogic + t su +δ +2tjitter
                           EE141            23
Hold time constraint (pos skew)




   thold + tjitter +δ - tjitter ≤ tc-q cd + tlogic, cd

  •Minimum time available (pos skew)
  Tclk +δ - 2tjitter ≥ tc-q + tlogic + t su

  Tclk ≥ tc-q + tlogic + t su -δ +2tjitter   EE141       24
         Clock Skew and Jitter
   Clk
             tSK



   Clk         tJS




• Both skew and jitter affect the effective cycle time
• Only skew affects race condition


                         EE141                      25
    Sources of skew and jitter
• Clock signal generation
• Manufacturing device variations
• Interconnect variations
• Environmental variations
• Capacitive coupling
Design clock distribution network carefully

                     EE141                    26
           Latch-Based Design
 L1 latch is                               L2 latch is transparent
transparent                                when clk f = 1
when clk f = 0                f



                  L1                                 L2
                                   Logic
                 Latch                             Latch




  Latch is a ‘soft’ barrier
                                  EE141                              27
Performance Similar to




                         EE141   28
            Slack borrowing
• Enhanced performance due to flexible
  timing, yet no design changes
• Possible for logic block to utilize time that
  is left over from the previous logic block.
• Total logic delay can be more than one
  clock cycle

                      EE141                       29
EE141   30
     Reg based vs. latch based--
             example
• Reg.




• latch


                 EE141             31
Less Tclk




   EE141    32
     Maximum slack possible
• Max time that can be borrowed is 0.5 Tclk
• So max logic cycle delay can be 1.5 Tclk
• But for n stages– overall delay would be
n Tclk




                    EE141                    33
              Drawbacks
• We have to use
• two phase clocking scheme,
• Glitches-power dissipation increases




                    EE141                34
Asynchronous systems--Self timed
           approach
• Syn systems—
• logical ordering of events by clk. It
  provides a time base
• Physical timing constraint- next edge
  comes when all blocks have reached
  steady state
• Problem—CLB has to wait even though it
                      EE141              35
  may finish earlier. Clock distribution
      Asynch. design—meeting
            constraints
• Adv—next block can start computation as
  soon as previous block has finished.
• Problem– when to latch the output ? When
  output is a correct value?
• Remedy—system has to meet timing
  constraints

                   EE141                    36
             Local signals
• Logical ordering and physical timing --—
• START, DONE, -- physical timing


• REQUEST , ACKNOWLEDGE - Logical
  ordering



                    EE141                    37
                    Self timed system
• System generate its own timing signal
        Req                       Req                       Req                        Req

        Ack          HS           Ack          HS           Ack          HS            ACK

                   Start        Done         Start        Done         Start        Done




              R1           F1           R2           F2           R3           F3          Out
   In

                           tpF1                      tpF2                      tpF3

                                              EE141                                              38
  Self timed system --Hand shake
              protocol
• Hand shaking- synchronize by mutual
  agreement
• adv.--timing signals generated locally—
  less prop. Delay, high speed, no glock
  routing
• Disadv.– hand shaking circuit design

                    EE141                   39
Implementation of HS protocol-
          2 phase




             EE141               40
4 phase protocol




      EE141        41
          Dual rail protocol
• I bit information coded using two wires
• Request is merged with data wires




                     EE141                  42
Bundled data protocol




         EE141          43
Event Logic – The Muller-C Element
                                                       A       B      Fn+1
           A
                                                       0       0     0
                       C         F                     0       1     Fn
           B                                           1       0     Fn
                                                       1       1     1

                 (a) Schematic                             (b) Truth table
                                                                             VDD
                               VDD        VDD

                           A             B
 A
               S   Q
                       F B
 B                                                         F
               R                                               A                    F
                           B
     (a) Logic
                           A             B
                                                               B

                               (b) Majority Function


                                        EE141                         (c) Dynamic       44
4-Phase bundled data Protocol--
            FIFO




              EE141               45
2-Phase bundled data Protocol--
            FIFO




              EE141               46
EE141   47
4-Phase dual rail Protocol--FIFO




              EE141                48
        2-Phase dual rail Protocol--FIFO

         Ack


       Done
       / Req   start


data




                       EE141               49
Ack


Done
/ Req   start




data




                EE141   50
EE141   51
EE141   52
EE141   53
Completion Signal Generation
         no glitches




    Using Redundant Signal Encoding



                 EE141                54
Completion Signal in DCVSL
             VDD             VDD


                     Start                  B0
                                                 Done
                                            B1


 B0                                    B1

      In1
      In 1
      In 2   PDN             PDN
      In 2


             Start




                               EE141                    55
Self-Timed Adder--example
                              VDD                                   VDD
Start
              P0        P1        P2        P3              Start          Done
         C0        C1        C2        C3        C4   C4
                                                            C4            C4
   C0         G0        G1        G2        G3              C3            C3

Start                                                       C2            C2

                                                            C1            C1
                             VDD
                                                            Start
Start
              P0        P1        P2        P3
        C0         C1        C2        C3        C4   C4   (b) Completion signal
  C0
              K0        K1        K2        K3

Start


   (a) Differential carry generation


                                            EE141                                  56
Bundled data protocol




         EE141          57
Memory element design




         EE141          58
PERFORMANCE PARAMETERS

• CLOCK LOAD
• NO OF TRANSISTORS
• CLOCKING SCHEME




               EE141     59
          Latch versus Register
   Latch                         • Register
    stores data when
    clock is low/ HIGH                 stores data when
                                       clock rises
                 D Q                        D Q

                 Clk                         Clk


    Clk                          Clk

    D                            D

    Q                            Q
                         EE141                            60
      Storage Mechanisms

    Static                   Dynamic (charge-based)

                                CLK
     CLK


                        D                        Q
                 Q

           CLK
                                CLK
D



     CLK



                     EE141                            61
   Static-----Mux-Based Latch-1
      Q = CLK’ . Q +CLK . D
                               CLK
CLK LOAD-4
                                                Q
2 PHASE CLOCKING
                                     CLK
10-TRANSISTORS
                   D



                               CLK
                       EE141               62
        Mux-Based Latch(2)-
               LESS CLK LOAD ,

CLK LOAD-2, 2 PHASE CLOCKING, 6-TRANSISTORS


               CLK


        D       T1           I1

                                 I2
               CLK

                     EE141                    63
        Mux-Based Latch(3)-
      LESS CLK LOAD , Vt   DEGRADATION
CLK
                      QM
                              CLK

                      QM

                              CLK



                                Non-overlapping clocks
          CLK


      NMOS only



                      EE141                        64
          Master-Slave (Edge-
          Triggered) Register




Two opposite latches trigger on edge
Also called master-slave latch pair

                           EE141       65
           Master-Slave Register

 Multiplexer-based latch pair




           I2      T2           I3           I5   T4   I6   Q


                                        QM
      D    I1      T1                        I4   T3


CLK




                                     EE141                  66
         TIMING METRICS
• T set up = I1+T1+I3+I2
• T CLK-Q = T3+ I6
• T HOLD = ~0
• EXACT VALUES CAN BE OBTAINED
  THROUGH SIMULATION



                     EE141       67
               Reduced Clock Load
              Master-Slave Register—
              SIZING IMPORTANT-REVERSE CONDUCTION



        CLK                          CLK


D        T1           I1             T2      I3      Q

                       I2                     I4
        CLK                          CLK



    I2 MUST BE WEAK
    WHEN SLAVE IS ON----REVERSE CONDUCTION
                             EE141                  68
         TIMING METRICS
• T set up = T1+I1
• T CLK-Q = T2+ I3
• T HOLD = ~0 (OR T1)
• EXACT VALUES CAN BE OBTAINED
  THROUGH SIMULATION



                     EE141       69
    Avoiding Clock Overlap
    CLK                 X               CLK
                                                        Q
          A
D
                            B




              CLK                                 CLK
                      (a) Schematic diagram


              CLK



              CLK
                    (b) Overlapping clock pairs


                                EE141                       70
Non overlapping phases




          EE141          71
         TIMING METRICS
• T set up = T1+I1
• T CLK-Q = T2+ I3
• T HOLD = ~0 (OR T1)
• EXACT VALUES CAN BE OBTAINED
  THROUGH SIMULATION



                     EE141       72
     Overpowering the Feedback Loop
                    ─
          Cross-Coupled Pairs
    NOR-based set-reset


                                                    S   R   Q    Q
S
                  Q
                          S     Q                   0   0   Q    Q
                                                    1   0   1    0
                          R     Q
                                                    0   1   0    1
                  Q
R                                                   1   1   0    0

                                      Forbidden State

                              EE141                             73
         Cross-Coupled NAND
                                         Added clock
Cross-coupled NANDs                            VDD


  S                                      M2            M4
                     Q
                                                            Q
                                     Q


                     Q    CLK      M6                       M8   CLK
  R                                      M1            M3

                             S     M5                       M7   R



 This is not used in datapaths any more,
 but is a basic building memory cell
                                 EE141                                 74
Dynamic registers




       EE141        75
             TIMING METRICS
• T set up = T1
• T CLK-Q = I1+T2+ I2
• T HOLD = ~0 (OR T1)
•   EXACT VALUES CAN BE OBTAINED THROUGH SIMULATION

• IN OVERLAP--



                            EE141                     76
OVELAPS




  EE141   77
 Other Latches/Registers:
         C 2MOS
                  VDD                         VDD


                  M2                          M6


          CLK     M4                   CLK    M8
                           X
    D                                                    Q
                                CL1                    CL2
          CLK     M3                   CLK    M7


                  M1                          M5




            Master Stage                 Slave Stage

“Keepers” can be added to make circuit pseudo-static
                               EE141                         78
        Insensitive to Clock-Overlap
         VDD                 VDD               VDD                 VDD

         M2                  M6                M2                  M6


    0    M4           0      M8
               X                                     X
D                                  Q   D                                  Q
                                           1   M3           1      M7


         M1                  M5                M1                  M5


         (a) (0-0) overlap                     (b) (1-1) overlap



                                   EE141                                 79
Dual edge registers




        EE141         80
                Single phase clock
             Latches/Registers: TSPC
             VDD         VDD                       VDD         VDD




                               Out

In     CLK         CLK               In      CLK         CLK

                                                                     Out




            Positive latch            Negative latch
     (transparent when CLK= 1) (transparent when CLK= 0)
                                     EE141                                 81
              Including Logic in TSPC
               VDD          VDD                      VDD                   VDD

                                         In1                   In2
               PUN
                               Q                                                 Q

In      CLK           CLK                      CLK                   CLK




               PDN                         In1



                                           In2



     Example: logic inside the latch
                                                           AND latch

                                       EE141                                         82
Reduced complexity




        EE141        83
      TSPC Register

          VDD          VDD              VDD


                CLK                           Q
          M3          M6                M9
                              Y
                                                  Q
D   CLK           X               CLK
          M2          M5                M8



                CLK
          M1          M4                M7




                      EE141                           84
        Pulse-Triggered Latches
        An Alternative Approach
Ways to design an edge-triggered sequential cell:

  Master-Slave                 Pulse-Triggered
    Latches                      Latch
           L1    L2                          L
 Data                          Data
         D Q     D Q                       D Q

          Clk    Clk           Clk         Clk
 Clk


                       EE141                     85
Pulsed register-avoid race,
single latch
             VDD             VDD


             M3              M6                           VDD
                                         CLK
                                   Q
 D   CLKG             CLKG                                MP                      CLKG
             M2              M5
                                                                X


                                                          MN
             M1              M4



             (a) register                                 (b) glitch generation



            CLK

            CLKG

                                       (c) glitch clock
                                          EE141                                          86
      Pulsed Latches

CLK          P1              P3
                    x             Q

                             M6
             M3

 D                      P2   M5
             M2

                             M4
             M1     CLKD




            EE141                     87
Sense amplifier based register




             EE141               88

				
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