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									     Blame Passing for Analysis and
             Optimisation


                   Charlie Brej
                   APT Group
             University of Manchester

03/11/2012            Async Forum       1
             Overview
Introduction
Synchronous methods
Blame passing
Optimisations
Results




03/11/2012      Group Talk   2
        Why we need optimisation
High level entry languages
     RTL
             Gates
               Transistors
                  Silicon

Large designs
     More important things to worry about
     Optimal designs often difficult to read
     Difficult to determine inefficiencies

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             Critical path analysis

              1

                      3
                  2         4
                                       5
              1
                      2         3




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             Retiming




03/11/2012     Group Talk   5
 Why we don’t use the Critical Path
Assumes isochronic arrival of all inputs in each
 stage
     Or predictable sequencing and timing of arrival of
      inputs (deterministic)
No cyclic circuits
     No C-elements
     Only looks at logic and not latches
     No method of determining the interaction between
      different computation cycles
Determines and improves the worst (not
 average / “mode”) case performance

03/11/2012                 Group Talk                      6
                Slowest Path
Designed for asynchronous circuits
     Allows cyclic circuits
     Allows non-deterministic behavior
     Uses a real simulation
     Gathers average case data (not worst case)
Sort of like critical path of a full benchmark
     Start point is the release of the reset
     End point is the benchmark completion signal

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                     Blame Game
              2nd
             Place

                                     Output


              1st
             Place


                                     Benchmark
                                      complete




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             Blame Game




03/11/2012      Group Talk   9
               Pass the blame
Blame passing forms a path from
 completion back to reset release
How to extract path
     Static timing analysis (cyclic paths)
     Simulation dump (lots of data)
Use a custom simulator
Small overhead (~30%)
     Only remember the slowest path transitions

03/11/2012               Group Talk                10
                         Decrementer
while (1) {
         if (Reg != 0)    Reg = Reg – 1;
         else             Reg = Const;
}




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             Graphical representation




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             Apply Optimisations
Find known paths through elements
     Paths with positive effect
     Paths with negative effect
Apply optimisation
Simulate again to determine the effect




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             Optimisation Rules




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             Optimisation Rules




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             Optimisation Rules




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       Optimisation Results (Dec)




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      Optimisation Results (GCD)




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     Optimisation Results (MIPS)




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                  Conclusions
Novel analysis and optimisation technique
Applicable to many asynchronous systems
     Not just circuits
Automatic reanalysis system
Future work:
     Read SDF files
     Extension to other systems (Balsa etc)
     Connection to a full design system (Biscotti)

03/11/2012                Group Talk                  20

								
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