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Fundamentals of Continuous-Time ΣΔ Modulators

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					 TAMU-ECE                                         Barcelona, 2012




                    Fundamentals of
                    Continuous-Time
                     ΣΔ Modulators
                      Jose Silva-Martinez
                     (Amesp02.tamu.edu/~jsilva)

                         Department of ECE
                        Texas A&M University


J. Silva-Martinez                                         -1-
 TAMU-ECE                                                Barcelona, 2012




                                       Outline
         Ø  Fundamentals of Sigma-Delta Modulators
                Ø  Noise and Signal Transfer Function
                Ø  Error Function
                Ø  Blockers tolerance
         Ø  System Limitations
              Ø  Linear Range
              Ø  Stability
              Ø  Clock Jitter
         Ø  Building blocks
              Ø  Filter issues
              Ø  Quantizer
              Ø  DAC issues
              Ø  Clock Generation
         Ø  Conclusions


J. Silva-Martinez                                                -2-
 TAMU-ECE                              Barcelona, 2012



                    State of the art


  100mW @10MHz

  10mW @10MHz

                            LTE




J. Silva-Martinez                              -3-
 TAMU-ECE                                                            Barcelona, 2012



                         Nyquist-Rate and
                    Oversampled A/D Conversion
         Ø  According to the ratio of sample frequency and Nyquist
              sample rate, A/D converters can be classified as,
                Ø Nyquist-rate A/D converter
                Ø Oversampled A/D converter
         Ø  For a Nyquist-rate A/D converter, the sample frequency is
              at, or slightly higher than, Nyquist sample rate of the input
              signal.
         Ø  For an oversampled A/D converter, the sample frequency
              (FS) is much higher than the Nyquist sample rate (Fnyquist).
              The ratio of M=Fs/Fnyquist is the oversample ratio (OSR).



J. Silva-Martinez                                                            -4-
 TAMU-ECE                                                              Barcelona, 2012




  Nyquist-Rate and Oversampled A/D Conversion
         §  One direct benefit of oversampled ADC is that the
             quantization noise is M (M is the oversample ratio) times
             less than its Nyquist counterpart.
         §  Every time we double the sample frequency, the
             effective resolution increases with 3 dB (0.5 bit).
                             Δ2 Fb
          Frequency band       ×       Snq(f) Quantization noise PSD
             of interest     12 Fs
                                                          Δ2 1
                                                            ×
                                                          12 Fs

                                                                  Freq
                    -Fs/2     -Fb/2         Fb/2       Fs/2

               The quantization noise outside of the frequency of
               interest should be filtered out by post digital filtering.

J. Silva-Martinez                                                              -5-
 TAMU-ECE                                                                  Barcelona, 2012




  Nyquist-Rate and Oversampled A/D Conversion

             Frequency band    Δ2 Fb
                                 ×        Sq(f)     Quantization noise PSD
                of interest    12 Fs                           Δ2 1
                                                                 ×
                                                               12 Fs

                                                                       Freq
                    -Fs/2        -Fb/2            Fb/2      Fs/2

      Ø  Reducing signal bandwidth decrease the integrated in-band
          noise level by 3 dB
      Ø  Increasing the oversampling ratio Fs/2Fb by factor of 4
          increases the resolution by 6dB or equivalently 1 dB.
      Ø  Changing the sampling frequency by a factor of 100
          increases the SQNR by only 20 dB.
             Ø  Very expensive: too much effort for additional 3.3 bits
             Ø  Can we do better than this?
J. Silva-Martinez                                                                  -6-
 TAMU-ECE                                        Barcelona, 2012



                    Conventional (Nyquist) ADC
                          Data
                          Out

  Vin               A/D




                             SQNR=6.02*n+1.76

J. Silva-Martinez                                        -7-
 TAMU-ECE                                                                                     Barcelona, 2012



                    Basic concept in ΣΔ Modulators
                                             Data
                                             Out
   Vin
          S         H(s)              A/D
                                 1
                            Ts =
                                 Fs
                      DAC
                                                                                                 Dout
                                                          Quantization                   NTF =
                                                                                                 Qn
                                                            Noise                 OBG
                                      H(s)          A/D
                                                                           Dout
                                                                                                              f
               Vin                                                                       f0
                                                                                                 Dout
                                                                                         STF =
                     VDAC                                                                        Vin
                                                                                  0 dB

                                             Feedback
                                               DAC                                                        f
                                                                                         f0

                               H( s )                                        1
               STF =                                      NTF =
                            1+ H ( s )                                   1+ H ( s )

J. Silva-Martinez                                                                                       -8-
 TAMU-ECE                                            Barcelona, 2012

      Identify the noise and signal and use
      Feedback to shape the noise!
                    Original ADC
                      + noise




    The assumption is that the DAC can do much better
    than the original ADC; is this realistic? Free lunch?
J. Silva-Martinez                                            -9-
 TAMU-ECE                                                                                                     Barcelona, 2012

               Oversampled A/D Conversion
               (Double check Mason’s rule)




                                                      ωT                         Check the input-output trajectories
                                                 −j        ⎛ + j ω2T   −j
                                                                           ωT
                                                                                ⎞ Original E(z) is shaped by NTF
H e (z ) = 1 − Z −1 = 1 − e − jωT = e                 2    ⎜ e
                                                           ⎜         −e 2      ⎟
                                                                                ⎟
                                                           ⎝                   ⎠
                    ωT                                                                           Spot SQNR
               −j        ⎛        ⎛ ωT ⎞ ⎞                       Original E(z) is
H e (z ) = e        2
                         ⎜ 2 j sin⎜
                         ⎜              ⎟ ⎟                       amplified here!
                         ⎝        ⎝  2 ⎠ ⎟
                                            ⎠                                                                     2
                                                                                                   X (z )Z   −1
                                                                                         SQNR =
                                                                                                  E (z )H e (z )
                ⎛ ωT ⎞                                                                                                          2
H e (z ) = 2 sin⎜    ⎟
                ⎝  2 ⎠                                                                                 2
                                                                                                X (z )         1
                                                                                         SQNR =        *
                                                                                                E (z )         ⎛ ωT ⎞
                                                                                                         2 sin ⎜    ⎟
                                                                                                                       ⎝ 2 ⎠
J. Silva-Martinez                                                                                                        - 10 -
TAMU-ECE                                                                                                                 Barcelona, 2012


                 Oversampled A/D Conversion

                                                                                                         2⎛ OSR 3 ⎞
                                                                                                 (   N
                                                                                                         )
                                                                                    SQNR ≅ 1.5* 2 − 1 * ⎜ 3*
                                                                                                          ⎜          ⎟
                                                                                                                   2 ⎟
                                                                                                                 π ⎠
                                                                                                          ⎝
                                                                                    SQNR ≅ 1.76 + 6.02 * N − 5.2 + 30 * log (OSR ) dB

                                   2

                                                                                         Signal to Quantization
                                                                            2
                  X (z )Z −1                                       X (z )
 SQNR =    fb
                                                    =          fb
                                       2                                        2
           ∫ (E (z )H (z ))                df           E (z ) ∫ (H e (z )) df
                                                                                         Noise Ratio (SQNR)
                          e
           0                                                   0




        X (z )
                      2
                                                    1                                    Ø N=number of bits
 SQNR =        *                                           2
        E (z )            fb
                            ⎛      ⎛ ωT ⎞ ⎞
                          ∫ ⎜ 2 sin⎜ 2 ⎟ ⎟ df                                        Ø OSR=fs/2fb
                          0 ⎝      ⎝    ⎠ ⎠
 If fb << fs , then                                                                      Ø SQNR improves by 30dB when
                                                2
                                                                                            OSR increases by 10
                                                                      3
           1    ⎛ 2 N − 1 ⎞          ⎛ f ⎞
           2    ⎜ 2 ⎟(ΔVq )
                ⎜         ⎟      6 * ⎜ S ⎟
                                       ⎜ 2 f ⎟
                ⎝         ⎠          ⎝    b ⎠
 SQNR ≅
                   ΔVq
                        2
                              2
                                 *      2
                                     π * fS                                              Ø Or 9dB SQNR improvement
                          *
                     12       fS                                                            when doubling OSR
                                                           3
                     2  ⎛    OSR ⎞
                  (
  SQNR ≅ 1.5* 2 N − 1 * ⎜ 3*
                        ⎜     )   ⎟
                               π 2 ⎟
J. Silva-Martinez       ⎝         ⎠                                                                                            - 11 -
 TAMU-ECE                                                          Barcelona, 2012


                    Oversampled A/D Conversion

      Typical spectrum for a 2nd order system




   Understanding Delta-Sigma Data Converters, Schreier and Temes


J. Silva-Martinez                                                          - 12 -
 TAMU-ECE                                                                                                                   Barcelona, 2012


                     Linearized Model: 2nd order
                    Multiple Feedback Modulator



  Schreier and Temes


                    V (z )                     a 1a 2                                         a 1a 2
                             =                                          =
                    U (z )       ( z − 1) 2 + ( z − 1) ba 2 + a 1 a 2       z 2 − ( 2 − ba 2 ) z + (1+ a 1 a 2 − ba 2   )
     STF                                                                                                                         X
                    V (z )                       a 1a 2                                    a 1a 2
                             =                                               =
                    U (z )        2
                                                                (
                                 z − ( 2 r cos (ω 0 T ) ) z + 1− r      2
                                                                            ) (z − re ω )(z − re
                                                                                       j 0T            − jω 0 T
                                                                                                                  )
     NTF                     V (z )                     ( z − 1) 2                                                                X
                    NTF =              =
                     ( z − 1) 2 + ( z − 1) ba 2 z + a 1 a 2
                             E (z )
  Under the conditions a1a2=1 and a2b=2, then
                                                    2
       V (z ) = z −2U (z ) + (1− z −1 ) E (z )                                                This is the real signal at the
                                                                        2                     filter’s input: THINK ABOUT IT!
                                 U
       U (z ) −V (z ) = (1− z −2 ) (z ) − (1− z −1 ) E (z )
J. Silva-Martinez                                                                                                                    - 13 -
 TAMU-ECE                                                                                   Barcelona, 2012

                     Linearized Model: 2nd order
                    Multiple Feedback Modulator



  Schreier and Temes



   STF and NTF are definitely not enough to design a robust system!
                                               2
              V (z ) = z −2U (z ) + (1 − z −1 ) E (z )
   At the input of the first amplifier we have:
                                                             2          Small for inband signals but
                                        U
              U (z ) −V (z ) = { − z −2 } (z ) − (1 − z −1 ) E (z )
                               1                                        what about the blockers?
   At the output of the first integrator we have (saturation?)
               V
               { (z ) − U (z )}z −1a1
                                        = { + z −1}z −1a1U (z ) − (1 − z −1 )z −1a1E (z )
                                          1
                      1 − z −1
      If a1>0.5, hence the in-band output of the 1st integrator is > than the input !
J. Silva-Martinez                                                                                   - 14 -
 TAMU-ECE                                                                                                                     Barcelona, 2012



      2nd order Multiple Feedback Modulator


                                                                                                                     Schreier and Temes




                                                            2

       STF =
               V (z )
                        =
                                               (
                                         b 3 1− Z −1        )             (           )
                                                                    + b 2 1− Z −1 + b 1
                                −1 2                                  2
               U (z )       (1− Z )                     (
                                        + a 3 Z −1 1− Z −1    ) +a            2   Z (1− Z )+ a
                                                                                   −1        −1
                                                                                                      1Z
                                                                                                           −1


                                     V (z )
                            STF =             = b3              −1 2
                                                       (1− Z ) + b            2   (1− Z )+ b
                                                                                        −1
                                                                                                  1
                                                                                                                    a1 = a2=1
                                     U (z )
                                     V (z )                     2
                                                                                                                    a3 = 0
                             NTF =                 (
                                              = 1− Z −1         )
                                     E (z )

                                                        {
  Amplifier input Ve (z ) = − b2 (1 − Z −1 ) − b3 (1 − Z −1 )2 U (z ) − (1 − Z −1 )2 E (z )                     }
J. Silva-Martinez                                                                                                                     - 15 -
 TAMU-ECE                                                                       Barcelona, 2012



Generic model for the Feed-forward Modulator




 V = {STF }U + {NTF }E

     ⎧ L ⎫
     ⎪      ⎪     ⎧ 1 ⎫
                    ⎪      ⎪                 Be sure that |1+L|>0 for all
 V = ⎨      ⎬ U + ⎨      ⎬ E
     ⎪ 1+ L ⎪     ⎪ 1+ L ⎪                 frequencies; e.g. phase at the unity
     ⎩      ⎭     ⎩      ⎭
                                               frequency
                 ⎧ 1 ⎫
                 ⎪       ⎪     ⎧ 1 ⎫
                                 ⎪      ⎪     U − E Very good for inband signals, but
 V e = U − V = ⎨         ⎬ U − ⎨      ⎬ E =
                 ⎪ 1+ L ⎪
                 ⎩       ⎭     ⎪ 1+ L ⎪
                                 ⎩      ⎭     1+ L some issues for out of band signals
                                                      specially if NTF>1 at high frequencies
             ⎧ L ⎫
             ⎪       ⎪
 Y = V e L = ⎨       ⎬ {U − E }                     Little chance of overloading at the
             ⎪ 1+ L ⎪
             ⎩       ⎭                              quantizer input

J. Silva-Martinez                                                                       - 16 -
 TAMU-ECE                                                                         Barcelona, 2012



Generic model for the Feed-forward Modulator

                                                      Schreier and Temes




                    1 ⎫
   V = U + ⎧
           ⎨           ⎬E           Very good STF but it is not very relevant in
                ⎩1 + L ⎭            practice

                ⎧ 1 ⎫               Excellent for both in-band and out-of-band
   Ve = U −V = −⎨      ⎬E           blockers; minor issues if NTF>1 at high
                ⎩1 + L ⎭
                                      frequencies

                              ⎧ L ⎫ Little chance of overloading at the quantizer input
   Y = U +Ve L = U − ⎨               ⎬E
                              ⎩1 + L ⎭
                                          But.. What about aliasing of HF signals? After Y we
J. Silva-Martinez                         have the quantizer (S/H)!                     - 17 -
 TAMU-ECE                                                                      Barcelona, 2012

                    Generic model for a Hybrid
                            Modulator




                                                  (HIGH) Risk of excessive signal at the
     ⎧ L k ⎫    ⎧ 1 ⎫
 V = ⎨ 0 ⎬U + ⎨          ⎬E                   internal nodes
     ⎩1 + L1k ⎭ ⎩1 + L1k ⎭
                                                  You have to analyze case by case; hard
  Error Signal =V − E                             to make general conclusions

                      ⎧ L k ⎫    ⎧ L k ⎫      Once you define Lo and L1 and the
                    = ⎨ 0 ⎬U − ⎨ 1 ⎬E
                      ⎩1 + L1k ⎭ ⎩1 + L1k ⎭   topology you must analyze how L1*V
                                                  and Lo*U affect the signal swing at
                                                  every internal node

                                                  Inband SNR is a strong function of Lok
J. Silva-Martinez                                                                      - 18 -
 TAMU-ECE                                                      Barcelona, 2012

               High-order Feedforward
            Modulator based on Integrators




        This architecture is very popular in CT modulators

        No problem with non-touching loops nor with trajectories
        non-touching loops

        A major issue is the frequency response of the adder
J. Silva-Martinez                                                      - 19 -
 TAMU-ECE                                                                         Barcelona, 2012

                    Generic model for a Hybrid
                            Modulator




                                              (HIGH) Risk of excessive signal at the
    ⎧ L k ⎫          ⎧ 1 ⎫                internal nodes
    ⎪    0     ⎪     ⎪          ⎪
V = ⎨          ⎬ U + ⎨          ⎬ E
    ⎪ 1+ L 1 k ⎪     ⎪ 1+ L 1 k ⎪
    ⎩          ⎭     ⎩          ⎭         You have to analyze case by case; hard
                      ⎧ L k ⎫               to make general conclusions
                                         ⎧ L k ⎫
                      ⎪ 0 ⎪            ⎪    1     ⎪
ErrorSignal = V − E = ⎨          ⎬ U − ⎨          ⎬ E
                      ⎪ 1+ L 1 k ⎪
                      ⎩          ⎭     ⎪ 1+ L 1 k ⎪ Once you define Lo and L1 and the
                                         ⎩          ⎭
                                              topology, you must analyze how L1*V
                                              and Lo*U affects the signal swing in
                                              every node

                                              Inband SNR is a strong function of Lok
J. Silva-Martinez                                                                           - 20 -
 TAMU-ECE                                                                 Barcelona, 2012


                    Fundamentals on MASH
                        architectures
                              Digital
                                               Quite relevant topology:
                                               Notice that the auxiliary
                       DAC                     ADC processes the
                                               quantization error E1
                                               What about E2?
Schreier-Temes

                                               Any other option?
                        V            V
         V (z ) = H 1(z ) 1 − H 2 (z ) 2
         V1(z ) = STF1(z )U + NTF1(z )E 1
         V 2 (z ) = STF 2 (z )E 1 + NTF2 (z )E 2
         Then
         V (z ) = H 1{STF1* U + NTF1* E 1} − H 2 {STF 2 * E 1 + NTF2 * E 2 }
                                U
         V (z ) = {H 1* STF1} + {H 1* NTF1 − H 2 * STF 2 }E 1 − {H 2 * NTF2 }E 2
J. Silva-Martinez                                                                  - 21 -
 TAMU-ECE                                                                         Barcelona, 2012

                          Fundamentals on MASH
                              architectures

                                                               Analog Intensive
                              DAC                              MASH topology


Schreier-Temes



 If H 1* NTF1 − H 2 * STF 2 = 0
 Then
                     U
 V (z ) = {H 1* STF1} − {H 2 * NTF2 }E 2

                    2                2                     2
        ⎧ E 1 ⎫       ⎧STF 2 ⎫       ⎧ STF1* U ⎫
 SQNR = ⎨ ⎬           ⎨      ⎬       ⎨           ⎬
        ⎩E 2 ⎭        ⎩ NTF2 ⎭       ⎩ NTF1* E 1 ⎭
J. Silva-Martinez                                                                         - 22 -
 TAMU-ECE                                               Barcelona, 2012




                Sigma-Delta Modulators
                    Design Issues

                             Jose Silva-Martinez
                            Texas A&M University
                    Electrical and computer Engineering

                           (Amesp02.tamu.edu/~jsilva)

                                    Part 1.2
J. Silva-Martinez                                               - 23 -
 TAMU-ECE                                                                                      Barcelona, 2012



           Linearized Discrete-Time Model
                                                   E(z)

       X(z)                         H(z)                       Y(z)                   z −1
                                                                              H(z) =
                                                                                     1− z −1



                                                                      Signal Transfer Function :
                                                                              Y(z )
            Y (z ) = H(z )⋅ [X(z ) − Y (z )] + E(z )                  STF =         = z −1 ← Delay
                                                                              X(z )
                          H(z )                1
            ⇒ Y (z ) =            ⋅ X(z ) +          ⋅ E(z )
                         1+ H(z )           1+ H(z )                  Noise Transfer Function :
                                                                              Y (z )
                                      (       )
            ⇒ Y (z ) = z −1 ⋅ X(z ) + 1− z −1 ⋅ E(z )                 NTF =
                                                                              E(z )
                                                                                     = 1− z −1 ← HP



  Caveat: E(z) may be correlated with X(z) – not “white”.

J. Silva-Martinez                                                                                      - 24 -
 TAMU-ECE                                                                                                        Barcelona, 2012




                        1st-Order Noise Shaping
                                                          2
                                      ⎡    ⎛       f ⎞⎤                fm
                                    ∝ ⎢2sin⎜ π       ⎟⎥        2            Δ2              1            2
                                      ⎣    ⎝      fs ⎠⎦       N =
                                                                   e       ∫ 12         ⋅               ⋅ NTF df
        PSD                                                                0
                                                                                            fs 2
                                                                                                        fm               2
                                                                                2
                                                                           Δ                1       ⎡     ⎛ f       ⎞⎤
                                                                       =            ⋅               ⋅  2sin⎜ π       ⎟⎥ df
                                                                                                2 ∫ ⎣
                                                                                                    ⎢     ⎜ f       ⎟
                    €                                                      12 f s                 0        ⎝ s       ⎠⎦
                                                                                                                 2
                                                              f            Δ2               1        ⎡
                                                                                                        fm
                                                                                                          f ⎤
                        fm                   fs/2                      ≈            ⋅            ⋅ ∫ ⎢2π ⎥ df
                                                                           12 f s               2 0 ⎣   f s ⎦
        In - band quantizati on noise :                                         2
                                                                                                        3
                            2            2                                 Δ ⎛ 2f                  ⎞ π 2
                        Δ            π                                 =   ⋅ ⎜ m                   ⎟ ⋅
             N2
              e     ≈           ⋅                                        12 ⎜ f s
                                                                             ⎝
                                                                                                    ⎟
                                                                                                    ⎠   3
                        12 3OSR 3

       Doubling OSR increases SQNR by 9 dB (1.5 bit/oct).

J. Silva-Martinez                                                                                                        - 25 -
 TAMU-ECE                                                                 Barcelona, 2012




                     2nd-Order ΣΔ Modulator
                           INT1                   INT2

      Vi                      z-1                   z-1         A/D           Do


                                            2

                                                     D/A

               Signal Transfer Function :
                                                In - band quantization noise :
                       STF = z −2
                Noise Transfer Function :                  2  Δ2 π 4
                                                          N ≈
                                                           e    ⋅
                                                              12 5M5
                                    2
                     NTF = ( z−1)
                           1−

 Doubling OSR (M) increases SQNR by 15 dB (2.5 bit/oct).
  €
J. Silva-Martinez                       €                                         - 26 -
 TAMU-ECE                                                          Barcelona, 2012



   Generalization (Lth-Order Noise Shaping)
      Modulator transfer function :
                                         L
     Y (z) = z−L X(z) + ( z−1) E(z)
                        1−

     In - band quantization noise :

              Δ2                π 2L
     N2 ≈
      e             ⋅
              12        ( 2L + 1)⋅ OSR 2L+1

       ⎛ 3 ⎞ N            2   ⎛ ( 2L + 1)⋅ OSR 2L +1   ⎞
       ⎜ ⎟
                (
SQNR = ⎜ ⎟ 2 − 1         )    ⎜
                                ⎜
                                                          ⎟
                                                          ⎟
       ⎝ 2 ⎠                  ⎝         π 2L           ⎠

  §  Doubling OSR (M) increases SQNR by (6L+3) dB, or (L+0.5) bit.
  §  Potential instability for 3rd- and higher-order single-loop ΣΔ
       modulators.



J. Silva-Martinez                                                          - 27 -
 TAMU-ECE                                                                                  Barcelona, 2012



 Equivalence of Continuous-Time & Discrete-Time ΣΔ

                    Discrete time                                Continuous time

                           x(n)                                               x(t) x(n)
  Vin                                                     Vin
         S         H(z)                                        S     H(s)
                                  1                                                   1
                           Ts =                                                Ts =
                                  Fs                                                  Fs
                     DAC                                                DAC
                                       x(n) = x(t ) |t = nTs
 §  The key feature of the ΣΔ1{H ( z )} = L−1is D ( s )noise |tshaping (NTF)
                            Z − modulator {Rthe H ( s )} = nTs
                            (n) = [RD t continuous-time and discrete-time
 §  To achieve equivalencehbetween (a) * h(t )]|t = nTs
                            Gain should response of DAC
      implementations, LoopR (t ) → Impulsehave the same properties
                            D
 §  How can we realize the same NTF using continuous-time and
      discrete-time loop filters ?
        Ø  The NTF is mainly determined by the transient response of the
            loop filter and the feedback DAC !

J. Silva-Martinez                                                                                  - 28 -
 TAMU-ECE                                              Barcelona, 2012



  Types of Feedback DAC with Rectangular
                  Pulses




             NRZ: Easy to design
             RZD: More tolerant to excess loop delay
J. Silva-Martinez                                              - 29 -
 TAMU-ECE                                                              Barcelona, 2012



      Impulse Invariant Transformation




      Transformations can be easily applied by decomposing the original
      DT (Z-domain) loop filter into partial fractions and use S-domain
      equivalences for the Z-domain poles to get the CT loop filter.


J. Silva-Martinez                                                              - 30 -
 TAMU-ECE                                                    Barcelona, 2012



  “Inherent Anti-aliasing” for narrow-band
                applications




                                     Check Hc(s)
                                     transfer
                                     function!

    Hc(s) has a low-frequency gain over 40 dB, with a -3dB
    frequency equal to ADC bandwidth and unity gain frequency
    between 5-10 times higher
J. Silva-Martinez                                                    - 31 -
 TAMU-ECE                                                                                       Barcelona, 2012

               Oversampled A/D Conversion:
               Feedforward architecture
    Ø  Eq stands for the quantization noise
    Ø  Ed stands for DAC non-idealities (jitter + thermal noise)
    Ø  Filter’s thermal noise is accounted in Eh
                                                               Eh                                         Eq
                                                           X            Ve               Vy                         Y
                                                                    S          H(s)           ZOH              S

                                                               Ef
                                                                                  S                 Z-1
                                                                             Ed


    Ø  The modulator’s output becomes
                                                                                      H ( s )* ZOH ( s )
   Y = STF * ( X + Ed + Eh ) + NTF * Eq                        STF =
    Ø  The error signal (Filter’s input) is                                 1+ H ( s )* ZOH ( s )* Z −1
                                                                                              1
                    {
 Ve = NTF* H ( s ) ZOH ( X + E d + E h ) + Z   −1
                                                    *E q   }   NTF =
                                                                             1+ H ( s )* ZOH ( s )* Z −1
J. Silva-Martinez                                                                                          - 32 -
 TAMU-ECE                                                                                     Barcelona, 2012


                     Oversampled A/D Conversion
                     Feed-forward configuration
            Eh                                      Eq                          H ( s )* ZOH ( s )
        X            Ve            Vy                        Y   STF =
                                                         S
                                                                         1+ H ( s )* ZOH ( s )* Z −1
                 S         H(s)         ZOH

            Ef
                                                                                        1
                               S              Z-1                NTF =
                          Ed                                             1+ H ( s )* ZOH ( s )* Z −1
 Ø  The system parameters are defined as                          Z = e jωTS
                                                                                        ⎛ ωTS ⎞
                                                                   ZOH (z ) = TS * sin c⎜     ⎟
 Ø  The lowpass transfer function H(s)                                                 ⎝  2 ⎠
      provides large loop gain (Noise shaping)
       Ø  DC gain >>0 dB
       Ø  Enough phase margin at 0 dB gain
       Ø  Z is a complex number (phase)
       Ø  Loop stability is fundamental

J. Silva-Martinez                                                                                     - 33 -
 TAMU-ECE                                                                                                                    Barcelona, 2012


                              Oversampled A/D Conversion
                              Feed-forward configuration
                     Eh                                      Eq
                                            Vy                        Y
                                                                                             Z = e jωTS
                 X            Ve
                          S         H(s)         ZOH              S
                                                                                                                  ⎛ ωT ⎞
                                                                                             ZOH (z ) = TS * sin c⎜ S ⎟
                     Ef                                                                                           ⎝ 2 ⎠
                                        S              Z-1
                                                                                       Ø  Notice that
                                   Ed
  dB                                                                                                           ⎛ ⎛        ⎞
     0                                                                                                         ⎜ ⎜   f ⎞ ⎟
                                                                                                                         ⎟
                                                                                             ZOH ( f ) = sin c ⎜ π ⎜   ⎟ ⎟
    -­‐5                                                                                                       ⎜ ⎜ f ⎟ ⎟
                                       ⎛ f      ⎞                              0
                                                                                                               ⎝ ⎝ S ⎠ ⎠
                                       ⎜        ⎟
  -­‐10                            sin ⎜ π      ⎟
                       ⎛ f ⎞         ⎜ f      ⎟                             -­‐5
                       ⎜     ⎟       ⎝    S   ⎠
  -­‐15          sin c ⎜ π   ⎟ =                                            -­‐10
                       ⎜ f ⎟             f
  -­‐20
                       ⎝   S ⎠      π                                       -­‐15

                                          fS                                  -­‐20
  -­‐25
                                                                              -­‐25

  -­‐30                                                                       -­‐30
           0.1                               f                            1            0.1     0.2   0.3   0.4   0.5   0.6   0.7   0.8     0.9    1



                                            fS
J. Silva-Martinez                                                                                                                        - 34 -
 TAMU-ECE                                                                                     Barcelona, 2012

                    Oversampled A/D Conversion
                    Use Mason’s rule again!
               Eh                                      Eq
                                      Vy                        Y
                                                                                   L ( f )* Z
           X
                    S
                        Ve
                              H(s)         ZOH              S              STF =
                                                                                   1+ L ( f   )
               Ef                                                                      1
                                  S              Z-1                       NTF =
                             Ed                                                    1+ L ( f   )
                              Z = e jωTS = cos(ωTS ) + j * sin(ωTS )
                                                                       Ø  L(f) is defined as the
                                                   ⎛ ωT ⎞               loop gain
                              ZOH (z ) = TS * sin c⎜ S ⎟
                                                   ⎝ 2 ⎠
                              L( f ) = H (z )* ZOH (z )* Z −1
                                                                       Ø  Phase of L(f) is quite
                                                                          important for stability


                                                                       Ø  Z is quite relevant for
                                                                          phase of L(f)

J. Silva-Martinez                                                                                     - 35 -
   TAMU-ECE                                                                                   Barcelona, 2012



                    Continuous-Time ΣΔ Modulators
           Eh                                       Eq
       X            Ve              Vy                       Y      Ø  For in-band frequencies STF
                S           H(s)         ZOH             S
                                                                      is determined by H(f)
           Ef
                                               -1
                                                                    Ø  At medium-high frequencies,
                                S              Z
                                                                      the blocker rejection is
                           Ed                                         limited (LTE)
 ADC                                                                Ø  Peaking if phase of L(f)
                                                                      phase margin is not enough
                    L(f)

                    STF             NTF                             Ø  At high-frequencies, the
0 dB                                                         Freq     anti-alias is mainly provided
                                                    Fs                by the sinc function rather
                                               H(f)                   than by the filter
                                                                             L ( f )* Z
                                                   ZOH(f)              STF =
                                                                             1+ L ( f )
                                                                                  1
                                                                       NTF =
  J. Silva-Martinez                                                          1+ L ( f )          - 36 -
 TAMU-ECE                                                                                          Barcelona, 2012



                    Oversampled A/D Conversion
    Ø  Remarks on DAC non-idealities. Same analysis apply to the
         input referred filter’s noise
         Eh                                      Eq               YDAC = STF * Ed
     X            Ve            Vy                        Y
              S         H(s)         ZOH              S                       H ( s )* ZOH ( s )
                                                                 STF =
         Ef                                                              1+ H ( s )* ZOH ( s )* Z −1
                            S              Z-1
                                                              Ø  DAC non-idealities are
                       Ed
                                                                 reflected at the ADC output
                                                                 similarly to the signal
                                                              Ø  Baseband noise can be directly
                                                                 mapped to ADC input (Ed and Eh)
                                                              Ø  Non-linearities in DAC that translate
                                                                 HF noise into baseband affects
                                                                 directly SQNR

                                                              Ø  DAC is an extremely
                                                                 critical component
J. Silva-Martinez                                                                                          - 37 -
 TAMU-ECE                                                                                                              Barcelona, 2012



                     Oversampled A/D Conversion
       Ø  Remarks on Filter’s operation: Filter’s input
           Eh                                                Eq                            X + E d + E h + Z −1 * E q
       X            Ve                 Vy                               Y           Ve =
                S               H(s)        ZOH                   S
                                                                                                     1+ L ( s )
                                                                                                 Transition       Out of
           Ef
                                                        -1
                                                                            Ve(f)    Inband        band           band
                                S                     Z
                          Ed


                         X(f)
 ADC

                         H(f)
                                                                                                                           Fs Freq
                                            1/(1+L)               Ø  For the single feedback loop architectures, the inband
0 dB                                                                  signal is usually very small: Nice property but…
                                                Fs Freq
                                                                  Ø  Transition band is more critical for filter’s linearity
                                                                      (neighbor channels); is this bad? Could be worse and it is!
                                               ZOH(f)
                                                                  Ø  Medium and high frequency 1/(1+L) gain could be around
                                                                      2-10 dB!
                                                                  Ø  Filter must be designed for out-of-band blockers!
J. Silva-Martinez                                                                                                               - 38 -
 TAMU-ECE                                                                                                   Barcelona, 2012



                    Oversampled A/D Conversion
    Ø  Remarks on Filter’s operation: Filter’s input
                                                    Eq
        Eh                                                                     X + Ed + Eh
    X            Ve                Vy                          Y        Ve =               + NTF * Z −1 * Eq
             S         H(s)             ZOH              S                       1 + L(s )
        Ef
                           S                  Z-1
                      Ed                                               Ø  Ef is an out-of-phase replica of the X+Ef+Eh if
                                                                         L(f)>>1
                                                                       Ø  When loop gain reduces, the loop is less
                                                                         effective and all HF input signals appear at
                               Transition     Out of
                                                                         filter input
Ve(f)        Inband              band         band
                                                                       Ø  Filter must be very linear at HF to
                                                                         minimize signal intermodulation
                                                                         distortions
                                                                       Ø Filter must be designed for the
                                                                         blockers
                                                                       Ø Blocker tolerance is a major issue in
                                                             Fs Freq
                                                                         broadband applications (WiMAX)
J. Silva-Martinez                                                                                                     - 39 -
 TAMU-ECE                                               Barcelona, 2012



             Continuous-Time ΣΔ Modulators

                             Ø  This is a realistic model
                             Ø  Check the phase of the loop at
                                the unity gain frequency!

                                                    L (f )* Z
                                              STF =
                                                    1 + L (f )
                                                     Z −1/ 2
                                              NTF =
                                                    1 + L (f )




J. Silva-Martinez                                               - 40 -
 TAMU-ECE                                                                        Barcelona, 2012



             Stability Issues: ΣΔ Modulators

                                            ADC



                                                                                   Fs

                                            0                                                    Freq
                                                        L(f)            H(f)
                                            π
  Ø  Check the phase contribution of                                                   φ ( H (f ))
                                            2
       the filter and the delay
       element!                                π
  Ø  Check the phase of the loop          3π
                                                                                   ⎛ f ⎞
                                                                                   ⎜   ⎟
       at the unity gain frequency!        2                                   2 π ⎜   ⎟
                                                                                   ⎜ f ⎟
                                                                                   ⎝ S ⎠
  Ø  Can you stabilize the loop
                                                           L (f )* Z
       employing the conventional filter           STF =
       design approach?                                    1 + L (f )
                                                          Z −1/ 2
  Ø  Additional parasitic poles!                  NTF =
                                                         1 + L (f )
J. Silva-Martinez                                                                            - 41 -
 TAMU-ECE                                                         Barcelona, 2012



             Stability Issues: ΣΔ Modulators


                                             ADC



                                                    H(f)          Fs

Ø With a filter with 2 zeros                0                              Freq
  (finite gain at high frequency)            π
                                                           L(f)        φ ( H (f ))
  Ø  Hard to stabilize the loop if the      2
     unity gain frequency is close to Fs/
     2! (Very Low OSR)                          π
  Ø  Notice that the delay element add     3π
     -180 degrees at f=Fs/2                                     ⎛ f ⎞
                                                                ⎜   ⎟
                                            2               2 π ⎜   ⎟
  Ø  If the loop unity gain frequency is                       ⎜ f ⎟
                                                                ⎝ S ⎠
     not beyond f=Fs/4, then maximum
     phase contribution due to the delay
     element is <-90 degrees
J. Silva-Martinez                                                         - 42 -
 TAMU-ECE                                                                     Barcelona, 2012



             Stability Issues: ΣΔ Modulators
                                                 Ø  Not very difficult to stabilize the
                                                   loop if the unity gain frequency is
                                                   below Fs/4! (not very Low OSR);
                                                   e.g. around 100Mhz if clock
                                                   frequency is 400MHz
                                                 Ø  Notice that larger oversampling
                                                   ratio allow you to reduce the filter
                                                   gain at high-frequency
  ADC                                            Ø  Out-of-Band noise is distributed in
                                                   wider n=bandwidth, hence smaller
                                                   noise density but same integrated
                                          H(f)
                                                   noise
 0                                                         Freq
                        φ ( H (f ))
 π
                                         L(f)
  2                            ⎛ f ⎞
                               ⎜   ⎟
                           2 π ⎜
     π                              ⎟
                               ⎜ f ⎟
                               ⎝ S ⎠
3π
                                                         Fs
 2

J. Silva-Martinez                                                                     - 43 -
 TAMU-ECE                                                                                  Barcelona, 2012

                Oversampled A/D Conversion
                Multiple Feedback architecture
     EH1                 EH2                           Eq
                                          Vy
 X
       S
           Ve
                 H1(s)        S   H2(s)        ZOH          S
                                                                Y   This architecture presents
                                                                    several interesting
  D1                     D2                                         properties, but be careful
                     S                           Z-1                with its drawbacks!
                Ed


Ø  Eq stands for the                     Y = STF * ( X + Ed + EH 1 ) + NTF * Eq + STF 2 * EH 1
     quantization noise
                                                                 H1 (s )* H 2 (s )* ZOH
Ø  Ed stands for DAC non-                STF =
     idealities (jitter + thermal
                                                                               {
                                                       1 + {D1* H1 (s ) + D 2}* H 2 (s )* ZOH * Z −1    }
     noise)                                                          ZOH
                                          NTF =
Ø  Filter’s thermal noise is                                                  {
                                                1 + {D1* H1 (s ) + D 2}* H 2 (s )* ZOH * Z −1               }
     accounted in EH1,2
                                                                   H 2 (s )* ZOH
Ø  D1,2 are the DAC                      STF 2 =
     coefficients                                                                  {
                                                  1 + {D1* H1 (s ) + D 2}* H 2 (s )* ZOH * Z −1              }
J. Silva-Martinez                                                                                  - 44 -
 TAMU-ECE                                                                                                   Barcelona, 2012

                     Oversampled A/D Conversion
                     Feedback architecture
    EH1                  EH2                           Eq
                                                                    Y = STF * ( X + Ed + E H 1 ) + NTF * Eq + STF 2 * E H 2
                                          Vy
X          Ve                                                   Y                     H1 (s )* H 2 (s )* ZOH
      S          H1(s)        S   H2(s)        ZOH          S       STF =
                                                                                                    {
                                                                            1 + {D1* H1 (s ) + D 2}* H 2 (s )* ZOH * Z −1     }
                         D2                                                                      ZOH
 D1                                                                 NTF =
                     S                           Z-1
                                                                                                     {
                                                                            1 + {D1* H1 (s ) + D 2}* H 2 (s )* ZOH * Z −1     }
                                                                                               H 2 (s )* ZOH
                Ed                                                  STF 2 =
                                                                                                        {
                                                                              1 + {D1* H1 (s ) + D 2}* H 2 (s )* ZOH * Z −1       }
    Ø  Notice that in-band STF is still approximately unity (1/D1 if
          D1H1>>D2) up to the unity gain frequency
    Ø  The error signal becomes:

     Ve =
          ( X + Ed + EH 1 )(1 + D2* H 2 (s )* ZOH * Z −1 ) + NTF * Z −1 * (H (s )* E + E )
          1 + {D1* H1 (s ) + D 2}* {H 2 (s )* ZOH * Z −1}
                                                                            2       H2  q



    Ø  In-band signal level at Ve is approximately obtained as
           (X + Ed + EH 1 )* D2 + EH 2 +              Eq
     Ve ≅
                D1* H1 (s ) + D 2        {D1* H1 (s ) + D2}* {H 2 (s )}
J. Silva-Martinez                                                                                                   - 45 -
 TAMU-ECE                                                                                    Barcelona, 2012

                    Oversampled A/D Conversion
                    Feedback architecture
         EH1                 EH2                           Eq
                                              Vy
                                                                    Y
     X
           S
               Ve
                     H1(s)        S   H2(s)        ZOH          S                         D1=1

      D1                     D2
                         S                           Z-1

                    Ed

    Y = STF * ( X + Ed + E H 1 ) + NTF * Eq + STF 2 * E H 2
           H1 (s )* H 2 (s )* ZOH
    STF =
                  1 + L( f )
             ZOH
    NTF =
           1 + L( f )

    STF 2 =
            H 2 (s )* ZOH                                                             {
                                         L( f ) = {D1* H1 (s ) + D2}* H 2 (s )* ZOH * Z −1                     }
               1 + L( f )
 Ø  Out of band STF is quite small; excellent for blockers rejection
 Ø  NTF follows the ZOH at very high frequencies, Minimizing the alias issue
 Ø  For STF2, again, the ZOH helps, but..                              The ZOH provides -4 dB
                                                                        attenuation at f=0.5fs and
 Ø  The ZOH is excellent filter around f=fs                            -20 dB at f=0.9fs
J. Silva-Martinez                                                                                    - 46 -
 TAMU-ECE                                                                                                   Barcelona, 2012

                 Oversampled A/D Conversion
                 Feedback architecture
      EH1                 EH2                           Eq
                                           Vy
  X         Ve                                                    Y                                 D1=1
        S         H1(s)        S   H2(s)        ZOH          S


   D1                     D2
                      S                           Z-1

                 Ed


Ve1 =
      (X + Ed + EH 1 )(1 + D2* H 2 (s )* ZOH * Z −1 )
                         1 + L( f )
Ø  For in-band signals apparently is fine:
             ( X + Ed + EH 1 )D2                                                                       {
                                                                           L( f ) = {D1* H1 (s ) + D2}* H 2 (s )* ZOH * Z −1   }
       Ve1 ≅
               D1* H1 (s ) + D 2                                 Ø  For out-band signals:
Ø  At the output of H1(s) we get                                                        (
                                                                 Ve1 = ( X + Ed + EH 1 ) 1 + D 2* H 2 (s )* ZOH * Z −1             )
                  ⎛ D 2 ⎞                                      Ø  Most of the blockers and HF noise
       VH 1−out ≅ ⎜     ⎟( X + Ed + EH 1 )
                  ⎝ D1 ⎠                                            sources are present at H1 input
 J. This signal
Ø Silva-Martinez could be excessive for H2                                                                          - 47 -
 TAMU-ECE                                                                                               Barcelona, 2012

                    Oversampled A/D Conversion
                    Feedback architecture
      EH1                   EH2                           Eq
                                             Vy                                                  D1=1
  X          Ve                                                    Y
        S           H1(s)        S   H2(s)        ZOH          S


   D1                       D2
                       S                            Z-1

                  Ed
            ZOH * Z −1 * (H 2 (s )* EH 2 + Eq )
  Ve 2 =
                  1 + L( f )
  Ø  For in-band signals:
                   EH 2           Eq                                                               {
                                                                       L( f ) = {D1* H1 (s ) + D2}* H 2 (s )* ZOH * Z −1   }
            Ve 2 =        +
                   H1 (s ) H1 (s )* H 2 (s )
  Ø  At medium and HF only the ZOH helps

        Ve 2 = ZOH * (H 2 (s )* EH 2 + Eq ) Ø  Looks like EH2 and Eq are not the main
                                                          issue in this topology
J. Silva-Martinez                                                                                                - 48 -
 TAMU-ECE                                                                                 Barcelona, 2012

              Oversampled A/D Conversion
              Multiple Feedback architecture
      EH1                   EH2                           Eq
  X
                                             Vy
                                                                   Y   This linear model is probably
            Ve
        S           H1(s)        S   H2(s)        ZOH          S       more appropriated for the
                                                                       feedback architecture!
   D1                       D2
                      S                             Z-1                ZOH does not affect the
                 Ed
                                                                       numerator of NTF
                                     Y = STF * ( X + E d + E H 1 ) + NTF * E q + STF 2* E H 2
Ø  Eq stands for the
   quantization noise                        H 1 (s )* H 2 (s )* ZOH
                          STF =
Ø  Ed stands for DAC non-      1 + {D 1* H 1 (s ) + D 2}* {H 2 (s )* ZOH * Z                     −1
                                                                                                       }
   idealities (jitter + thermal
   noise)                                                    1
                              NTF =
Ø  Filter’s thermal noise is       1 + {D 1* H 1 (s ) + D 2}* {H 2 (s )* ZOH * Z                 −1
                                                                                                       }
   accounted in EH1,2
Ø  D1,2 are the DAC                                            H 2 (s )* ZOH
   coefficients                      STF 2 =
                                             1 + {D 1* H 1 (s ) + D 2}* {H 2 (s )* ZOH * Z             −1
                                                                                                            }
J. Silva-Martinez                                                                                 - 49 -
 TAMU-ECE                                                                                   Barcelona, 2012

                    Oversampled A/D Conversion
                    Feedback architecture
                                                  Y = STF * (X + E d + E H 1 ) + NTF * E q + STF 2* E H 2
                                                                       H 1(s )* H 2 (s )* ZOH
                                                  STF =
                                                                                      H
                                                          1 + {D 1* H 1(s ) + D 2}* { 2 (s )* ZOH * Z −1}
                                                                                 1
                                                  NTF =
                                                                                     H
                                                          1 + {D 1* H 1(s ) + D 2}* { 2 (s )* ZOH * Z −1}
                                                                               H 2 (s )* ZOH
                                                  STF 2 =
                                                                                         H
                                                            1 + {D 1* H 1 (s ) + D 2}* { 2 (s )* ZOH * Z −1}

Ø  Notice that in-band STF is still approximately unity (1/D1 if
   D1H1>>D2) up to the unity gain frequency; D1 is usually set as 1
Ø  The error signal becomes:

 Ve =
      (X + E d + E H 1 )(1 + D 2* H 2 (s )* ZOH * Z −1 ) + NTF * Z −1* (H (s )* ZOH * E + E )
                                                                         2             H2  q
                                 H
       1 + {D 1* H 1(s ) + D 2}* { 2 (s )* ZOH * Z −1}

Ø  In-band signal level at Ve is approximately obtained as
      (X + E d + E H 1 )* D 2 + E H 2 +                   Eq
 Ve ≅
           D 1* H 1(s ) + D 2           {D 1* H 1(s ) + D 2}* {H 2 (s )* ZOH }
J. Silva-Martinez                                                                                   - 50 -
 TAMU-ECE                                                                                          Barcelona, 2012

                    Oversampled A/D Conversion
                    Feedback architecture
                                                                                               D1=1




 Y = STF * (X + E d + E H 1 ) + NTF * E q + STF 2* E H 2
                       H 1(s )* H 2 (s )* ZOH
  STF =
                                      H
          1 + {D 1* H 1(s ) + D 2}* { 2 (s )* ZOH * Z −1}
                                 1
  NTF =
                                      H
           1 + {D 1* H 1(s ) + D 2}* { 2 (s )* ZOH * Z −1}
                               H 2 (s )* ZOH
  STF 2 =
                                         H
            1 + {D 1* H 1 (s ) + D 2}* { 2 (s )* ZOH * Z −1}                               {
                                                               L( f ) = {D1* H1 (s ) + D2}* H 2 (s )* ZOH * Z −1     }
 Ø  Out of band STF is quite small; excellent for blockers rejection
 Ø  NTF does not follows the ZOH at very high frequencies
 Ø  For STF2, again, the ZOH helps, but.. The ZOH provides -4 dB
                                                                  attenuation at f=0.5fs and -20 dB
 Ø  The ZOH is excellent around f=fs
                                                                  at f=0.9fs
J. Silva-Martinez                                                                                          - 51 -
 TAMU-ECE                                                                                    Barcelona, 2012

             Oversampled A/D Conversion
             Feedback architecture
                                                                                     D1=1




Ve1 =
      (X + Ed + EH 1 )(1 + D2* H 2 (s )* ZOH * Z −1 )
                         1 + L( f )
Ø  For in-band signals apparently is fine
   if D2 is not very large                                                              {
                                                            L( f ) = {D1* H1 (s ) + D2}* H 2 (s )* ZOH * Z −1   }
      Ve1 ≅
            ( X + Ed + EH 1 )D2
              D1* H1 (s ) + D 2                   Ø  For out-band signals:
Ø  At the output of H1(s) we get             Ve 1 ≅ (X + E d + E H 1 )(1 + D 2* H 2 (s )* ZOH * Z −1 )

                    ⎛ D 2 ⎞                    Ø  Most of the blockers and HF noise
         VH 1−out ≅ ⎜     ⎟ ( X + Ed + E H 1 )     sources are present at H1 input
                    ⎝ D1 ⎠
 J. This signal
Ø Silva-Martinez could be excessive for H2                                       - 52 -
 TAMU-ECE                                                                                     Barcelona, 2012

                    Oversampled A/D Conversion
                    Feedback architecture
                                                                                       D1=1




         Z −1* (H 2 (s )* ZOH * E H 2 + E q )
Ve 2   =
                        1 + L (f )
  Ø  For in-band signals:
               EH 2           Eq
        Ve 2 =        +                                                                 {
                                                            L( f ) = {D1* H1 (s ) + D2}* H 2 (s )* ZOH * Z −1   }
               H1 (s ) H1 (s )* H 2 (s )
  Ø  At medium and HF only the ZOH helps

       Ve 2 = ZOH * H 2 (s )* E H 2 + E q   Ø    Looks like EH2 and Eq are not the main
                                                  issue in this topology
J. Silva-Martinez                                                                                      - 53 -
 TAMU-ECE                                                                    Barcelona, 2012



                    CT ΔΣ ADC Non-idealities
      DAC Non-idealities

      §  Excess loop delay : Constant delay between ideal and implemented
          DAC feedback pulse
            Ø Decision time required by quantizer affecting latches used for
               synchronizing DAC inputs
            Ø Finite response time of DAC to its clock and inputs
            Ø Excess Loop Delay can be incorporated: Z-1èZ-1+Δ	



      §  Inter-symbol interference : Finite slew rate of DAC outputs with
          unequal rise and fall times
            ‒  Additional noise and tones fold into baseband

      §  Clock jitter in DAC
                                              Processed by STF
      §  DAC and Filter Non-linearity
                                              Not noise-shaped

J. Silva-Martinez                                                                    - 54 -
 TAMU-ECE                                                                                  Barcelona, 2012




  Typical Quantizer: Flash Architecture
                                                                  Ø  S/H operates at clock rate
     +Vref Vin
                                                                  Ø  Huge input capacitance if N>6
    R/2             +                                                 Ø Kick back noise
                    -
                                                       Digital


                                            data
                             Thermometric
     R              +
                                                       Signal     Ø  Requires a precise low-
                               to Binary
                    -


                                                      Processor       impedance resistive ladder:
                    +                                    and          Ø Power-accuracy-Speed tradeoff
                    -
                                            Digital


     R                                                Memory
                    +
                    -                                             Ø  Limited by comparator
    R/2                                                               Ø Speed and accuracy
                                                                      Ø Offset voltage
      -Vref         flock
                     c


                                                                  Ø  Hard to improve its resolution


         State of the art: ~ 2.4 GS/s 6 bits resolution
J. Silva-Martinez                                                                                  - 55 -
 TAMU-ECE                                                                                    Barcelona, 2012



              Flash Based Quantizer Architecture

                      Vi         VFS   Vi                                  §  Reference ladder
                                              Strobe
                           VFS
                                                    fs                        consists of 2N equal
      7
                           7Δ
                                                                              size resistors
          6                                                                §  Input is compared
                           6Δ                                                 to 2N-1 reference
              5
                                                                              voltages.




                                                          Encoder
                           5Δ
                                                                    Dout
                  …
                  …


                                 …
                                       …

                                              …                            §  Massive parallelism
                           2Δ                                              §  Fastest ADC
                  1
                                                                              architecture
                           Δ
                      0                                                    §  Latency = 1T = 1/fs
    Do                     0
                                                N
                                                                           §  Throughput = fs
                                               2 -1
                                            comparators                    §  Complexity = 2N


J. Silva-Martinez                                                                                    - 56 -
 TAMU-ECE                                                            Barcelona, 2012



                           ADC Input Capacitance
                       2
           2       A
        σ (VT 0 ) = VT 0     C g = 10 fF / µm 2
                    WL
                                                             # of
    •  N = 6 bits             →  63 comparators   N (bits)           Cin (pF)
                                                             comp.
    •  VFS = 1V               →  1 LSB = 16mV
                                                     4        15          1
    •  σ = LSB/4              →  σ = 4mV
                                                     6        63          3.9
    •  AVT0 = 10mV·µm →  L = 0.24µm,
                                                     8       255          16
                         W = 26µm



  •  Small Vos leads to large device sizes, hence large area and power.
  •  Large comparator leads to large input capacitance, difficult to drive and
     difficult to maintain bandwidth.



J. Silva-Martinez                                                             - 57 -
 TAMU-ECE                                                                                Barcelona, 2012



                     Kick-back noise and coupling
                              capacitors

                             M3   M4                       M5        M6


                      Cgd1             Cgd2                     Φ
                                                                                  Φ      Mode
                             M1   M2          VR
      Vin                                          V o+                   Vo-   “high”   Track
                RS                                              M9
                      Cgs1             Cgs2
                                                                                “low”    Regen.
                                       CS             M7             M8




  •  Preamp delay and Vth of sampling switch (M9) are both signal-dependent
     → signal-dependent sampling point (aperture error)
  •  A major challenge of distributing clock signals across 2N-1 comparators
     in flash ADC with minimum clock skew (routing, Vth mismatch of M9)


J. Silva-Martinez                                                                                - 58 -
 TAMU-ECE                                                                              Barcelona, 2012



                     Fully-Differential Comparator


                               M5 M6

                                                                Φ
                                                           M7       M8
                                                                                  Φ

                    M1 M2                    M3 M4
                                                                            Vo+         Vo-
                                                                                  M9
           Vi+                VR+ VR-                Vi-




                            Fully-diff. PA                               Latch


   •  Double-balanced, fully-differential preamp
   •  Switches (M7, M8) added to stop input propagation during regeneration
   •  Active pull-up PMOS added to the latch


J. Silva-Martinez                                                                              - 59 -
 TAMU-ECE                                                                                                 Barcelona, 2012



                                     DAC Non-idealities
                    Sources of jitter error                      Jitter errors in rectangular DAC
                                       esamp(t)                  pulse
                                                         hNRZ(t)
  Vin                                             Dout
                        H(s)                                                    TS
               _                                                        tdn
                                Ts = 1/Fs                                       tpn
                                                             1
     Vdac(t)

                               DAC
                                                            0         tn a Ts         bTs    tn+1                   tn+1 t
                   edac(t)                                       tpn = (b	
  -­‐ 	
  a )TS + Dtpn ® Pulse-position jitter
                                                                 tdn = a TS + Dtdn                ® Pulse-position jitter


    §  Pulse-width jitter: Random variation in charge fed back per clock cycle
          ‒  Wide-band clock phase noise modulates out-of-band ADC inputs and
             quantization noise to in-band

    §  Pulse-position jitter: Random variation in integration interval of constant charge
          ‒  Amplitude errors due to PP jitter are at least 1st-order noise-shaped


J. Silva-Martinez                                                                                                  - 60 -
 TAMU-ECE                                                                 Barcelona, 2012


                          Binary-Weighted CR DAC

              Cu = unit capacitance                            CP
                                                                          Vo
                                                                VX


                    8Cu        4Cu        2Cu        Cu              Cu




              VR


                          b3         b2         b1        b0

                §  Binary-weighted capacitor array → most efficient
                    architecture
                §  Bottom plate @ VR with bj = 1 and @ GND with bj = 0

J. Silva-Martinez                                                                 - 61 -
 TAMU-ECE                                                                                           Barcelona, 2012


                             Binary-Weighted C-DAC
                                                        CP
                                                                   Vo
                                                         VX
                                                                                     N
                                                                             ⎛                           ⎞
                                                                             ⎜ ∑ bN− j ⋅ 2N− j Cu ⎟
          8Cu          4Cu        2Cu         Cu              Cu
                                                                        Vo = ⎜                           ⎟ ⋅ V
                                                                                    j=1
                                                                             ⎜              N
                                                                                                  N− j
                                                                                                          ⎟ R
                                                                             ⎜ Cp + Cu + ∑ 2 Cu ⎟
                                                                             ⎜                           ⎟
     VR
                                                                             ⎝             j=1           ⎠
                                                                             ⎛ N                  ⎞
                b3           b2         b1         b0
                                                                             ⎜ ∑ bN− j ⋅ 2N− j Cu ⎟
                                                                           = ⎜                    ⎟ ⋅ V
                                                                                j=1
                                                                             ⎜ C + 2N C ⎟ R
                                                                                      p        u
                          ⎛ 2N Cu ⎞             N b                        ⎜
                                                                             ⎜                    ⎟
                                                                                                   ⎟
                     Vo = ⎜           ⎟ ⋅ VR ⋅ ∑ N- j                      ⎝                    ⎠
                          ⎜ C + 2N C ⎟         j=1 2
                                                       j
                          ⎝  p      u ⎠



                     §  Cp → gain error (nonlinearity if Cp is nonlinear)
                     §  INL and DNL limited by capacitor array
                          mismatch

J. Silva-Martinez                                                                                           - 62 -
 TAMU-ECE                                                                             Barcelona, 2012



                               Stray-Insensitive C-DAC

           ⎛                               ⎞
           ⎜                               ⎟
                      2N Cu                 ⎟ ⋅ V ⋅ bN- j
                                                     N
      Vo = ⎜
           ⎜ N      Cp + 2N+1Cu − Cu       ⎟ R ∑ 2 j
                                                    j=1
           ⎜ 2 Cu +                        ⎟                               16Cu
           ⎝               A               ⎠
                                                                       CP

                                                                        VX                  Vo
                                                                                A
                    8Cu          4Cu          2Cu            Cu

                                                                             Large gain A
                                                                             needed to
          VR                                                                 attenuate
                                                                             summing-node
                                                                             charge sharing
                          b3           b2           b1            b0



J. Silva-Martinez                                                                             - 63 -
 TAMU-ECE                                                        Barcelona, 2012



      Binary-Weighted Current Steering DAC

                             N    bN- j
                    Vo = IR ⋅ ∑        j
                                                             R
                            j=1    2
                                                        VX
                                                                   Vo
             b3        b2                   b1     b0
                                                             A

            I/2       I/4                  I/8   I/16




     §    Current switching is simple and fast.
     §    Vo depends on Rout of current sources without op-amp.
     §    INL and DNL depend on matching, not inherently monotonic.
     §    Large component spread (2N-1:1)

J. Silva-Martinez                                                        - 64 -
 TAMU-ECE                                                        Barcelona, 2012




                            Unit Current Cell
                                       ...                      Io

                                Φ
                bN
                                             Sj           Sj
                     ROW/COL
               ...



                      Decoder   Φ
                b1
                                                     I


     §  2N current cells typically broken up into a (2N/2 X 2N/2)
        matrix
     §  Current source cascoded to improve accuracy
     §  Coupled inverters improve synchronization of current
        switches.

J. Silva-Martinez                                                        - 65 -
 TAMU-ECE                                       Barcelona, 2012



                    Randomization and Dummies




J. Silva-Martinez                                       - 66 -
 TAMU-ECE                                                               Barcelona, 2012



      Example: “8+2” Segmented Current DAC




     C.-H. Lin and K. Bult, "A 10-b, 500-MSample/s CMOS DAC in 0.6mm2," IEEE
     Journal of Solid-State Circuits, pp. 1948-1958, 1998.

J. Silva-Martinez                                                               - 67 -
 TAMU-ECE                                                                                   Barcelona, 2012



          DAC Non-idealities in CT ΔΣ ADCs - 2
                                             Effects of DAC non-linearity
                                                     H(s) >> 1
                                              ≈0     in-band
                      Vin(t)               in-band
                                                                                     Dout
                                                       H(s)
                                       _
                                                                  Ts = 1/Fs

                    Vdac(t) ≈ Vin(t)
                       in-band                         DAC
                                                     Non-linear        Dout non-linear
                                                                          in-band


     §  Non-linearity caused due to mismatch between different output levels of
         DAC
          ‒  Variation in feedback levels yields signal-dependent feedback charge
             error directly fed to the modulator input.

     §  Low resolution feedback DAC requires linearity better than overall
         modulator

J. Silva-Martinez                                                                                   - 68 -
 TAMU-ECE                                                                   Barcelona, 2012



DAC Calibration (Signal-to-Distortion Ratio)
  This is a major (hot) research area in multi-bit sigma-delta
    modulators. Several alternatives have been reported; main
    trends are:

     §  Randomize the errors such that the non-linear errors are converted in
         noise instead of tones that degrades SNDR
           Ÿ    Dynamic element matching techniques
           Ÿ    Pseudo Randomizers such as Rotators
           Ÿ    Digital signal processors
           Ÿ    Drawbacks?

     §  Calibration
        Ÿ  By design using large overdrive voltages and large dimensions
        Ÿ  Pre-calibration of current cells
        Ÿ  Other options?




J. Silva-Martinez                                                                   - 69 -
 TAMU-ECE                                                                          Barcelona, 2012



            Current Cell Design Considerations
     Matching considerations                  Trade-off

     §  Sizing of current source transistors §  Higher overdrive voltage provides
                                                  better area efficiency at the
                                                  expense of reduced output swing
                                              §  Larger area results in greater
                                                  parasitic capacitances which limit
                                                  the speed of operation


                                                  DACi       Unit     (W/L), m=4 Total area,
     Output impedance                                       current                     µm2

     §  Greater than 700kΩ over 100MHz       DAC1-coarse   610uA     203µ/3.84µ        7795
         signal bandwidth                       DAC1-fine    35uA      48µ/16µ          7680
           ‒  Sufficient for 12-bits static      DAC2       1.55mA    323µ/2.4µ         6976
              (INL) and dynamic linearity        DAC3       960uA      255µ/3µ          6885
              (SFDR)                             DAC4       790uA     231µ/3.36µ        6985


J. Silva-Martinez                                                                          - 70 -
 TAMU-ECE                                                      Barcelona, 2012



                Multi-bit DAC Architecture: DEM




 §  Dynamic Element Matching (DEM), Self-calibration combined to
 achieve high linearity
 §  When DACi is under calibration, demultiplex Datai to dummy current
 cell
J. Silva-Martinez                                                      - 71 -
 TAMU-ECE                                                                                  Barcelona, 2012



                          Dynamic Element Matching
          Representing DAC input v using a thermometer DAC
                    v=1                                          v=3
    I8      I8      I8         I8             I8       I8        I8         I8
    I7      I7      I7         I7             I7       I7        I7         I7
    I6      I6      I6         I6             I6       I6        I6         I6
    I5      I5      I5         I5             I5       I5        I5         I5
    I4      I4      I4         I4             I4       I4        I4         I4
    I3      I3      I3         I3             I3       I3        I3         I3
    I2      I2      I2         I2             I2       I2        I2         I2
    I1      I1      I1         I1             I1       I1        I1         I1

     0       Ts          2Ts        3Ts            0        Ts        2Ts        3Ts


                                          t                                            t


    §    v = 1 can be represented by any one of I1-8
    §    Averaging all possible combinations produces the ideal output
    §    Use different combinations to represent a given code
    §    Errors are randomized
J. Silva-Martinez                                                                                  - 72 -
 TAMU-ECE                                                        Barcelona, 2012



                Implementation of DEM Scheme




       §  Shifter performs a Rotate-right shift on its inputs
       §  PN-sequence generator indicates number of shifts
       §  DEM is operated at 2GHz to maximize randomization

J. Silva-Martinez                                                        - 73 -
 TAMU-ECE                                                               Barcelona, 2012



                    PN-Sequence Generator
 §  Generates maximal length sequence based on 3rd-order primitive polynomial




                                  z-1         z-1       z-1       OUT
                         1               1          0         1

                             P(x) = x3 + x2 + 1     State: 1011




J. Silva-Martinez                                                               - 74 -
 TAMU-ECE                                                            Barcelona, 2012



 Analog Self-Calibration of Current Sources
                       Current Calibration Principle




     §  At the end of a calibration cycle, CCAL attains the correct VGS
     required to generate Iref

J. Silva-Martinez                                                            - 75 -
 TAMU-ECE                                                         Barcelona, 2012



                    Multi-bit Calibrated DAC




      §  Calibration control signals generated using a N-bit CMOS Ring
          Counter
      §  Extra dummy current cell used to implement continuous
          background calibration
J. Silva-Martinez                                                         - 76 -
 TAMU-ECE                                         Barcelona, 2012



                    Current Calibration Circuit




J. Silva-Martinez                                         - 77 -
 TAMU-ECE                                                                                   Barcelona, 2012



                          Simulation Results
                           Output Spectrum
                   0

                                                 Ideal
                                                 1% mismatch
                  -20
                                                 1% mismatch +
                                                 DEM + Calibration

                  -40



                  -60
    Power (dB)




                  -80

                                                                                       Self-        SNR
                 -100                                                Mismatch DEM
                                                                                    calibration     (dB)
                                                                        N       N       N           73.8
                 -120
                                                                        Y       N       N            55
                                                                        Y       Y       N           63.6
                 -140
                      0    1                        2                   Y   3   N       Y            70
                    10    10                     10                     10
                               Frequency (MHz)                          Y       Y       Y           72.7

J. Silva-Martinez                                                                                   - 78 -
 TAMU-ECE                                                                           Barcelona, 2012



         Clock Jitter Sensitivity (SJNR)
      §  The effect of clock jitter is present at the input of the
           quantizer and DAC.
      §  Jitter induced noise at DAC output is processed according
           to the NTF, which is a serious problem for continuous-
           time sigma-delta modulators

                               Loop Filter           Quantizer    Output
                                                                 (digital)
                                             uc(t)                           Y(n)
                                  1/s
                     Input
                    (analog)
                     xc(t)
                                              DAC


                                          Clock jitter introduce
                                         uncertainty at the DAC
                                         output (1 bit NRZ DAC)
J. Silva-Martinez                                                                           - 79 -
 TAMU-ECE           Barcelona, 2012




J. Silva-Martinez           - 80 -
 TAMU-ECE           Barcelona, 2012




J. Silva-Martinez           - 81 -
 TAMU-ECE                                                                                                                          Barcelona, 2012


Ji#er	
  Insensi*vity	
  of	
  Switched-­‐Capacitor	
  DACs	
  



                              Ji#er	
  error	
  




  • So	
  far,	
  SC-­‐DAC	
  is	
  the	
  most	
  ji#er	
  tolerant	
  approach	
  
  • Quite	
  precise	
  and	
  may	
  not	
  require	
  further	
  calibra*on	
  procedures	
  

  • 	
  Drawbacks	
  of	
  the	
  SC	
  DAC	
  
  • Peak	
  current	
  in	
  the	
  SC-­‐DAC	
  can	
  be	
  as	
  high	
  as	
  10	
  *me	
  IDAC	
  used	
  in	
  the	
  current	
  mode	
  DAC!	
  
  • Very	
  demanding	
  SR	
  for	
  the	
  OPAMP:	
  Power	
  consump*on	
  
  • Class	
  AB	
  OPAMP	
  may	
  help	
  while	
  dealing	
  with	
  this	
  issue	
  

J. Silva-Martinez                                                                                                                            - 82 -
 TAMU-ECE                                                                                                                                                                                                                             Barcelona, 2012



         Clock Jitter Sensitivity (SJNR)
Relationship between jitter and Phase noise: Lets consider a jittered signal
         cos (ω o t + ϕ n   )
The phase of the noisy signal is then computed as

            ⎛ ϕ         ⎞         ⎛ T * ϕ n   ⎞
            ⎜     n     ⎟         ⎜ t +       ⎟
        ω o ⎜ t +       ⎟ = ω o
            ⎜ ω         ⎟         ⎜           ⎟
            ⎝     o     ⎠         ⎝     2π    ⎠
Therefore, timing error can now be estimated as follows:
                                                                                68% of the samples
         ΔT         ϕn
               =                                                                                         -­‐ 0.2s 	
  	
  	
  	
  0.2s                                15% of the samples
          T         2π

  We can find the clock jitter variance
  employing the eye diagram, and making                                                                                                                                                                                                            DT
  the following histogram                             	
  	
  3s   2s 	
  	
  	
  	
  	
  	
  	
  s 	
  	
  	
  	
  	
  	
  	
  	
  	
  	
  0	
  	
  	
  	
  	
  	
  	
  	
  	
  s 	
  	
  	
  	
  	
  	
  	
  	
  2s 	
  	
  	
  	
  	
  	
  3s    T

                                                                   99.9% of the samples
J. Silva-Martinez                                                                                                                                                                                                                                  - 83 -
 TAMU-ECE                                                                              Barcelona, 2012



         Clock Jitter Sensitivity (SJNR)
           cos (ωo t + ϕn )                                                                 L ( dBc )
                                                         L (in dBc)                           10
                    2            2
                                                                             L ( f ) = 10
           ⎛ ΔT ⎞   ⎛ ϕn ⎞
           ⎜    ⎟ = ⎜    ⎟
           ⎝ T ⎠    ⎝ 2π ⎠

  Then

                      ⎛ T ⎞
                                 ∞
     RMS J per      = ⎜    ⎟   ∫ φn 2 (f )df
                      ⎝ 2π ⎠   −∞

                                                      Timing spectrum is correlated with phase
                                                      noise measured in the spectrum analyzer
  RMS value of total jitter

                                              ⎛ T ⎞    ∞
                        RMS J               = ⎜     ⎟ 2 ( L ( f   ) ) df
                                      per
                                              ⎜     ⎟  ∫
                                              ⎝ 2 π ⎠  0

J. Silva-Martinez                                                                                - 84 -
 TAMU-ECE                                                                                                         Barcelona, 2012


           Jitter Issues: High Clock Frequency
                                           Jittered
                          Loop Filter       Clock
                                                            Dout

  Vin                                                                                             D(n-1)


                                              Quantizer                                                    D(n)
        VDAC

                                Re-timed
                                 Data
                                               Flip-Flops
                    Multi-Bit                                                                                DT(t)
                     DAC

                                  Jittered                                            Error Function
                                   Clock

 The DAC error due to clock jitter:
                                                     ⎛ ΔT ( t ) ⎞
     J error ( n ) = ( D out ( n ) − D out ( n − 1) )⎜          ⎟
                                                     ⎜          ⎟
                                                     ⎝ T ⎠
 In the frequency domain: Differential of Dout convolves with Jn(ω)

                                                                   ⎡⎛   ⎛ ωTS   ⎞ ⎞         ⎤
                     [(             )                 ]
  J error (ω ) = 1 − Z −1 Dout (ω ) ⊗ J n (ω ) = ⎢⎜ 2 sin ⎜                     ⎟ ⎟Dout (ω )⎥ ⊗ J n (ω )
                                                                   ⎣⎝   ⎝ 2     ⎠ ⎠         ⎦
 In-band signal is shaped by 1 − Z −1, then it is not very critical
 Out-of-Band quantization noise and blockers convolve with the clock jitter
J. Silva-Martinez                                                                                                         - 85 -
 TAMU-ECE                                                                                               Barcelona, 2012

  Effect of clock jitter and Quantization noise on SNR
                                                 Δt ( n )
  e j ( n ) = (V out ( n ) − V out ( n − 1) )                     Quantization
                                                                                               NTF*Vq
                                                   T              noise
  then
                 {(           )              }
  E j ( Z ) = 1− Z −1 (V out ( Z ) ) ⊗ ( J ( Z ) )

  Or
                 {(           )(                                      )}
  E j ( Z ) = 1− Z −1 STF ( Z )* V in ( Z ) + NTF ( Z )V q ( Z ) ⊗ ( J ( Z ) )

  Therefore
                                                                                                                             f
               {(     )                          }
  E j ( Z ) = 1− Z −1 STF * V in ( Z ) ⊗ J ( Z ) +
                                                                                     Jn                                 Jn

             + {(1− Z ) NTF * V
                         −1
                                            ( Z )}⊗ ( J ( Z ) )   Clock
                                        q
                                                                  Phase
                               ⎛ ωT s               ⎞           Noise
                 −1
     1− Z              = 2 sin ⎜                    ⎟
                               ⎜                    ⎟
                               ⎝ 2                  ⎠                                                                          f
                                   1/ 2OSR                  2                  -fs                                 fs
                      P j ,S ≅ 2∫                E j (Z ) dθ                              SJNR is function of
                                   0
                                                                                          the convolution of
             1/ 2OSR                                                       2              NTF and J(Z)
P j ,Q ≅ 2∫              (1− Z ){(NTF (Z )V (Z )) ⊗ (J (Z ))} dθ
                                   −1
                                                            q
             0
J. Silva-Martinez                                                                                               - 86 -
 TAMU-ECE                                                                                                                                                                    Barcelona, 2012




Continuous-Time BP-ΣΔ ADC: Jitter effects
                                                                                                                            ⎛ ωT ⎞
                                                                                                                       sinc ⎜ s ⎟                               f
                                                                                                                   CLK      ⎝ 2 ⎠                        fck
                                                                                                                                                      Qn
                                        0     f0         fck                   0    f0                  fck

                                        Vin        + S            BPF(s)
                                                                  LPF(s)                                          Sampler             Hold            S
                                                    -                                                                                                2-bit
                                                                                                                                                                      Data
                                                                                         Quantization
                                                                                                                                                   Quantizer          out
                                                                                          and Jitter

                                                                           0
SJNR NRZ ≅ 60 dB ⇒
                                                                                   f0                  fck            0     f0               fck
                                                               Multi-bit
                                                                                                              S                                     Z-1
                                                                DAC
                                 2
⎛ OSR * P      ⎞ ⎛ T s   ⎞                                                                                         1-Z-1
⎜         in   ⎟ ⎜       ⎟
                                     > 10 6
                                                                      Jitter induced noise

⎜              ⎟ ⎜       ⎟                                                                                                   Jn          f0

⎝    4         ⎠ ⎜ σ j
                   ⎝
                            ⎟
                            ⎠
                                                                           f0                    fck                      X
                                                                                                                                         0                  fck

σ j ≈< 10 −3 T s

 In absence of blockers, assuming white jitter, the jitter induced
 noise has been usually approximated as:     ⎛                 ⎞
                                             ⎜                 ⎟                                                                                   ⎛ ω T                   ⎞
                                     ⎛                                     ⎞                                              ⎜ OSR * P in * sinc 2 ⎜ o s                     ⎟ ⎟
                                     ⎜                                     ⎟
                                     ⎜               P in                  ⎟
                                                                                                                            ⎜                       ⎜
                                                                                                                                                     ⎝ 2
                                                                                                                                                                              ⎟ ⎟
                                                                                                                                                                              ⎠ ⎟
      SJNR NRZ ≅ 10 log 10                                                  ⎟ = 10 log 10
                                                                                                                            ⎜
                                     ⎜
                                     ⎜
                                         (   2
                                                   (
                                     ⎜ ∫ J n ⊗ 1 − Z
                                                      −1 2
                                                                  )
                                                           PQuantization df ⎟
                                                                            ⎟
                                                                                             )                              ⎜
                                                                                                                            ⎜
                                                                                                                                          ⎛ σ ⎞
                                                                                                                                          ⎜ j ⎟
                                                                                                                                        4 ⎜
                                                                                                                                                   2
                                                                                                                                                                                 ⎟
                                                                                                                                                                                 ⎟
                                     ⎝ BW                                  ⎠                                              ⎜
                                                                                                                            ⎜            ⎜ T ⎟
                                                                                                                                                ⎟                               ⎟
                                                                                                                                                                                 ⎟
                                                                                                                            ⎝            ⎝ s ⎠                                ⎠
J. Silva-Martinez                                                                                                                                                                     - 87 -
 TAMU-ECE                                                                                                                                                        Barcelona, 2012


       Continuous-Time ΣΔ ADC: Jitter & Blockers
                                                                                                                      0       f0                fck                          f
                                                                                                                                                         Qn            fck
                                                                                                                 CLK
RF clock filtering is an           0    f0            fck                   0    f0                fck
effective method to                    Vin          + S        LPF(s)                                           Sampler                 Hold             S
partially overcome                                   -                                Quantization                                                      2-bit
                                                                                                                                                                         Data
                                                                                       and Jitter                                                                        out
this issue!                                                                                                                                           Quantizer


J Silva et.al., SRC                                         Multi-bit
                                                                        0       f0                fck
                                                                                                            S
                                                                                                                      0       f0               fck
                                                                                                                                                       Z-1
report Dec 2010                                              DAC
                                                                                                                       1-Z-1
                                                                 Jitter induced noise
                                                                                                                                               f0
                                                                                                                                   Jn
                                                                        f0                  fck                           X
                                                                                                                                           0                     fck


Ø  High frequency blockers convolve with Jn and are folded back in band.
                                             ⎛                                                                                                                                          ⎞
                                             ⎜                                                                                                                                          ⎟
Ø  Considering                              ⎜                                                                 Pin                                                                      ⎟
                      SJNR ≅ 10 log 10       ⎜                                                                                                                                          ⎟
                                                                                      2                                                                      2
   Pblocker and
                                             ⎜
                                             ⎜
                                                     ⎛ 2        (
                                                   ∫ ⎜ J n ⊗ 1− Z
                                                                   −1
                                                                                      )   PQuantization + J n 2 ⊗ 1− Z −1                 (                  )    PBloc ker        ⎞ df ⎟
                                                                                                                                                                                   ⎟ ⎟
                                             ⎝   BW ⎝                                                                                                                            ⎠ ⎠

   Pquantization                                                              ⎛ J 2 ⊗ 1− Z −1 2 P
                                                                 ⎛
                                                                 ⎜       ∫ ⎜ n                            (
                                                                                                            ⎞ df
                                                                                                   Bloc ker ⎟
                                                                                                                              )                                    ⎞
                                                                                                                                                                   ⎟
                                                                 ⎜      BW ⎝                              ⎠                                                     ⎟
                         = SJNR no Bloc ker − 10 log 10          ⎜ 1+                                                                                             ⎟
                                                                 ⎜        ⎛ J 2 ⊗ 1− Z −1 2 P         (      ⎞ df      )                                        ⎟
                                                                 ⎜     ∫ ⎜ n
                                                                           ⎝                    Quantization ⎟
                                                                                                               ⎠                                                  ⎟
J. Silva-Martinez
                                                                 ⎝    BW                                                                                          ⎠            - 88 -
 TAMU-ECE                                                                                                         Barcelona, 2012


        Effect of clock jitter on SNR:                                                     STF*Blockers
                                                                                           + NTF*Vq
        Quantization noise +Blockers
                                                            Δt ( n )
     e j ( n ) = (V out ( n ) − V out ( n − 1) )
                                                               T


     E j ( Z ) = 1− Z −1{(            )(V   out   ( Z ) )}⊗ ( J ( Z ) )
                                                                                                                                       f
     E j ( Z ) = 1− Z {(     )STF * V
                                 −1
                                                    in   ( Z )}⊗ J ( Z ) +                                                        Jn

                    + {(1− Z ) NTF * V
                                 −1
                                                    q    ( Z )}⊗ ( J ( Z ) )

                             1/ 2OSR                         2                  Clock Phase Noise
     P j ,S ≅ 2∫                            E j (Z ) dθ
                             0
                                                                                                                                           f
                                                                                                                             fs

                    1/ 2 OSR                                                                                           2
P j −inband ≅ 2 ∫
                    0
                                  (1− Z ){(STF (ω )V
                                            −1
                                                                   Bloc ker s (ω ) + NTF (ω )V q (ω ) )⊗ ( J (ω ) )}       d (ωT s         )
J. Silva-Martinez                                                                                                             - 89 -
 TAMU-ECE                                                                                               Barcelona, 2012


          A	
  Ji#er-­‐Tolerant	
  12-­‐Bit	
  ΣΔ	
  Modulator	
  




      SNR>12	
  bits,	
  Power	
  <	
  20mW,	
  BW=	
  20	
  MHz,	
  OSR=10	
  
      Challenges:	
  	
  
        •  Calibra*on	
  procedure:	
  NTF	
  will	
  be	
  op*mized	
  through	
  the	
  calibra*on	
  tones	
  
        •  Low-­‐sensi*vity	
  to	
  clock	
  ji#er:	
  Emulated	
  switched-­‐capacitor	
  DACs	
  
        •  Robust	
  against	
  blockers:	
  Feedback	
  based	
  topology	
  
        •  Extremely	
  linear	
  filters:	
  IM3	
  @	
  20	
  MHz	
  <	
  75	
  dB	
  Full	
  scale	
  
J. Silva-Martinez                                                                                               - 90 -
 TAMU-ECE                                                                                                             Barcelona, 2012


            A	
  Ji#er-­‐Tolerant	
  14-­‐Bit	
  ΣΔ	
  Modulator	
  




     Main	
  goal:	
  ENOB≥14	
  bits,	
  SQNR	
  >16	
  bits,	
  Total	
  power	
  <	
  50mW,	
  BW=	
  20	
  MHz,	
  
     OSR=10	
  
                    • 	
  Fully	
  calibrated	
  modulator	
  	
  
                    • 	
  Low-­‐sensi*vity	
  to	
  clock	
  ji#er:	
  clock	
  ji#er	
  as	
  high	
  as	
  10psecs	
  (RMS)	
  
J. Silva-Martinez
                    • 	
  Robust	
  against	
  blockers:	
  5th-­‐order	
  feedback-­‐based	
  topology	
                   - 91 -
 TAMU-ECE                                                                    Barcelona, 2012



 Design Example: 12-bit, 20MHz CT ΔΣ ADC
    System-level Design Considerations


    Design Trade-offs:
   Order of modulator, L          L↑     §  Reduced stability,
                                         §  Less robust to PVT variations
   Oversampling ratio, OSR      OSR↑     Limited by fT of technology
   Quantizer resolution, N        N↑     §  Improved stability
                                         §  Improved clock jitter tolerance
                                         §  More power, area in quantizer
                                         §  Limited by non-linearity of
                                         feedback DAC
   Max. NTF gain, NTFmax        NTFmax §  Reduced stability
                                  ↑    §  More sensitive to clock jitter
   Max. stable amplitude, MSA   MSA↑     L↓, N↑, NTFmax↓

J. Silva-Martinez                                                                    - 92 -
 TAMU-ECE                                                                                      Barcelona, 2012

                    System-level Optimization
 §  Order of modulator (L), and OSR set by target SQNR (~80dB) and
     settling time requirements on 1st integrator stage
                L = 5, OSR = 10         Peak SQNR vs NTF
                                                        max
                                                           , No. of Quantizer levels


Ø Order of modulator (L),
   and OSR set by target                           90

   SQNR (~80dB)                                    88

                                                   86
  Ø  L = 5, OSR = 10
                                                   84
                                  Peak SQNR (dB)
  Ø  A number of tradeoffs                        82

      involved                                     80

                                                   78
  Ø Just picking                                  76

    values is not a                                74

    good approach                                  72
                                                    4
                                                                                                               11
                                                        3.5                                        10

  Ø EDUCATED                                                      3
                                                                       2.5   7
                                                                                 8
                                                                                       9



    GUESSES!                                              NTFmax                     No. of Quantizer levels


J. Silva-Martinez                                                                                         - 93 -
 TAMU-ECE                                                                                                 Barcelona, 2012



                    System-level Optimization
                                                                 Peak SQNR vs Biquad Quality Factors
                                                                        L = 5, OSR = 10, N = 9
Ø Order of modulator
   (L), and OSR set by
   target SQNR (~80dB)
                                             86

                                             84
  Ø High-Q filters give                     82
     you better SQNR        Peak SQNR (dB)
                                             80
     (due to picking in                      78
     the gain; better in-
                                             76
     band noise)
                                             74

                                             72

  Ø Implications on                         70

    filter’s signal                          68
                                              8
                                                                                                                       8
    swing and out-                                     6                                                   6
                                                                4
    of-band noise?                                                     2                  2
                                                                                                  4

                                                                               0   0
                                                  Q1 (ω0 = 18.1MHz)                             Q2 (ω0 = 10.8MHz)



J. Silva-Martinez                                                                                                   - 94 -
 TAMU-ECE                                                                                                   Barcelona, 2012


                    System-level Optimization
                                                   MSA vs NTF          , No. of Quantizer levels
                                                                   max
Ø Maximum Signal
   Amplitude Increase
   with number of levels
   and with small NTF -1
   values              -1.5

                                   -2

  Ø Several tradeoffs
                    -2.5
                       MSA (dB)




    involved          -3

                                  -3.5

                                   -4

                                  -4.5
                                                                                                                 2.5
                                   -5
                                   11
                                                                                                        3
                                         10
                                                      9                                     3.5
                                                                   8
                                                                             7   4
                                                                                                   NTFmax
                                         No. of Quantizer levels


J. Silva-Martinez                                                                                                   - 95 -
 TAMU-ECE                                                                                            Barcelona, 2012

                    System-level Optimization
                                                      NTF         vs Biquad Quality Factors
                                                            max
                                                             L = 5, OSR = 10, N = 9
  Ø High-Q sections
     is synonymous of
     higher NTFmax
     and better in-             3.8

     band NTF
                                3.6



  Ø However, MSA               3.4
                          max




    decreases,
                        NTF




                                3.2

    then it is                   3
    unclear if your
    SQNR is better              2.8
                                  8

    or not                                    6                                                              8
                                                                                                    6
                                                  4
                                                                                         4
                                                        2
                                                                                2
                                  Q (ω = 18.1MHz)                   0   0
                                      1   0                                            Q2 (ω0 = 10.8MHz)



J. Silva-Martinez                                                                                            - 96 -
 TAMU-ECE                                                                                                                                         Barcelona, 2012



         Loop Filter Design Considerations - 2
                                         5TH ORDER CT LOOP FILTER

                                                                                                                                       9-level Quantizer
 IN                       LP1,out                   LP2,out
                                                                                    LP3,out               kLP3                                             OUT
                BIQUAD1 BP               BIQUAD2 BP                INTEG1
                           1,out                   2,out
                                                                                                                                   _
                                                                                                          kLP2


                                                                                                          kBP2
                                                                                                                                          Clock
         DAC1




                                                                                                                            DAC3
                                                                                                                                         Generator
                                                                                                          kLP1


                                                                                                          kBP1

                                                                                                                                           DAC
                                                   DAC Control Signals
                                                                                                                                         Controller




                           Block	
       Order	
   DC Gain         Cut-off                Q	
   IM3	
             SNR	
  
                                                      dB	
       freq. MHz	
                           dB	
        dB	
  

                         BIQUAD1	
         2	
         20	
              18.4	
           3	
          -78	
       74	
  
                         BIQUAD2	
         2	
         20	
              10.8	
           4	
          -60	
       60	
  
                          INTEG1	
         1	
         19	
               3.2	
               -	
      -60	
       60	
  
                            Filter	
       5	
         59	
               20	
                -	
     < -76	
      72	
  

J. Silva-Martinez                                                                                                                                            - 97 -
 TAMU-ECE           Barcelona, 2012




J. Silva-Martinez           - 98 -
 TAMU-ECE           Barcelona, 2012




J. Silva-Martinez           - 99 -
 TAMU-ECE           Barcelona, 2012




J. Silva-Martinez           - 100 -
 TAMU-ECE           Barcelona, 2012




J. Silva-Martinez           - 101 -
 TAMU-ECE           Barcelona, 2012




J. Silva-Martinez           - 102 -
 TAMU-ECE           Barcelona, 2012




J. Silva-Martinez           - 103 -
 TAMU-ECE           Barcelona, 2012




J. Silva-Martinez           - 104 -
 TAMU-ECE                            Barcelona, 2012




                        The DEM is usually
                        slow and may lead to
                        significant loop delay!

                        May require loop
                        compensation



 Nice feature: Robust
 against blockers!
J. Silva-Martinez
                                          105-
                                           - 105
 TAMU-ECE           Barcelona, 2012




J. Silva-Martinez           - 106 -
 TAMU-ECE           Barcelona, 2012




J. Silva-Martinez           - 107 -
 TAMU-ECE           Barcelona, 2012




J. Silva-Martinez           - 108 -
 TAMU-ECE           Barcelona, 2012




J. Silva-Martinez           - 109 -

				
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