# Advantages and Pitfalls of Using Fractional PLLs

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```					                                                      04/09/2003

Using Fractional N PLLs

Dean Banerjee
Senior Wireless Applications Engineer

February 27, 2003

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a020
s //
Bia381

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Overview

• Integer/Fractional N PLL Structural
Differences
– Integer N PLLs
– Fractional N PLLs
• Sigma Delta Fractional N PLLs
• Performance Differences
– Lock Time
– Phase Noise
– Spurs
• Competitive Analysis

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Integer N Example

200 KHz
Output
1/R           φ
Kφ
10 MHz
900.2 MHz
1/50                               VCO
Crystal
Reference

200 KHz

1/N
4501

Integer N PLL Example
In this example, a stable 10 MHz reference signal is divided down by 50 in order to get a
comparison frequency of 200 KHz. The output frequency is divided by 4501. The phase
detector compares the divided down output frequency to the comparison frequency and puts
out corrections until both signals are the same.

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Overview

• Integer/Fractional N PLL Structural
Differences
– Integer N PLLs
– Fractional N PLLs
• Sigma Delta Fractional N PLLs
• Performance Differences
– Lock Time
– Phase Noise
– Spurs
• Competitive Analysis

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Fractional N Example

1000 KHz
Output
1/R            φ
Kφ
10 MHz         1/5                                           900.2 MHz
VCO
Crystal
Reference

1000 KHz

1/N
900 1/5

Fractional N Operation
Note that if one was able to make N in the resolution of 1/5, then the comparison frequency
could be 5 times larger, as shown. In other words, a 1000 KHz reference frequency is used
instead of a 200 KHz reference frequency.

Fractional N Modulus
The fractional N modulus is the denominator in the fraction. In this case, since the fractional
part can be 1/5, 2/5, 3/5, 4/5, or 0, the modulus is 5. Note it is desirable to have a larger
fractional modulus, since it allows a higher comparison frequency.

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Fractional N Implementation
• Uses Fractional N Averaging
900                    First Time
900                    Second Time
900                    Third Time
900                    Fourth Time
901                    Fifth time
900.2                  Average Value
• Although the Average Value is correct,
compensation is necessary to correct
for the instantaneous phase error.

This method is fractional N averaging. It also applies to sigma delta PLLs, which will be
discussed later. Now explaining the phase error is a little more complicated. Consider when
the PLL first divides by 865. Now it was supposed to divide by 865.2, thus the resulting
comparison frequency is too high, and ahead in phase of the desired waveform by 0.2 cycles.
The time delay method therefore adds a 0.2 cycle delay.

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The Need for Compensation
1/R
φ
Kφ

900.2 − 900
ε =
900. 2 MHz

1/N

Desired
Divider
Output

Actual
ε          2ε                3ε          4ε
Divider
Output

0 uS        1 uS        2 uS              3 uS          4 uS   5 uS
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Fractional Compensation
METHOD 2:
Crystal                                    Current Compensation
Reference

1/R                                         Loop                      VCO
φ
Kφ               Filter                    Output
METHOD 1:

∆t
Delay Compensation

Σ           1/N

METHOD 3:
Sigma Delta Compensation

Fractional Spurs
Inherent in a Fractional-N topology is the risk of unwanted Fractional spurs at the output. A
good solution will include a way to minimize or eliminate these spurs so as not to degrade
system performance.

Current Compensation Technique
Philips uses a current compensation technique, which is really a band-aid solution on the output
that is difficult for the user in properly implement. Another problem is that it requires the user to
calibrate the correction currents vs. frequency, and these values can not be optimized over
temperature.

Delay Compensation Technique
The National delay compensation technique will eliminate the root cause of the problem. Since
the root cause is an instantaneous phase error, it seems sensible to try to correct this with an
instantaneous phase delay.

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Overview

• Integer/Fractional N PLL Structural
Differences
– Integer N PLLs
– Fractional N PLLs
• Sigma Delta Fractional N PLLs
• Performance Differences
– Lock Time
– Phase Noise
– Spurs
• Competitive Analysis

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Σ∆ Modulator Compensation

1/R                            Loop                  VCO
φ
Kφ            Filter
Crystal                                                         Output
Reference

Σ         1/N

1st Order Modulator:     0, +1
2nd Order Modulator:   -2, -1, 0, +1
3rd Order Modulator:    -4, -3, ... +2, +3
4th Order Modulator:   -8, …, +7
Nth Order Modulator:   -2^N … 2^N-1

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1 Minute Z Transform Course

X(z) = ∑ n= 0 x(n) • z − n
∞

• Not exactly, but sort of like a discrete
version of the Laplace transform
• z-1 represents 1 clock cycle delay

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This definitely does not do justice to the Z transform, but just understanding
the clock delay part is enough to introduce sigma delta PLLs. Note that n is a discrete integer,
but z is continuous variable. Z transforms find their way into discrete signals and systems.
They can also be used to solve difference equations.
It’s actually more accurate to say that the Z transform of x(n) can be
interpreted as the Fourier transform of x(n)*r^(-n), but this is beyond the scope of this
presentation.

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1st Order Σ∆ Noise Shaping

• Noise Shaping techniques use
sigma-delta modulation
• Based on concepts of oversampling
sigma delta-converters
E(z): Quantization Noise
+
X(z)                           −
z −1              +             Y(z)
Σ               1 − z −1
−                  Σ
+
-

Noise Shaping in Σ∆ Modulator
12

Sigma delta noise shaping is very complicated and hard to explain. If this slide looks Chinese
to you, that’s because it is. In some literature, the big ugly expression with all the z’s is simply
replaced with 1/s. Using s instead of z is much more intuitive, but all the PLL diagrams use the
z format, so that’s the format this presentation follows.

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1st Order Σ∆ Noise Shaping

−
z−1
Y(z) = [X(z) - Y(z) ] •                  + E
1 − z −1
−

Y(z) = X(z) • z -1       + E • (1 - z -1 )
Finite Difference --
Loop Filter will filter.
Time Delay --
Discrete analogy to
Can think of this as a low pass filter.              high pass filter

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For the X(z) term, it is not obvious where the low pass filtering comes from. Actually, this is an
all-pass filter with a time delay. However, by sampling any signal at discrete points in time, this
is a type of low pass filtering. Whether the signal is all-pass or low pass filtered, it doesn’t
change the point that it passes through the loop filter without being attenuated, and the
quantization noise is filtered by the loop filter.

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High Order Σ∆ Modulators

• Increasing the order of a Σ∆ modulator (adding more integrators to the
modulator) enhances the noise shaping effect.
• More Loop Filtering is necessary
– i.e. Loop Filter Order = Sigma Delta Order + 1

Quantization
Noise Power                               3rd Order Σ∆ Modulator

2nd Order Σ∆ Modulator
1st Order Σ∆ Modulator
Unshaped Noise Level
Not to
scale
Fcomp/        Noise Shaping Characteristic curves
2
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So higher order modulators are better, but this pushes more noise out, thus requiring a higher
order filter. This noise that is pushed far out can mix with things and come back as spurs closer
to the carrier, so higher order filters really are necessary. The equation:
Loop Filter Order = Sigma Delta Order + 1
is a consequence of applying the constraint that the noise must degrade at a rate of 20
dB/decade outside the loop bandwidth. For the 1st order modulator, the noise increases at a
rate of 20 dB/decade. Therefore the filter must attenuate at 40 dB/decade. A second order
filter has a pole at 0 and another at T1, therefore it has 40 dB/decade roll-off . For the 3rd
order modulator, the noise increases at a rate of 60 dB/decade. Therefore the filter must
attenuate at 60 dB/decade. The 3rd order filter has a pole at 0 and the poles T1 and T3, and

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3rd Order Modulator Structure

z-1                            z-1
-                               -
Y(z)                 Σ     -                      Σ
-
+                            +

Accumulator                Accumulator             Accumulator
X(z)

Y(z) = X(z) + (1 - z -1 )3 • E
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How to get the equation from this architecture is not obvious to the most casual observer. Just
note that the [1-z^(-1)] term is raised to the power of the sigma delta modulator.

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Σ∆             Filtering Example

40

30

20

10                                                        NSM Stock Price
1st Order Modulator
0                                                        3rd Order Modulator
1

6

11

16

21

26

31

36

41

46

51
-10

-20

-30

• For this example, the National stock price was used to represent the
quantization noise and was high pass filtered through a sigma delta
modulator

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For all the modulators, note that the DC component is eliminated. Comparing
the 3rd order modulator to the 1st, note that it appears to have more higher frequency content.
That is because more of the low frequency components are removed by the 3rd order
modulator than the 1st order modulator.

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Overview

• Integer/Fractional N PLL Structural
Differences
– Integer N PLLs
– Fractional N PLLs
• Sigma Delta Fractional N PLLs
• Performance Differences
– Lock Time
– Phase Noise
– Spurs
• Competitive Analysis

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Theoretical Fractional N Benefits

• Silence -- Improved phase noise
– Noise voltage less ( since it is proportional to N )
– 20 *log(N’/N) THEORETICAL phase noise
improvement
– 10*log(N’/N) ACTUAL phase noise improvement
( because digital phase detectors put out noise
proportional to 10*log(Fcomp) )
• Spurs -- Lower reference spurs
– Since the spurs occur at the comparison
frequency, which is low pass filtered, they will be
lower, given the same loop bandwidth
• Switching -- Better switching times
– Since the SPURS are lower, one can afford to
make the loop bandwidth wider, thus improving the
lock time.

Realize that these are theoretical benefits. In actuality, there are fractional spurs, which can be
worse than integer PLL spurs. Also realize that fractional compensation circuitry can also add
phase noise.

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Phase Noise Potential
Comparison
PN1Hz     -214.0  -213.0   -214.8  -217.8  -207.0  -208.8   -215.0
FcompKnee 15000      1400     1200    1200    1000    4000    10000
MaxKphi-60.01000    4000     4000    4000    1600   16000     1600
KphiKnee    1000    1400     1000      0      50      800     2000
MaxMod -65.0 1       1         1       1      16      128   4000000
Part    LMX2326 LMX2310 LMX2330U LMX2346 LMX2354 LMX2364 LMX247X
1 -70.0 -61.0  -61.7     -63.8   -67.8  -68.8   -79.5    -101.5
5       -68.0  -68.7     -70.8   -74.8  -75.6   -86.0    -101.5
LMX2326
10 -75.0                                                            LMX2310
Phase Noise
-71.0  -71.7     -73.8   -77.8  -78.3   -88.5    -101.5
50      -78.0  -78.5     -80.6   -84.6  -83.3   -92.5    -101.5
100 -80.0-81.0  -81.4     -83.5   -87.5  -84.8   -93.4    -101.5     LMX2330U
500      -87.8  -87.4     -89.3   -93.3  -86.4   -94.3    -101.5
LMX2346
1000      -90.7  -89.4     -91.2   -95.2  -86.6   -94.5    -101.5
-85.0
5000      -96.7  -92.1     -93.7   -97.7  -86.8   -94.6    -101.5     LMX2354
10000      -98.8  -92.6     -94.1   -98.1  -86.8   -94.6    -101.5
-90.0                                                   LMX2364
-95.0                                                   LMX247X

-100.0

-105.0
1   10         100         1000         10000
Channel Spacing (KHz)

19

A common question is how the phase noise of various PLLs compare. This is dependent on
the channel spacing. When the channel spacing is low, fractional parts ( shown in various
shades of blue) outperform integer parts by the most margin. However, when the channel
spacing becomes larger ( > 200 KHz ), then it is not always the case that fractional parts get the
best phase noise. This is because the benefit of raising the phase detector has diminishing
returns. This slide is labeled “Phase Noise Potential”, because it disregards issues with illegal
divide ratios with prescalers and assumes the crystal reference is at least 20 MHz.

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04/09/2003

Spur Comparison
( Typical Charge Pump Leakage)

0.0
-20.0
LMX2326
Spur Level (dBc)    -40.0
LMX2310
-60.0                                        LMX2330U
-80.0                                        LMX2346
-100.0                                        LMX2354
LMX2364
-120.0
LMX247X
-140.0
-160.0
1   10      100       1000   10000
Channel Spacing (KHz)

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At lower channel spacings, the fractional parts outperform integer parts, because the leakage
currents cause excessive spurs. Between 10 KHz and about 300 KHz, some integer PLLs
outperform fractional PLLs. At very high channel spacings, fractional parts again become better
because their spurs roll off faster with channel spacing.

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04/09/2003

Fractional Spur Games

• By avoiding particular fractional
numerators, fractional spurs can be
significantly reduced. This requires good
frequency planning.
• Becomes possible with parts that have high
fractional moduli ( >100) and parts with
higher comparison frequencies.
• Only possible in some particular
applications, like CDMA.

21

In CDMA applications, it is common to use a fractional denominator of 1968. It turns out that
the smallest fractional numerator required is 7 for some frequency plans. As a result, the
fractional spurs are excellent. Some competitors make claims on how great their fractional
spurs are, but this is not really the worst case for the part. In some applications, fractional
spurs can be significantly reduced by good frequency planning.

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Fractional Spur Games

LMX2364 Uncompensated Fractional Spurs vs.
Fractional Numerator

0.0
-18.3                                               -18.8
-20.0                 -28.0                    -28.2
Spur Level

-40.0
-60.0
-80.0
-100.0
0        20           40          60           80      100
FNUM

22

This shows the impact of fractional numerator on spurs. For instance, if you can avoid using a
numerator of 1 or 99, your spurs are reduced about 10 dB.

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04/09/2003

Lock Time

• Fractional N PLLs Allow Wider Loop Bandwidths
for Faster Lock Times
– Maximum Loop Bandwidth is limited to about
1/10th of the comparison frequency in order to
avoid instability due to discrete sampling effects.
– Provided the comparison frequency is < 100 X
loop bandwidth, The lock time is pretty much
dictated by the loop bandwidth of the PLL system
– However, if the comparison frequency is >100X
loop bandwidth, cycle slipping can degrade the
lock time as shown on the next slide.

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The Impact of Cycle Slipping

925

920

915
Frequency (MHz)

910                                                       Analog
Fcomp=200KHz
905
Fcomp=1MHz
900                                                       Fcomp=2MHz

895

890

885
0     500   1000     1500      2000   2500   3000
Time (uS)                               24

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04/09/2003

LMX247X Cycle Slip Reduction Circuitry
Example

No Cycle Slip Reduction
• Peak Time = 561 uS
• Lock Time = 834 uS

With Cycle Slip Reduction
• Peak Time = 151 uS
• Lock Time = 486 uS

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04/09/2003

Fractional N vs. Integer N

– Better Phase Noise
– Potential to play fractional spur games
– Best for applications with narrow channel
spacings
• Pitfalls
– Potential for Cycle Slipping
• Make sure your Fractional N PLL has cycle
slipping reduction circuitry.
– More Difficult to Use

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04/09/2003

Overview

• Integer/Fractional N PLL Structural
Differences
– Integer N PLLs
– Fractional N PLLs
• Sigma Delta Fractional N PLLs
• Performance Differences
– Lock Time
– Phase Noise
– Spurs

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04/09/2003

Accumulator in Z Domain

• X(z) is the input
• Add Previous value to current value
• Transfer Function:
X(z)
Y(z) =
1 − z −1

X(z)                                  Y(z)
Σ
+
-
z −1
−

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04/09/2003

Σ∆ Noise Shaping Concepts

E(z):
Quantization Noise

X(z)                         1                                           Y(z)
Σ                                                    Σ
−
1 − z −1
+
-
z −1
−

29

Sigma delta noise shaping is very complicated and hard to explain. If this slide looks Chinese
to you, that’s because it is. In some literature, the big ugly expression with all the z’s is simply
replaced with 1/s. Using s instead of z is much more intuitive, but all the PLL diagrams use the
z format, so that’s the format this presentation follows.

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04/09/2003

Σ∆ Noise Shaping Equations

Y(z) = [ X(z) - Y(z) ] • 1 + E
Y(z) = X(z) + E • (1 - z -1 )

Finite Difference --
Loop Filter will filter.
Discrete analogy to
high pass filter
Desired Signal

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04/09/2003

Conclusion

• Fractional PLLs provide the most benefit for
applications with narrow channel spacings (<100
KHz)
– Better Spurs
– Better Phase Noise
• Sigma Delta Fractional PLLs deliver excellent
performance
• National’s PLLs Deliver Excellent Performance
– Low Spurs
– Excellent Phase Noise
– Faster lock times due to cycle slip reduction circuitry
and fastlock.

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Description: Advantages and Pitfalls of Using Fractional PLLs