Documents
Resources
Learning Center
Upload
Plans & pricing Sign in
Sign Out

Review of MOSFET

VIEWS: 23 PAGES: 11

									                     EEEB273/EEEB314 Electronics II - BJT and MOSFET Revisited (Part 2)



BJT and MOSFET Revisited (Part 2) – Metal-
Oxide-Semiconductor Field Effect Transistor
MOSFET Characteristics and Properties

Circuit Symbols and Conventions

    N-channel enhancement                                P-channel enhancement
    mode MOSFET (NMOS)                                   mode MOSFET (PMOS)




Figure 1: n-channel and p-channel MOSFET (a) conventional circuit symbol and (b)
                   circuit symbol that will be used in this course.

Basic Principle of Operation

“The voltage between two terminals (G-S) controls the current through the
third terminal (D).”




Figure 2: Cross section of the n-channel MOSFET (a) prior to formation of
inversion layer, (b) equivalent back-to-back diodes between source and drain when
transistor is cut off and (c) cross-section after formation of an electron inversion
layer.


Dr. Ungku Anisa, UNITEN, 2007                                                          1
                     EEEB273/EEEB314 Electronics II - BJT and MOSFET Revisited (Part 2)


Operation of NMOS:
   +ve voltage applied to GATE (G) creates an electric field in the
     underlying p-type substrate. This forces holes down into the substrate
     and attracts electrons towards the surface.
   For zero or small VGS, the SOURCE (S) and DRAIN (D) terminals
     are separated by the p-region (like two back-to-back diodes). Hence,
     no current can flow between S and D.
   For larger VGS, the region near the surface becomes inverted (i.e.
     changes from p-type to n-type) and an n-channel inversion layer is
     created between the S and D terminals. This provides current flow
     from D to S.
   Appreciable channel conduction occurs only when VGS exceeds
     threshold voltage, VTN.

Note: the operation of p-channel device is the same except:
    the hole is the carrier rather than the electron.
    -ve gate bias is required to induce an inversion layer of holes
       (because substrate is of n-type).
    current flows from S to D.
    threshold voltage for p-channel device is denoted as VTP.

In both types of MOSFET, the GATE is electrically isolated from the
channel by the oxide layer, hence IG = 0.

Modes of Operation

There are three modes of operation:

                                   NMOS               PMOS
                             0 < vGS < VTN ,    0 < vSG < VTP ,
          cut off
                             iD = 0             ID = 0
                             vGS > VTN ,        vSG > VTP ,
          nonsaturation
                             vDS < vGS - VTN ,  vSD < vSG + VTP ,
          or triode region
                             iD  0             iD  0
                             vGS > VTN ,        vSG > vTP ,
          saturation                            vSD  vSG + VTP ,
                             vDS  vGS - VTN ,
          region
                             iD  0             iD  0
               Saturation region        for amplifier circuits.


Dr. Ungku Anisa, UNITEN, 2007                                                        2
                           EEEB273/EEEB314 Electronics II - BJT and MOSFET Revisited (Part 2)


    Current-voltage Relationships

                                    NMOS                                   PMOS
Nonsaturation      vDS < vDS (sat)                          vSD < vSD (sat)
   region                       
                   iD  K n 2vGS  VTN vDS  vDS
                                                 2
                                                                      
                                                             i D  K p 2vSG  VTP v SD  v SD
                                                                                              2
                                                                                                   
                   vDS  vDS (sat)                          vDS  vDS (sat)
                                                                                    
 Saturation
                   i D  K n vGS  VTN                    iD  K p vSG  VTP 
                                          2                                        2
   region
 Transition                vDS ( sat)  vGS  VTN                   vSD ( sat)  vSD  VTP
   point
Enhancement
                                    VTN > 0                                VTP < 0
   mode
 Depletion
                                    VTN < 0                                VTP > 0
   mode

    Note:
                   n Cox        '
                                W kn W
       o Kn                        = conduction parameter for n-channel
                       2        L 2 L
            device
                     Cox  W k p W
                                 '

       o Kp                     
                       p
                                     = conduction parameter for p-channel
                       2     L  2 L
            device
       o    n = mobility of electrons
       o    p = mobility of holes
       o    C ox   ox t ox = oxide capacitance per unit area
       o    ox = oxide permittivity
       o    tox = oxide thickness
       o    W = channel width
       o    L = channel length
       o    kn’ = nCox = process conduction parameter (provided by manufacturer
            for a particular process)

            The channel geometry, i.e. width-to-length ratio (W/L), is a variable
            in the design of MOSFETs that can be utilised to produce specific
            current-voltage characteristics in MOSFET circuits.




    Dr. Ungku Anisa, UNITEN, 2007                                                            3
                               EEEB273/EEEB314 Electronics II - BJT and MOSFET Revisited (Part 2)
                                                          Nonsaturation
                                                          region,
          MOSFET Operating Curves                         vDS < vDS (sat)


                     Active
                     region


Cut-off
mode




                                                vGS (V)
                     VTN

          Figure 3: INPUT – OUTPUT        iD vs vGS       Figure 4: IDEAL OUTPUT                iD vs vDS

          Finite Output Resistance

          In an actual MOSFET, the output curve has a finite slope beyond the
          saturation point due to channel length modulation (as vDS > vDS (sat) , the
          point of inversion zero charge moves away from the D terminal causing a
          reduction of channel length).



                                                                            Figure 5: Family of iD vs
                                                                            vDS curves showing the
                                                                            effect of channel length
                                                                            modulation producing a
                                                                            finite output resistance.



                                                                                 is a positive quantity
                                                                                called the channel length
                                                                                modulation parameter.
          This effect is included in the drain current equation:

                                            
                                   i D  K n vGS  VTN  1  v DS 
                                                          2
                                                                            

          Dr. Ungku Anisa, UNITEN, 2007                                                                 4
                     EEEB273/EEEB314 Electronics II - BJT and MOSFET Revisited (Part 2)


                                  1
                         i                                 1    V
Output resistance, ro   C 
                         v                                     A
                         DS                                I DQ I DQ
                                       vGS cons tan t



where IDQ = quiescent drain current. Note VA is analogous to Early
voltage of a BJT.

DC Analysis Of MOSFET Circuits

   o dc biasing of MOSFET amplifiers is required to obtain saturation
     mode of operation

 Step 1:        Assume transistor is biased in the saturation region,
                i.e. VGS > VTN , ID > 0 and VDS  VDS (sat).

 Step 2:        Analyse the circuit using the saturation current-voltage
                relations.
                    o Calculate VG and VGS from the biasing circuit.
                    o Calculate ID.
                    o Perform KVL on D-S (or S-D) loop to find VDS (or
                       VSD).

 Step 3:        Evaluate the resulting bias condition of the transistor. If the
                assumed parameter values in step 1 are valid, then the initial
                assumption is correct. However,
                   o if VGS < VTN, then the transistor is probably cut off, and
                   o if VDS < VDS (sat), the transistor is likely to be biased in
                      nonsaturation region.

 Step 4:        If the initial assumption is proven incorrect, then a new
                assumption must be made and the circuit reanalysed. Step 3
                must then be repeated.




Dr. Ungku Anisa, UNITEN, 2007                                                        5
                      EEEB273/EEEB314 Electronics II - BJT and MOSFET Revisited (Part 2)


Example: DC Analysis of Common-source Circuit
Calculate the ID and VDS. (Note: VTN = 1V and Kn = 0.1mA/V2)




Figure 6: Common-source circuit.




Load Line of Common-source Circuit

                                                                            VDD VDS
                                                     D-S load line: I D       
                                                                            RD   RD




Figure 7: Transistor characteristics, vDS (sat) curve, load line and Q-point for the
NMOS current-source circuit in the previous example.


Dr. Ungku Anisa, UNITEN, 2007                                                          6
                     EEEB273/EEEB314 Electronics II - BJT and MOSFET Revisited (Part 2)


AC Analysis Of MOSFET Circuits

   o In the MOSFET amplifier analysis, superposition theory applies, i.e.
     perform dc and ac analysis separately.

 Step 1:        Analyse with only dc sources present to give the dc or
                quiescent solution. The transistor must be biased in the
                saturation region in order to produce a linear amplifier.

 Step 2:        Replace each element in the circuit with its small-signal
                model, including replacing the transistor by its small-signal
                equivalent model.

                To draw the small-signal model of the amplifier circuit:
                   o Start with the three terminals of the transistor.
                   o Then sketch equivalent circuit between these
                      terminals.
                   o Connect the small-signal model of the remaining
                      circuit elements to the transistor terminals.

 Step 3:        Analyse the small-signal equivalent circuit, setting the dc
                source components equal to zero, to produce the response of
                the circuit to time-varying input signals only.




Dr. Ungku Anisa, UNITEN, 2007                                                        7
                      EEEB273/EEEB314 Electronics II - BJT and MOSFET Revisited (Part 2)


Small-signal Hybrid- Equivalent Circuit of BJT




Figure 8: Small-signal equivalent circuit, including output resistance, for NMOS
transistor.

    transconductance,
           i
      gm  D                     2 K n VGSQ  VTN   2 K n I DQ
           vGS v V constan t
                   GS      GSQ




    small-signal transistor output resistance,
                     1
             i 
       ro   D 
             v                                  
                                                  K n VGSQ  VTN 
                                                                    2 1
                                                                          I 
                                                                              DQ
                                                                                   1

             DS         vGS VGSQ constan t




Note: The small-signal model of a PMOS transistor is the same as in
Figure 8 but with all ac voltage polarities and current directions
reversed. All the parameter equations stated above still apply for the
PMOS transistor.




Dr. Ungku Anisa, UNITEN, 2007                                                           8
                     EEEB273/EEEB314 Electronics II - BJT and MOSFET Revisited (Part 2)


Basic Single Stage MOSFET Amplifiers

Common-source (CS) Amplifier




Figure 9: CS amplifier circuit.            Figure 10: Small-signal equivalent circuit.

Common-source (CS) Amplifier with Source Resistor (ro = )




Figure 12: CS with source resistor         Figure 11: Small-signal equivalent circuit.
amplifier circuit.

                                                       CS Amplifier with Source
                        Basic CS Amplifier
                                                         Resistor (and ro = )
Input resistance,
                                  R1 R2                             R1 R2
Ri
Output                                                                RD
                                  RD ro
resistance, Ro
                                        Ri                       g m RD     RD
Voltage gain, Av    Av   g m RD ro 
                                       R R            Av               
                                        i  si 
                                                                 1  g m RS    RS
Current gain, Ai                     -                                 -


Dr. Ungku Anisa, UNITEN, 2007                                                        9
                     EEEB273/EEEB314 Electronics II - BJT and MOSFET Revisited (Part 2)


Common-drain (CD) Amplifier a.k.a. Source Follower




Figure 13: CD amplifier circuit.            Figure 14: Small-signal equivalent circuit.

Common-gate (CG) Amplifier (and ro = )




  Figure 15: CG amplifier circuit.                Figure 16: Small-signal equivalent circuit.


                                                                      CG Amplifier
                           CD Amplifier
                                                                       (and ro = )
Input
resistance,                       R1 R2                                     1 gm
Ri
Output                       1
resistance,                         RS ro                                    RD
                             gm
Ro
Voltage                  g m RS ro   Ri                                 g m R D R L 
                Av                                1              Av 
gain, Av               1  g m RS ro   Ri  Rsi 
                                                                          1  g m Rsi
                                                                   RD   g m Rsi 
Current                                                            R  R   1  g R  ,
                                                             Ai                      
gain, Ai
                                    -                              D     L       m si 

                                                            Ai 1 if RD >>RL and gmRsi >>1


Dr. Ungku Anisa, UNITEN, 2007                                                          10
                     EEEB273/EEEB314 Electronics II - BJT and MOSFET Revisited (Part 2)


Characteristics of Basic Single Stage MOSFET Amplifiers

           Input         Output                Voltage           Current
                                                                                  Application
       resistance, Ri resistance, Ro           gain, Av          gain, Ai
                                                 High                                Power
CS           RTH                High                                  -
                                              (inverted)                            amplifier
                                                                                     Voltage
CD           RTH                Low         Almost unity              -
                                                                                     buffer
                                             High (non-                              Current
CG          Low                 High                               Unity
                                             inverting)                              buffer




Dr. Ungku Anisa, UNITEN, 2007                                                       11

								
To top