ADCS OF SDR PARAMETERS_ DESIGN CONSIDERATIONS AND IMPLEMENTATIONS

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					               ADCS OF SDR
 PARAMETERS, DESIGN CONSIDERATIONS
       AND IMPLEMENTATIONS
Presented by Spectrum Signal Processing and Intersil Corporation
                          August 2011



                                                 SIMPLY SMARTER™
                            1
Company Overview
           •   Intersil
           •   Headquarters: Milpitas, CA
           •   Solutions: Best-in-class solutions for video processing,
               active cables, and high-speed/high resolution ADCs.
               Intersil strives to provide products that offer Simplicity,
               Innovation, & Intelligence to their customers.




           • Spectrum Signal Processing by Vecima
           • Headquarters: Burnaby, BC
           • Solutions: High-performance data acquisition (RF, analog
             and digital I/O) and reconfigurable signal and video
             processing hardware and systems for ISR (SIGINT, COMINT,
             ELINT), SDR, MILCOM and SATCOM markets. Spectrum is
             part of Vecima Networks Inc.


                           2
Presenters

       Mark Rives, Principal Applications Engineer at Intersil
       Mark is a Principal Applications Engineer at Intersil where he
       supports high speed data converter customers and
       participates in new product definition.


       Edward Kohler, Strategic Marketing Manager at Intersil
       Edward is Intersil’s Strategic Marketing Manager for high
       speed data converters and ADC drivers.



       Tudor Davies, Director of Technology at Spectrum
       Tudor is the Director of Technology at Spectrum, and in this
       role, he defines the architecture of Spectrum’s future
       products and projects.

                            3
Outline

Software Defined Radio (SDR) Overview

ADC Fundamentals and Specifications

How ADC Specifications Impact SDR

Small Form-Factor Real World Implementation

Summary




                         4
The United States RF Spectrum
       9kHz




                            300GHz
                    5
The RF Spectrum in Egypt
       9kHz




                           300GHz
                    6
SDR Overview
Traditional receivers only cover a single channel in a
limited number of bands because they are made with
dedicated hardware for a specific signal or waveform.




A Software Defined Radio (SDR) is a radio where digitizing
the signal allows circuitry previously implemented in
dedicated hardware to be moved into the digital domain.
                           Ideally, an ADC could
         ADC    DSP        directly sample the signal
                           from the antenna.
                           7
SDR Overview (continued)
ADCs do not have infinite dynamic range or infinite input
bandwidth so additional components are still required to
condition the ADC input signal.




After the signal is digitized, software can control the
channel frequency, bandwidth and modulation format.
Placing the ADC as close to the antenna as possible
provides the most flexibility but must be traded off
against performance limitations.

                           8
Outline

Software Defined Radio (SDR) Overview

ADC Fundamentals and Specifications

How ADC Specifications Impact SDR

Small Form-Factor Real World Implementation

Summary




                         9
  ADC Fundamentals
 ADC = Analog to Digital Converter         Performance of the sampling
                                           process is specified by
 The ADC clock (FSAMPLE or FS) sets
 the sample interval                       • Noise – SNR
                                           • Distortion – SFDR, THD, INL
 The sampling process introduces
 side effects

Noisy Analog                                                          23 or 8 Digital
                 Anti-Alias Filter           3-bit ADC                Output Codes
 Input or FIN




                                      10
Signal to Noise Ratio (SNR)
 SNR = the sum of all power except DC, fundamental and the first ten
 harmonics relative to full-scale power (dBFS) or to signal power (dBc)




                   Fundamental = Primary Input Signal or Carrier


                      Harmonics                       Noise Floor – Dominated by
     DC                                               white Gaussian thermal noise




                                      11
   Clock Jitter Reduces SNR
   Clock uncertainty -> Sample time uncertainty
   Result: Output voltage errors
   • The SNR may be dominated by thermal noise or jitter noise
   • The jitter noise is constant relative to the input amplitude
   • A very large signal may cause a small signal to be lost in the noise
   • Lower clock jitter can offer higher sensitivity
Desired signal, constant     Large signal with jitter raises   Jitter noise masks the
amplitude                    the noise floor                   desired signal




                                                                  Jitter Noise
   Thermal Noise                                                  Thermal Noise
   Jitter Noise



                                            12
Distortion (THD, SFDR)
 THD = Total Harmonic Distortion is the sum of power in the first
 ten harmonics relative to the fundamental signal power (dBc)


                Spurious Free Dynamic Range (SFDR)



                                                     H9 – H10 have aliased back
                                                     to the first Nyquist zone

                                                              H10        H9

                  H2
                            H3
                                        H4     H5        H6         H7           H8




                                   13
         Clock Spurs
   0.0
                                               Any signal on the ADC’s clock
 -20.0

 -40.0
                                               input will be convolved (mixed)
 -60.0
                           Clock
                                               with the analog input
 -80.0
                                               • Any spurs or non-harmonic content on
                                                 the clock signal will appear around
-100.0


                                                 every analog input signal and may
-120.0

-140.0
   75.0E+06    125.0E+06           175.0E+06     mask a desired signal
                                                                  Spur masks the
                                                                  desired signal




                                                14
Noise + Distortion Specifications
 SINAD = the sum of all power except DC and the
 fundamental relative to the signal power (dBc)



                              ENOB =
                                     (SINAD − 1.76)
                                          6.02




                         15
Aliasing
All signals sampled by the ADC will be output in the first
Nyquist zone (DC to Fs/2) therefore,
If there are any unwanted signals (including noise) above
Fs/2 they must be filtered prior to sampling
• Unwanted signals above Fs/2 can interfere with desired signals
• Once sampled, the unwanted signals cannot be removed
• The Analog Input (FIN) and Aliased Image (FIMAGE) are identical at the ADC
  output
    Aliased Image (FIMAGE = FS - FIN)         Analog Input (FIN)




                                        TS=
                                        1/fS                              t

                                               16
    Sub-Sampling
We can take advantage of aliasing to sample narrow-band
signals beyond the first Nyquist zone
• All the images will appear in the first Nyquist zone at the ADC output
• Filtering must be used to select the desired image
• Commonly used for Intermediate Frequency (IF) sampling receivers
• A wide ADC input bandwidth enables high-IF sub-sampling
• The signal of interest must fit within a single Nyquist zone

                                                                            192MHz
                                    92MHz   108MHz                                    208MHz
A    8MHz
                                       I         I                             I           I
        Fout                                          Bandpass Filter


                     Fs/2           Fs=100MHz               3*Fs/2                  2*Fs
         First                Second                Third               Fourth
      Nyquist Zone          Nyquist Zone         Nyquist Zone        Nyquist Zone


                                            17
Mixer Example
ADC performance continues to increase but is still limited
at very high frequencies. Mixers are used to translate
signals to a lower frequency where they can be sampled.

                                                                                  -6dB
                                                                                  Amplitude
                                                  Mixer


                         100MHz    ~
                                   RF                           IF
                                                                                              LO
                                                                                              Feedthrough
                                        LO         ~
                         MHz                                                                          MHz
                                              110MHz
  dc   100   200   300                                               dc     100     200        300




                                                                           MHz
                                  dc     100              200        300



                                             18
  Low IF Superheterodyne Receiver
            Filter                         VGA                Mixer            Filter        VGA             Mixer     Filter

                                                                                                                                                                      Digital
                                                                                                                                     ADC
                            LNA                                                                                                                             ADC       Down-
            20MHz                                                              20MHz                                  20MHz          Driver
                                                                                                                                                                     Converter
             BW                                                                 BW                                     BW

        2160-2180MHz                                                     160-180MHz                                  10-30MHz
                                                   Local                                          Local
                                                Oscillator     ~                               Oscillator     ~
                                                             2000MHz                                        150MHz




                            2162MHz                                          162MHz                                             12MHz
          Filter


                                                                                                                                               HD2
                                                                                                                                              24MHz

                                                                                           HD2                                                              HD3
                                                                                         324MHz                                                            36MHz

                                                   MHz                                                       MHz                                                    MHz
         2000        2100         2200   2300                          100        200    300        400                         10        20          30       40




Architecture                   Pros                                                     Cons                                              ADC Requirements
Low-IF                         • Well Understood                                        • Higher BOM count/cost                           • Lower Speed
Superheterodyne                • Excellent Blocker                                      • Limited Flexibility                             • Moderate Performance
                                 Performance                                            • ADC Harmonics are
                               • Perfect I/Q Demodulation                                 In-Band


                                                                                        19
   Zero-IF Receiver
                                                            Quadrature
                                                            Demodulator                 VGA         Filter

                    Filter                           VGA
                                                                                                                         ADC
                                                                                                    10MHz
                                                                                                     LPF
                                      LNA                                                                                            DDC
                    20MHz
                     BW
                                                                                                                         ADC
             2160-2180MHz                                                                           10MHz
                                                                                                     LPF




                                                                            ~
                                                                          2170MHz                            DC
                                    2172MHz                                                                   2MHz




                                                                                                                   HD2
                                                                                                                  4MHz



                                                      MHz                                                                                       MHz
             2000            2100      2200   2300                    -20         -15         -10    -5              5         10   15     20




Architecture                  Pros                                          Cons                                               ADC Requirements
Direct Conversion • Lowest Cost                                             • I/Q Impairments                                  • Dual Channel
Zero-IF (ZIF)     • Moderate ADC                                            • ADC Harmonics are                                • Lower Speed
                                    Requirements                              In-Band                                          • Moderate Performance



                                                                             20
  High-IF Receiver
                   Filter                            VGA            Mixer         Filter

                                                                                                                     Digital
                                                                                           ADC
                                   LNA                                                               ADC             Down-
                  20MHz                                                           20MHz    Driver
                                                                                                                    Converter
                   BW                                                              BW

               2160-2180MHz                                                  160-180MHz
                                                         Local
                                                      Oscillator     ~
                                                                   2000MHz




                                           2162MHz                                                        162MHz




                                                                                                                           HD2
                                                                                                                         324MHz

                                                                   MHz                                                                  MHz
                            2000    2100      2200         2300                                     100       200        300      400




Architecture           Pros                                                  Cons                                    ADC Requirements
High-IF                • Reduced Cost                                        • Faster ADC                            • High Input Bandwidth
IF Sampling            • Perfect I/Q Demodulation                            • Higher Performance                    • Low Jitter
Sub-sampling           • ADC Harmonics are                                     ADC                                   • Good SNR/SFDR/IMD
                         Out-of-Band


                                                                             21
Higher Sample Rate Aids Frequency Planning
Avoid 2nd and 3rd harmonics to increase dynamic range
• Amplifier harmonics may be attenuated with filter but ADC harmonics can not
• Harmonics from either source may be avoided with careful frequency planning
Other Benefits of High Sample Rate
• More spectrum can be processed by a single ADC
• Doubling Fs gives 3dB more SNR in the desired channel
• Anti-aliasing filters are simplified




                                     22
Outline

Software Defined Radio (SDR) Overview

ADC Fundamentals and Specifications

How ADC Specifications Impact SDR

Small Form-Factor Real World Implementation

Summary




                         23
ADC Specifications and SDR

Noise
•Limits the smallest signal that can be digitized
Linearity (Distortion)
•Distortion can mask desired signals
Resolution
•Sets quantization noise limiting ultimate sensitivity
Instantaneous Dynamic Range
•The maximum input level minus the noise and distortion
•Critical for multichannel wideband SDR receivers




                             24
ADC Specifications and SDR (cont’d)

Sample Rate
•High sample rate is closer to an ideal SDR
•High sample rate enables flexible frequency planning
•Can increase SNR in the desired channel
•Trade-off: sample rate vs. resolution
Power Consumption
•Affects battery life
•Affects reliability
•Limits the number of ADCs in high-density systems
•Trade-off: Dynamic range vs. sample rate vs. power
 consumption .



                            25
Design Considerations at System Level

Care and feeding of high-speed ADCs to ensure optimal
performance:
• Sample clock purity
• Frequency Planning - Optimize IF
  frequency & bandwidth with sample rate
• High-quality analog filtering
• Analog and digital design practices
• Power supply
• Chassis




                                                    RF-4902 components:
                                           Physical separation of analog and digital
                                                 sections reduce interference

                                26
Outline

Software Defined Radio (SDR) Overview

ADC Fundamentals and Specifications

How ADC Specifications Impact SDR

Small Form-Factor Real World Implementation

Summary




                         27
    Small Form Factor Real World Implementation

•   Spectrum’s RF-4902 card
    • Digitizes 195 MHz of bandwidth anywhere from 200 MHz to 2.7 GHz
    • 14-bit ADC 490 MSPS
       • Intersil ISLA214P50
    • 16-bit dual DAC 980 MSPS
       • Up to 400 MHz Transmitter analog bandwidth
    • Xilinx Virtex-5 SX95T User FPGA for flexible IF
      signal processing
    • Fast-frequency hopping up to 3000 hops/sec
    • Integrated RF and Digital IF Processing in a single
      3U cPCI slot


                                        28
A Simplified Receiver Enables These Benefits

•   Small footprint
•   Low power
•   High bandwidth
•   High dynamic range
•   Greater flexibility




                          29
RF-4902 Transceiver Block Diagram




                    30
 Digital Down Conversion
                                                 DDC IP provided with the RF-4902:
Digital Down Converter (DDC):
                                                 • Dual phase to handle 490 MSPS ADC
 •Acts as second mixer stage of                    sampling rate
  Superhet                                       • Polyphase filter with fractional re-
 •Performed digitally in FPGA                      sampling
  • NCO replaces Local Oscillator                • Model-based design, using Simulink &
  • Multipliers replace mixer                      Xilinx System Generator
 •Desired frequency converted to                 • User configurable
  baseband (0 Hz)
 •Digital filter(s) to select band(s) of         COMPLEX
                                                                POLYPHASE FILTER
                                                                FRACTIONAL RESAMPLER
  interest                                         NCO
                                                                DECIMATION BY
 •DDC’s Advantages include:                 Fs        COS       2 <= D <= 1024
  • Flexibility                                             I     2X -                I
  • Precision                                                     1024X
                                      14-BIT
                                    500 MSPS          SIN                           Fs/D
                                         ADC
                                                                  2X -
                                                            Q     1024X               Q

                                                                D = 10bits.22bits


                                           31
Outline

Software Defined Radio (SDR) Overview

ADC Fundamentals and Specifications

How ADC Specifications Impact SDR

Small Form-Factor Real World Implementation

Summary




                         32
Summary

Many applications benefit from an SDR with these attributes
• wide instantaneous bandwidth
• high dynamic range
• small size, weight and power
High Speed, high-resolution ADCs help you get there
• Ability to simultaneously monitor more spectrum
• Higher sensitivity
• Adapt to different signal & waveform requirements
• Simplified frequency planning
Software Defined Radios are challenging
• Many conflicting requirements require good design trade-offs
• No single ideal design exists for all cases
• Proven platforms can reduce risk and speed system development


                                   33
Contact Info

                     Thank You for Joining Us!

Spectrum Signal Processing            Intersil
www.spectrumsignal.com                www.intersil.com

                                      Ed Kohler
Tudor Davies                          Product Marketing Manager
Director of Technology                (978) 805-6945
(604) 676-6713
                                      Mark Rives
ADC.webinar@spectrumsignal.com        Applications Engineer
                                      (978) 805-6957

                                      SDR.webinar@intersil.com




                                 34
Questions?




             35

				
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Description: Software Defined Radio (SDR) Overview ADC Fundamentals and Specifications How ADC Specifications Impact SDR Small Form-Factor Real World Implementation Summary