ASP-DAC2013-CFP-CFD_final by xiaopangnv


									                                                                               Call for Papers
                                                                               ASP-DAC 2013
                                                                            Asia and South Pacific Design
                                                                            Automation Conference 2013
                                                                                   January 22-25, 2013
                                                                                    Yokohama, Japan
 Aims of the Conference:
 ASP-DAC 2013 is the eighteenth annual international conference on VLSI design automation in Asia and South Pacific region, one
 of the most active regions of design and fabrication of silicon chips in the world. The conference aims at providing the Asian and
 South Pacific CAD/DA and Design community with opportunities of presenting recent advances and with forums for future
 directions in technologies related to Electronic Design Automation (EDA). The format of the meeting intends to cultivate and
 promote an instructive and productive interchange of ideas among EDA researchers/developers and system/circuit/device designers.
 All scientists, engineers, and students who are interested in theoretical and practical aspects of VLSI design and design automation
 are welcomed to ASP-DAC.
 Areas of Interest:                                                            Paper Submission Deadline:
 Original papers on, but not limited to, the following areas are invited.      July 13, 2012, 5:00 PM JST (UTC +09:00)
 Please note that ASP-DAC will work cooperatively with other
 conferences and symposia in the field to check for double submissions.
 [1] System-Level Modeling and Simulation/Verification:                        package/PCB routing, etc.
      System-level modeling, specification, language,                    [8] Timing, Power, Thermal Analysis and Optimization:
      performance analysis, system-level                                       Deterministic and statistical static timing analysis,
      simulation/verification, hardware-software                               statistical performance analysis and optimization, low
      co-simulation/co-verification, etc.                                      power design, power and leakage analysis, power/ground
 [2] System-Level Synthesis and Optimization:                                  and package analysis and optimization, thermal analysis,
      System-on-chip and multi-processor SoC (MPSoC)                           etc.
      design methodology, hardware-software partitioning,                [9] Signal/Power Integrity, Interconnect/Device/Circuit
      hardware-software co-design, IP/platform-based design,                   Modeling and Simulation:
      application-specific instruction-set processor (ASIP)                    Signal/power integrity, clock and bus analysis,
      synthesis, low power system design, etc.                                 interconnect and substrate modeling/extraction, package
 [3] System-Level Memory/Communication Design and                              modeling, device modeling/simulation, circuit simulation,
      Networks on Chip:                                                        high-frequency and electromagnetic simulation of circuits,
      Communication-based architecture design,                                 etc.
      network-on-chip (NoC) design methodologies and CAD,                [10] Design for Manufacturability/Yield and Statistical
      interface synthesis, system communication architecture,                  Design:
      memory architecture, low power communication design,                     DFM, DFY, CAD support for OPC and RET, variability
      etc.                                                                     analysis, yield analysis and optimization, reliability
 [4] Embedded and Real-Time Systems:                                           analysis, design for resilience and robustness, cell library
      Embedded system design, real-time system design, OS,                     design, design fabrics, etc.
      middleware, compilation techniques, memory/cache                   [11] Test and Design for Testability:
      optimization, interfacing and software issues.                           Testable design, fault modeling, ATPG, BIST and DFT,
 [5] High-Level/Behavioral/Logic Synthesis and                                 memory test and repair, core and system test, delay test,
      Optimization:                                                            analog and mixed signal test.
      High-Level/behavioral/RTL synthesis,                               [12] Analog, RF and Mixed Signal Design and CAD:
      technology-independent optimization, technology                          Analog/RF synthesis, analog layout, verification and
      mapping, interaction between logic design and layout,                    simulation techniques, noise analysis, mixed-signal
      sequential and asynchronous logic synthesis, resource                    design considerations.
      scheduling, allocation, and synthesis.                             [13] Emerging Technologies and Applications
 [6] Validation and Verification for Behavioral/Logic                      i. Design case studies for emerging applications:
      Design:                                                                  multimedia, consumer electronics, communication,
      Logic simulation, symbolic simulation, formal                            networking, ubiquitous computing and biomedical
      verification, equivalence checking, transaction-level/RTL                applications, etc.
      and gate-level modeling and validation, assertion-based              ii. Post CMOS technologies: nanotechnology, quantum,
      verification, coverage-analysis, constrained-random                      optical interconnect, 3D integration, probabilistic
      testbench generation.                                                    architecture, emerging memory technologies,
 [7] Physical Design:                                                          microfluidics, molecular, bioelectronics, etc., with
      Floorplanning, partitioning, placement, buffer insertion,                emphasis on modeling, analysis, novel circuit/architecture,
      routing, interconnect planning, clock network synthesis,                 CAD tools, and design methodologies.
      post-placement optimization, layout verification,

 ASP-DAC 2013 University LSI Design Contest encourages submitting original papers on LSI design and implementation at
 universities and other educational organizations.
Submission of Papers:
 Deadline for submission:      5 PM JST (UTC+9)   July 13 (Fri.), 2012               Specification of the paper submission format
 Notification of acceptance:                      Sept.12 (Wed.), 2012               will be available at the WEB site:
 Deadline for final version:   5 PM JST (UTC+9)   Nov. 14 (Wed.), 2012     

 Panels, Special Sessions and Tutorials:                                ASP-DAC2013 Chairs:
 Suggestions and proposals are welcome and have to be                   General Chair: Shinji Kimura (Waseda Univ.)
 addressed to the Conference Secretariat                                Technical Program Chair: Yuan Xie (Pennsylvania State Univ.)
 (e-mail: no later than June
 4 (Mon.), 2012.                                                        Contact:
 Prospective Sponsors:                                                  Conference Secretariat:
 ACM SIGDA, IEEE CASS, IEICE ESS, IPSJ SIG-SLDM                         TPC Secretariat:
Call for Designs
University LSI Design Contest
ASP-DAC 2013
January 22-25, 2013
Yokohama, Japan

Aims of the Contest:

As a unique feature of ASP-DAC 2013, the University LSI Design Contest will be held. The aim of the Contest is to
encourage education and research on VLSI design at universities and other educational organizations. We solicit designs
that fit in one or more of the following categories:

    (1) Designed, and actually implemented on chips in universities or other educational organizations during the last two
    (2) Designs that report actual measurements from implementations;
    (3) Innovative design prototypes.

Interesting or excellent designs selected will be honored by providing the opportunities for presentation in a special
session at the conference. Award(s) will be given to a few numbers of outstanding designs, selected from those presented
at the conference.

Areas of Design:

Application areas or types of circuits of the original LSI circuit designs include (but are not limited to):
    (1) Analog, RF and Mixed-Signal Circuits, (2) Digital Signal Processing, (3) Microprocessors, (4) Custom ASIC.
Methods or technology used for implementation include:
    (a) Full Custom and Cell-Based LSIs, (b) Gate Arrays, (c) FPGA/PLDs.

Submission of Design Descriptions:

A camera-ready summary is requested to be prepared within 2 pages including figures, tables, and references. It is
strongly recommended that measured experimental results and a chip micrograph are included in the original LSI circuit
design. Please do not submit the same paper as a regular paper.

Specification of the submission format will be available at

                       Deadline for summary:                5PM JST (UTC+9) July 13 (Fri.), 2012
                       Notification of acceptance:          Sep. 12 (Wed.), 2012
                       Deadline for camera-ready:           5PM JST (UTC+9) Nov. 14 (Wed.), 2012


Submitted designs will be reviewed by the Design Contest Committee in a process similar to the review process for the
technical papers. The following criteria will be applied in the selection of designs:
     (1) Reliability of design and implementation, (2) Quality of implementation, (3) Performance of the design,
     (4) Novelty of application, algorithm, architecture, (5) Others.
Interesting or excellent designs selected will be presented at a special session of the conference.


An author of each selected design will be required to make a short presentation at a special session of ASP-DAC 2013.
A digest of each design to be presented will be included in the conference proceedings.

Contact Email:

ASP-DAC 2013 Chairs

     General Chair:                       Shinji Kimura (Waseda University)
     Technical Program Chair:             Yuan Xie (Pennsylvania State University)
     Design Contest Co-Chairs:            Tetsuo Hironaka (Hiroshima City University)
                                          Hiroshi Kawaguchi (Kobe University)

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