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Performance of an IF sampling ADC in receiver applications David Buchanan Staff Applications Engineer Analog Devices, Inc. Introduction list of possible frequencies by considering real world limita- The concept of direct intermediate frequency (IF) sampling is tions, such as the bandwidth of the analog source, or the band- not a new one. In fact many modern receiver designs employ width of the ADC’s analog input circuit2. Another helpful con- this architecture. Performance of commercially available ana- cept is to divide the unfiltered analog input spectrum into log to digital converters (ADC) , however, often eliminates this Nyquist zones. As defined in Figure 3, a signal at frequency architecture due to dynamic performance limitations. This pa- fanalog in an odd Nyquist zone N will alias to fanalog’= fanalog - (N- per explores the concept of direct IF sampling and ADC perfor- 1)fs/2 . Even Nyquist zone frequencies will alias to fanalog’ = mance characteristics which designers should consider in this (N)fs/2 - fanalog. application, and highlights the performance of a new 12 bit, 125Msps ADC design optimized for this application. Basics of Direct IF Sampling The Nyquist sampling theorem, as traditionally interpreted, requires that the sampling rate (fs) of an ADC be at least twice the highest frequency component in the waveform being sampled to recover or accurately represent the original waveform.1 This is often referred to as baseband sampling. To meet this requirement, the analog signal must be low pass filtered before being sampled. In Figure 1, f2 is filtered to meet the Nyquist criteria. If you examined the frequency content of the Figure 2. Aliasing in the time domain. ADC output data with a fast Fourier transform (FFT), the desired signal (f1) would be represented within the accuracy of the ADC. Figure 3. Dividing the analog input spectrum into Myquist zones. Figure 1. Traditional Interpretation of Nyquist Sampling Theorem Without the low pass filter to guarantee the Nyquist sam- Figure 4 illustrates how frequencies are aliased in the fre- pling theorem is met, aliasing may occur. Aliasing is a term quency domain, with f2 and f3 being aliased to f2' and f3'. used to describe frequency content in the ADC output spec- The traditional interpretation of the Nyquist sampling theo- trum caused by under-sampling signals (fanalog>fs/2). If you re- rem is not completely accurate, in that it limits the absolute construct the samples of an under sampled frequency, it will frequency of the waveform being sampled to be less than 1/2 always alias to a baseband frequency as shown in Figure 2. the sampling frequency. In fact it is the bandwidth of the wave- Alias is an appropriate term because the actual analog input form that must be limited, and not the actual frequency.3* In IF frequency which has been aliased to fanalog’ could theoretically under-sampling applications, a band-pass filter limits the be generated from any frequency Nfs (fanalog’, where N is an inte- ger. In practice, fanalog can always be narrowed to a more finite * Also known as the Shannon sampling theorem. International IC – China • Conference Proceedings 63 output spectrum to a particular Nyquist zone, and in effect takes advantage of the aliasing affect. Figure 6. Traditional Super Heterodyne Digital Receiver. Figure 4. Aliasing occurs when the conditions of the Nyquist Sampling Theorem are not met. Figure 7. IF Sampling Digital Receiver. Figure 8. Multi Carrier IF Sampling Receiver Figure 5. Bandpass or IF Under-Sampling ADC Performance Considerations IF vs. Baseband Sampling While ADC technology has improved significantly over time, Many modern receivers take advantage of digital signal pro- only a few can provide the performance needed for IF sampling cessing, but most rely on traditional super heterodyne architec- applications. Even fewer guarantee performance specifications tures to translate the signal of interest to a base band IF before for under-sampling applications. This puts the burden on de- the signal is sampled (base band sampling). Direct IF receivers signers to understand the specifications and characteristics of take advantage of under-sampling to eliminate one or more of the ADC. This section will highlight some of the more impor- the tuned analog IF stages. The ADC acts like a mixer, trans- tant dynamic performance characteristics designers should con- lating the signal to base band for digital processing. Depend- sider when selecting an ADC for IF sampling. It also offers ing on system performance, each IF stage eliminated has the examples of performance data for the AD9433, a new 12 bit, potential to reduce system cost by $10 to $100. 125 Msps ADC from Analog Devices, Inc., which is targeted at The eliminated IF stages are replaced by digital Receive this application. Signal Processors (RSPs). These specialized devices take ad- As discussed above, the minimum sample rate of an ADC vantage of low cost VLSI solutions for filtering, frequency trans- must be twice the signal of interest. However, a higher sample lation, error correction, and demodulation. In addition to sys- rate is often instrumental in reducing the required selectivity , tem cost reduction, these RSPs eliminate the many of the sensi- and therefore the cost and complexity, of the analog anti-aliasing tivities of analog solutions, such as device matching, phase noise, filter. By frequency planning so that the signal of interest is not environmental sensitivity, and performance variation over time. near the boundaries of the Nyquist zones, the selectivity of the If the ADC can maintain the required performance level over band pass filter is relaxed. Since IF components, such as sur- a wide bandwidth, it may be possible to implement a multi car- face acoustic wave (SAW) filters, are only available at limited rier receiver. In this architecture, a single ADC samples mul- number of frequencies, it is not practical to design receivers tiple signal channels, which are then separated and with arbitrary IFs. Alternatively, increasing the sample rate is demaodulated in parallel in the digital domain. This architec- often an easy way to move the IF away from the Nyquist bound- ture compounds the system cost and performance advantage of ary. Relaxing the selectivity of the analog filter may also allow IF sampling by eliminating multiple RF / IF sections. additional noise and adjacent interfering signals into the ADC 64 International IC – China • Conference Proceedings output spectrum. These can be removed by additional filtering that will determine how it distortion performance. Devices with in the digital domain. large INL errors, or many perturbations in the transfer function There are obvious disadvantages to higher sample rates as will have poor harmonic and spurious distortion performance. well. Like many other components, the highest speed ADCs For instance, a “S” shaped linearity curve will cause the ADC available are leading edge technology, and therefore their cost to have pronounced third harmonic distortion. is higher. Designers will also find that resolution and dynamic In the case of the AD9433, two key features minimize its performance will be degraded as compared to lower speed al- linearity errors. The first is an on board circuit that trims out ternatives. Power dissipation of the converter may also increase DNL errors to –0.25LSBs. During device test, DNL is mea- with sample rate. The cost, performance, and power dissipa- sured and then adjusted by programming registers in the trim tion of other devices in the system (RSPs, drive amplifiers, and circuit. Once optimized, the trim setting is fixed with poly-sili- ADC clock sources) are also impacted by the ADC sample rate. con fuses. An ADC’s performance will also degrade as you increase The second linearity feature optimizes INL errors during the sample rate. This may be due to a variety of factors, but T/ device operation, and is referred to an SFDR (spurious free H settling time is most often the main reason for this degrada- dynamic range) optimization circuit. This circuit shuffles some tion. It may be advantageous to use a sample rate below the of the internal devices that determine the linearity of the ADC rated maximum to insure that system dynamic performance is between each clock cycle, which randomizes the location of not impacted by this effect. Another concern is the added noise the worst DNL errors in the transfer function. This effectively of higher speed digital circuits, which can often degrade the spreads the worst DNL errors over the entire range of the con- performance of nearby analog circuits and the ADC itself. In verter transfer function. To illustrate the effectiveness of this fact, an ADCs own outputs may often degrade its performance. circuit, an AD9433 was intentionally mis-trimmed to exagger- The bandwidth of an ADC can be defined in several ways. ate DNL errors, and then INL was measured with and without One is simply to specify the -3dB bandwidth of the ADC input the SFDR optimization circuit. The results were that the SFDR stage or track and hold circuit. Another is to consider the fre- circuit could reduce the INL error from LSBs to (0.25LSBs. quency at which the spectral power of the ADCs digital output Unless otherwise noted, the SFDR improvement circuit is ac- signal is reduced by 3dB. Perhaps the most stringent definition tive for all AD9433 data presented in this paper. would be the analog frequency for which the ADCs signal to noise ratio (SNR, see below) performance was reduced by 3dB (as compared to it’s base band performance). However it is defined, direct IF sampling receiver applications require the ADC to provide enough bandwidth to allow sampling of com- mon IF frequencies, 70-300MHz. This frequency range is driven by availability of other IF components, such as mixers, ampli- fiers, and SAW filters. Additional bandwidth may be neces- sary in the analog front end for the ADC to meet other dynamic specifications, such as harmonic distortion, but it is important to consider that this extra bandwidth will also allow additional wide band noise to be aliased into the spectrum of the ADC output signal. Designers are cautioned not to assume that an ADC’s dynamic specifications will be constant over its rated bandwidth. The bandwidth of the AD9433 is an extremely wide Figure 9. AD9433 INL without SFDR Optimization Circuit. 750MHz, allowing it to extend other important performance characteristics to IFs as high as 400MHz. One of the more unique features of this ADC is a user configurable input band- width optimization. Control pins on the device allow the user to optimize the performance of the ADC for 3 different input bandwidths: Base band (<100MHz, IF Sampling I (100- 250MHz), and IF Sampling II (>250MHz). The IF Sampling II mode also reduces the differential analog input voltage range from 2Vp-p to 1Vp-p, reducing the drive requirements of the signal source. The transfer function of the ADC is described in terms of its linearity. Differential non-linearity (DNL) is the deviation of any output code from an ideal least significant bit (LSB) step. Manufacturers typically specify the worst short and long code in terms of an ideal LSB. Although it is not specified, the rms value of all the DNL errors in the ADC will determine the amount of quantization noise in the ADCs output spectrum. Figure 10. AD9433 INL With SFDR Optimization Circuit. Integral non-linearity is typically specified as the deviation, in LSBs, of the ADCs transfer function from a best straight line (offset and gain errors are ignored). While the INL specifica- Frequency domain testing and characterization of high speed tion is a good measure of overall dynamic performance, it does ADCs has become standard over the past decade. Most of these not tell the whole story. It is the shape of the linearity curve specifications are measured by performing a FFT on the output International IC – China • Conference Proceedings 65 data. It is important that designers consider test conditions, the output spectrum that are not traceable to the fundamental or such as sample rate, analog input frequency, and analog input its harmonics. They may be due to other frequency sources in amplitude, when interpreting and comparing these specifica- the system which unintendendly couple into the ADCs clock, tions. analog input, power supplies, or reference. Even worse are in- The most common benchmark is SNR. It is usually speci- ter-modulation products between two system frequencies, which fied in dB for a sine wave input, and at rated sample rate. It is may be nearly impossible to identify. In many ADC specifica- defined as the ratio of the rms signal amplitude to the rms value tions, higher order harmonics are often considered spurious fre- of the sum of all other spectral components in the ADC output quency content. spectrum. To give designers a more accurate understanding of Another key specification related to receiver sensitivity is ADC performance, manufacturers typically specify SNR ex- two tone inter modulation distortion. In this test, the analog cluding the harmonics of the fundamental frequency. SNR with input contains two sine wave inputs, f1 and f2. The inter-modu- harmonics, or SINAD (signal to noise and distortion), as well lation distortion products fall at 2f1 - f2, and 2f2 - f1 as illustrated as the relative levels of the individual harmonics (Harmonic in Figure 12. Distortion) and other spurious frequency content (Spurious Free Dynamic Range) are often specified as well. The theoretical SNR of an ADC for a full-scale sine wave input is SNRTheoretical = 6.02N + 1.76dB, where N is the number of bits.4 Based on this, manufactur- ers often specify an Effective Number of Bits (ENOB), calcu- lated from the measured SNR or SINAD based on the follow- ing equation: Figure 12. Diagram Two Tone Inter-modulation Distortion. The last term in the numerator compensates for any reduc- An FFT for the AD9433 illustrates additional higher order tion in the signal amplitude during the test. It is impractical in harmonics and IMD products in Figure 13. production test systems (as well as in receiver applications) to maintain a constant full scale amplitude, so the testing is per- formed with a -0.5 to -1.0dBFS (relative to full scale) input level. Because they can affect overall sensitivity, harmonic and spurious frequency content in the ADC output spectrum are of key importance in receiver applications. It is important to note that these frequencies can be aliases, so they may be difficult to identify. The FFT result in Figure 11 is for the under sampling condition of 100Msps and 140.3MHz, so the fundamental and all harmonics appear as aliased frequencies. Figure 13. AD9433 Two Tone Intermodulation. 100Msps,ƒ1=210.3MHz, ƒ2=211.3Mhz Realizing ADC performance in Systems While it is not possible to give a comprehensive overview of realizing the performance of a high performance ADC such as the AD9433 in the space provided, it is worth mentioning a few key issues. The first is signal conditioning of the analog input circuit. While most real world signals are single ended, most high performance ADCs require a differential analog input sig- nal to realize rated performance. It is also difficult to find cost Figure 11. FFT of AD9433. 100Msps, 140.3MHz effective differential amplifiers at IF frequencies, especially ones that provide the level of performance of the ad9433. A trans- Harmonics may be difficult to recognize in the output spec- former, as configured in can provide cost effective solution to trum, but since the fundamental frequency is known, it possible this problem. to predict where they will fall using the Nyquist zone technique Perhaps the most important consideration in realizing the discussed earlier. Spurious frequencies are technically those in performance of the ADC is the sampling clock. While the 66 International IC – China • Conference Proceedings Figure 14. Using two Transformers for Single Ended to Differential Signal Conversion AD9433 has an integrated clock duty cycle stabilization circuit that will the user to provide input duty cycles from 25-75%, jitter in the clock reference will severely degrade noise perfor- mance at IF frequencies.5 For the test results presented in this paper, a 100MHz sine oscillator from Wenzel Associates was used as configured in Figure 15. Figure 15. Wenzel Sine Oscillator Sample Clock Circuit. Summary The direct IF sampling architecture provides the opportunity to simplify and cost reduce receiver designs when compared with standard super heterodyne architectures. The AD9433, a 12 bit, 125Msps ADC, provides a new level of performance in IF sampling ADC technology. The design innovations of this new device, including an SFDR optimization circuit, will allow de- signers to extend the IF sampling architecture to higher IF fre- quencies, and over wider bandwidth signals. References ( Also known as the Shannon sampling theorem. 1 Robert W. Ramirez. The FFT Fundamentals and Concepts. New Jersey: Prentice-Hall, 1985 2 N. S. Tzannes. Communication and Radar Systems. New Jersey: Prentice-Hall, 1985 3 Walt Kester. High Speed Design Seminar . Massachusetts. Analog Devices, 1990. 4 Rudy Van De Plassche. Integrated Analog To Digital and Digital To Analog Converters. Massachusetts. Kluwer Aca- demic Publishers, 1994. 5 Brad Brannon. Application Note 501: Aperture Uncertainty and ADC System Performance. Massachusetts. Analog De- vices, 2000. Author’s contact details David C. Buchanan, Jr. Analog Devices, Inc. 7910 Triad Center Drive Greensboro, NC 27410 USA Phone: (1-336) 605 4221 Fax: (1-336) 605 4187 E-mail: david.buchanan@analog.com International IC – China • Conference Proceedings 67