# tutorial 4

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```					University of the West Indies
Department of Electrical and Computer Engineering
EE19D Digital Electronics
Tutorial #4

1. Implement the following using only one 4-1 Multiplexer plus as few additional logic gates as
possible.: F(U,V,W,X,Y,Z) = m(1,5,9,13,21,23,29,31,37,45) +d(53,61). Show all working.

2. Implement the function in question 1 using ONLY 4-1 Multiplexers (no extra gates). Implement
the design using the 74153 dual MUX. Show all the connections to this device.

3. Write the VHDL code of the Binary-to-BCD Code Converter of Lab2.

4. The figure below shows an EPROM based 7-segment display for use with a digital voltmeter.
The EPROM input is an 8-bit binary word (W 0-7) generated by an Analog to Digital (A/D)
converter; W 0-7 is connected to A0-7 of the EPROM respectively. This device produces a digital
output code that represents the input analog DC voltage. The EPROM is supposed to generate
a 2-digit BCD number to indicate the actual measured voltage. In this case, the design range is
0 - 2V and the display accuracy is to 1 decimal place. The A/D transfer function can be
assumed to be linear with a 0 V input resulting in the binary code 00 16 and a 2V input resulting
in binary code output FF16.
a) What is an ADC device? (this can be found on the web).
b) Determine the minimum EPROM size required for this application
c) Suggest a suitable commercially available EPROM.
d) Determine suitable EPROM contents for satisfactory operation of the display unit.
e) It is possible for the EPROM to generate the segment data directly. Compare and contrast
this approach with that used in the figure. You should refer to the specifications for the
EPROM suggested above and for the 7447 BCD to 7-segment displays.
Common Anode Displays
MSD
EPROM                                                             LSD

Data
Data In

74LS47                74LS47
a-g
7                 7
a-g
4
D4-7
D0-3      4
Figure Q3

5. Figure Q4 shows an incomplete schematic of an address-decoding scheme used in an
embedded microprocessor application. The scheme uses the 74x138 binary decoder. Recall
that the microprocessor operates by placing a word on its address lines A0-15 to uniquely
connect a single data source or sink to the data bus.

a) What is the function of the CS and OE inputs of the ROM? Why are they necessary?

1
b) The ROM is to be accessed at starting (lowest) address location \$C000 1. What is the
binary form. Are there any address bits that remain unchanged?
c) Complete the design so that the ROM is accessed from address \$C000.
d) Further modify the design so that the microprocessor can now also access a similarly sized
RAM chip at starting address \$4000.

6. For the decoder circuit shown in Figure Q5                                                                                      1/2 74LS139
write a sum of products logic expression for                                                    Y                                   A    Y0
the output M as a function of the inputs                                                                                                 Y1
W,X,Y,EN.                                                                                   X                                       B                             M
Y2
W                                            Y3
G
EN
Figure Q5
7.
a) Your younger brother who likes electronics, came across the circuit diagram of figure Q9.

CA
VCC                                                                                                                 CA
5V                                                                                                                                                    U6
U5

A B C D E FG
A B C D E FG
GND

U1                                    U2

2    1A        1Y   4               7     A          OA   13
5    2A        2Y   7               1     B          OB   12
11   3A        3Y   9               2     C          OC   11
14   4A        4Y   12              6     D          OD   10
OE   9
3    1B                             3     ~LT        OF   15
6    2B                             5     ~RBI       OG   14
10   3B                             4     ~BI/RBO
13   4B                                                        VCC
1 ~A/B                                     74LS47N                     5V
15 ~G

74LS157N
U4B
U3A
74LS125N
V1                                              2   1A          1Y0   4
3   1B          1Y1   5
1kHz                                                            1Y2   6
1   ~1G         1Y3   7
5 V
74LS139N
U4A
74LS125N
GND

Figure Q9: Unknown functional circuit

i.               In order for your brother to analyze the functionalities of the circuit, he needs from
you a description of the 74LS125 and the 74LS47 chips. State briefly the logic
functions of these two chips.

1
No its not an error. The \$ sign is a standard way of indicating that the number that follows is hexadecimal
2
ii.    Draw the equivalent block diagram of the circuit in figure 1. Name clearly its
inputs (data A, B and the other signals) and its outputs that are connected to the
two 7-segment displays.

iii.   Your brother had implemented the above circuit diagram without errors. What are
the numbers being displayed on the two 7-segment LEDs? Explain to your
brother why he is getting two different numbers on the displays, which are
apparently in contradiction with the physical connections.

iv.    In order to verify your statement (b), your brother has reduced the frequency
clock signal to 1 Hz. Explain using the timing diagram of the clock signal, the
behaviors of the two 7-segement LEDs.

v.     By inadvertence your brother burns the rightmost LED of the circuit. You have a
spare LED, which is a common cathode LED. Draw the portion of the circuit that
replaces the burned LED with the common cathode one. You will certainly need
to use also some basic logic gates.

Microprocessor                                        ROM

8
D0-7                                        D0-7
A0                                         A0
A1                                         A1
A2                                         A2
A3                                         A3
A4                                         A4
A5                                         A5
A6                                         A6
A7                                         A7
A8                                         A8
A9                                         A9
A10                                         A10
A11                                         A11
A12                                         A12
A13
A14
A15

OE
CS
OE

3
Figure Q4

4

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