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Programmable_Logic_Devices_-_I

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					Programmable Logic Devices - I
Outline

 Programmable Logic Devices
 PN Diode Operation
    AND Logic Arrays
    OR Logic Arrays
    Two-level AND-OR Arrays

 Programmable Logic Array (PLA)
 Realising Logic Functions with PLAs
Outline

 Programmable Logic Devices
 PN Diode Operation
    AND Logic Arrays
    OR Logic Arrays
    Two-level AND-OR Arrays

 Programmable Logic Array (PLA)
 Realising Logic Functions with PLAs
Programmable Logic Devices (1/4)

 Programmable Logic Devices (PLDs) are IC chips with internal
  logic gates connected by electronic fuses.
 These fuses can be ‘blown’ (by programming) to obtain different
  circuit configurations.
 Semi-customized chips that give high packing density at
  reasonable cost.
 Three classes of PLDs are :
    Programmable Logic Array (PLA)
    Programmable Read Only Memory (PROM)
    Programmable Array Logic (PAL)
Programmable Logic Devices (2/4)

                        Fixed      Fuses       Fused
  Inputs              AND array            programmable   Outputs
                                              OR array

             Programmable Read Only Memory (PROM)


           Fuses        Fused                 Fixed
  Inputs            programmable             OR array     Outputs
                      AND array

                    Programmable Array Logic (PAL)


           Fuses        Fused      Fuses       Fused
  Inputs            programmable           programmable   Outputs
                      AND array               OR array

                   Programmable Logic Array (PLA)
Programmable Logic Devices (3/4)

  “Programming” an array – blowing the fuses.

     A A' B B'                       A A' B B'

                            x1                           x1 = A.B

                            x2                           x2 = A'.B

                            x3                           x3 = A.B'


       (a) Unprogrammed                 (b) Programmed

                 Example of a basic AND array
Programmable Logic Devices (4/4)
 PLDs use diodes. A PN diode is an electronic device formed by
  creating a junction of two types of semi-conductor materials, p
  type and n type.
    Forward-biased: When p side (anode) is more positive than
      n side (cathode), it behaves as a closed switch.
    Reverse-biased: When cathode is more positive than anode,
      it behaves as an open circuit.


             P      N                     +                        -
     Anode               Cathode       Forward-biased (closed circuit)

                                          -                       +
         PN junction diode and
                                              Reverse-biased (open circuit)
         schematic symbol.
Outline

 Programmable Logic Devices
 PN Diode Operation
    AND Logic Arrays
    OR Logic Arrays
    Two-level AND-OR Arrays

 Programmable Logic Array (PLA)
 Realising Logic Functions with PLAs
PN Diode Operation
                       +V                             A                   B
      (a)                                     (d)


            A                    B

      (b)              +V                     (e)   A=0                   B=0



        A=1                      B=1
                       +V                           A=1                   B=1
      (c)                                     (f)


        A=0                      B=0

                   PN diode operation for digital applications.

 (a) With pull-up resistor.                   (d) With pull-down resistor.
 (b) Reverse-biased: diode open; B pulled     (e) Reverse-biased: diode open; B
     up to 1.                                     pulled down to 0.
 (c) Forward-biased: diode shorted, forcing   (f) Forward-biased: diode shorted,
     B to 0.                                      forcing B to 1.
Outline

 Programmable Logic Devices
 PN Diode Operation
    AND Logic Arrays
    OR Logic Arrays
    Two-level AND-OR Arrays

 Programmable Logic Array (PLA)
 Realising Logic Functions with PLAs
AND Logic Arrays
                            +V                                       +V
         (a)                                      (c)


                                  f(A,B,C)                                  f(A,B,C) = 0
               A                   = A.B.C              A=0
               B                                        B=1
               C                                        C=1


                           +V                     (d)                +V
         (b)


                                  f(A,B,C) = 1                              f(A,B,C) = 0
            A=1                                         A=0
            B=1                                         B=0
            C=1                                         C=1


 AND function realised with a diode array.
  (a) Basic configuration.                   (c) One diode shorted, forcing f to 0.
  (b) All diodes open; f pulled up to 1.     (d) Multiple diodes shorted, forcing f to 0.
Outline

 Programmable Logic Devices
 PN Diode Operation
    AND Logic Arrays
    OR Logic Arrays
    Two-level AND-OR Arrays

 Programmable Logic Array (PLA)
 Realising Logic Functions with PLAs
OR Logic Arrays

             (a)        A
                        B
                        C
                                            f(A,B,C) = A+B+C




 (b)   A=0                                         A=1
                                             (c)
       B=0                                         B=0
       C=0                                         C=0
                             f(A,B,C) = 0                      f(A,B,C) = 1




              OR function realised with a diode array.
                   (a) Basic configuration.
                   (b) All diodes open; f pulled up to 0.
                   (c) One diode shorted, forcing f to 1.
Outline

 Programmable Logic Devices
 PN Diode Operation
    AND Logic Arrays
    OR Logic Arrays
    Two-level AND-OR Arrays

 Programmable Logic Array (PLA)
 Realising Logic Functions with PLAs
Two-level AND-OR Arrays
 AND and OR circuits can be interconnected to realise any
  arbitrary switching function.

                Example: f(a,b,c)=a.b.c'+b'.c
Outline

 Programmable Logic Devices
 PN Diode Operation
    AND Logic Arrays
    OR Logic Arrays
    Two-level AND-OR Arrays

 Programmable Logic Array (PLA)
 Realising Logic Functions with PLAs
Programmable Logic Array (PLA)

 Combination of a programmable AND array followed by a
  programmable OR array.
 Example:
  Design a PLA to realise the following three logic functions and
  show the internal connections.
    f1(A,B,C,D,E) = A'.B'.D' + B'.C.D' + A'.B.C.D.E'
    f2(A,B,C,D,E) = A'.B.E + B'.C.D'.E
    f3(A,B,C,D,E) = A'.B'.D' + B'.C'.D'.E + A'.B.C.D
Outline

 Programmable Logic Devices
 PN Diode Operation
    AND Logic Arrays
    OR Logic Arrays
    Two-level AND-OR Arrays

 Programmable Logic Array (PLA)
 Realising Logic Functions with PLAs
Realising Logic Functions with PLAs
                   f1(A,B,C,D,E) = A'.B'.D' + B'.C.D' + A'.B.C.D.E'
                   f2(A,B,C,D,E) = A'.B.E + B'.C.D'.E
                   f3(A,B,C,D,E) = A'.B'.D' + B'.C'.D'.E + A'.B.C.D

     A
                               X            X      X                  X
                                            X      X                  X




                                                                           Programmable
     B




                                                                             AND array
                               X       X                X    X
     C                                 X    X           X             X
                                                             X
     D                                      X                         X
                               X       X                X    X
     E                                             X    X    X
                                            X

                        A'.B'.D' B'.C.D' A'.B.C.D.E'
         Programmable
           OR array




                               X       X    X                                        f1
                                                   X    X                            f2
                               X                             X        X              f3
                               P1      P2   P3     P4   P5   P6       P7
                            A'B'D'        A'BCDE'    B'CD'E        A'BCD
                                     B'CD'      A'BE       B'C'D'E

				
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posted:10/19/2012
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