# programmable_logic

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```					Programmable Logic

55:032 - Introduction to Digital Design   Page 1
Prgrammable Logic Organization
 Pre-fabricated building block of many AND/OR gates (or
NOR, NAND)
 "Personalized" by making or breaking connections among
the gates

Inputs

Dense array of                      Dense array of
AND gates         Product            OR gates
terms

Outputs

Programmable Array Block Diagram for Sum of Products Form

55:032 - Introduction to Digital Design         Page 2
Basic Programmable Logic Organizations

 Depending on which of the AND/OR logic
arrays is programmable, we have three basic
organizations

ORGANIZATION           AND ARRAY              OR ARRAY

PAL                   PROG.                 FIXED

PROM                   FIXED                 PROG.

PLA                   PROG.                 PROG.

55:032 - Introduction to Digital Design       Page 3
PLA Logic Implementation
Key to Success: Shared Product Terms

Equations
F0 = A + B C
Example:    F1 = A C + A B
F2 = B C + A B
F3 = B C + A

Personality Matrix
Input Side:
Product Inputs      Outputs
term
1 = asserted in term
A B C     F0 F 1 F 2 F 3                0 = negated in term
AB    1 1 -      0 1 1 0                      - = does not participate
BC    - 0 1      0 0 0 1         Reuse
0 1 0 0           of      Output Side:
AC    1 - 0
terms
BC    - 0 0      1 0 1 0                      1 = term connected to output
A    1 - -      1 0 0 1                      0 = no connection to output

55:032 - Introduction to Digital Design             Page 4
PLA Logic Implementation
Example Continued - Unprogrammed device
A    B   C
All possible connections are available
before programming

F0    F1    F2    F3

55:032 - Introduction to Digital Design           Page 5
PLA Logic Implementation
Example Continued -          A   B    C
Programmed part                            Unwanted connections are "blown"

AB

BC

AC

BC

A

Note: some array structures
work by making connections
rather than breaking them
F0   F1      F2   F3

55:032 - Introduction to Digital Design             Page 6
PLA Logic Implementation
Alternative representation for                       Unprogrammed device
high fan-in structures

Short-hand notation
so we don't have to
draw all the wires!

X at junction indicates             A B C D
a connection
AB

AB

CD
Notation for implementing
CD
F0 = A B + A B
Programmed device
F1 = C D + C D

AB+AB   CD+CD

55:032 - Introduction to Digital Design                Page 7
PLA Logic Implementation
A B C
Design Example
ABC

Multiple functions of A, B, C                                                A

B
F1 = A B C                                                                C

A
F2 = A + B + C
B
F3 = A B C                                                                C
ABC
F4 = A + B + C
ABC

F5 = A  B  C                                                            ABC

ABC
F6 = A  B  C                                                            ABC

ABC

ABC

F1 F2 F3 F4 F5   F6

55:032 - Introduction to Digital Design                  Page 8
PALs and PLAs
What is difference between Programmable Array Logic (PAL) and
Programmable Logic Array (PLA)?

PAL concept — implemented by Monolithic Memories
AND array is programmable, OR array is fixed at fabrication

A given column of the OR array
the possible product terms

PLA concept — Both AND and OR arrays are programmable

55:032 - Introduction to Digital Design            Page 9
PALs and PLAs

 Of the two organizations the PLA is the most
flexible
 One PLA can implement a huge range of logic
functions
 BUT many pins; large package, higher cost
 PALs are more restricted / you trade number
of OR terms vs number of outputs
 Many device variations needed
 Each device is cheaper than a PLA

55:032 - Introduction to Digital Design   Page 10
PAL Logic Implementation
Design Example: BCD to Gray Code Converter                                      K-maps
Truth Table                         AB
A
AB
A

A   B    C   D   W   X   Y    Z           CD   00      01    11       10       CD   00      01    11        10
0   0    0   0   0   0   0    0               00   0    0     X       1            00   0    1     X        0
0   0    0   1   0   0   0    1
0   0    1   0   0   0   1    1               01   0    1     X       1            01   0    1     X        0
0   0    1   1   0   0   1    0                                            D                                     D
0   1    0   0   0   1   1    0               11   0    1     X       X            11   0    0     X        X
0   1    0   1   1   1   1    0           C                                    C
0   1    1   0   1   0   1    0               10   0    1     X       X            10   0    0     X        X
0   1    1   1   1   0   1    1
1   0    0   0   1   0   0    1                            B                                    B
1   0    0   1   1   0   0    0                        K-map for W                          K-map for X
1   0    1   0   X   X   X    X
1   0    1   1   X   X   X    X
A                                    A
1   1    0   0   X   X   X    X             AB                                   AB
1   1    0   1   X   X   X    X           CD   00      01    11       10       CD   00      01    11        10
1   1    1   0   X   X   X    X               00   0    1     X       0            00   0    0     X        1
1   1    1   1   X   X   X    X
01   0    1     X       0            01   1    0     X        0
Minimized Functions:                                                            D                                     D
11   1    1     X       X            11   0    1     X        X
C                                    C
W=A+BD+BC                                          10   1    1     X       X            10   1    0     X        X
X=BC
Y=B+C                                                           B                                    B
Z=ABCD+BCD+AD+BCD                                           K-map for Y                          K-map for Z

55:032 - Introduction to Digital Design                                       Page 11
PAL Logic Implementation
Programmed PAL:                              A B   C D

A
BD
BC
Minimized Functions:
0
W=A+BD+BC                                                             BC
X=BC                                                                  0
Y=B+C                                                                 0
B
C
0
0
AB C D
BCD
BCD

4 product terms per each OR gate
W       X       Y       Z

55:032 - Introduction to Digital Design                             Page 12
PAL Logic Implementation
Code Converter Discrete Gate Implementation
A                                A
A   1
B       4
C
B                                                D
2                3       W
D
B
C    3
B           2
C                                            D
D                              4      Z
D   1
5
A
B
2            1       X   B
C       1
C    3
D
C
1: 7404 hex inverters
B   2                Y           2,5: 7400 quad 2-input NAND
B       1                                          3: 7410 tri 3-input NAND
4: 7420 dual 4-input NAND

4 SSI Packages vs. 1 PLA/PAL Package!

55:032 - Introduction to Digital Design               Page 13
PLA Logic Implementation
Another Example: Magnitude Comparator                                         A   B   C   D

A                                         A                                            ABCD
AB                                       AB
CD   00      01       11       10        CD   00       01       11       10
ABCD
00   1    0        0       0             00   0     1       1        1
ABCD
01   0    1        0       0             01   1     0       1        1
D                                        D                                   ABCD
11   0    0        1       0             11   1     1       0        1
C                                        C                                                                        AC
10   0    0        0       1             10   1     1       1        0
AC
B                                         B
BD
K-map for EQ                             K-map for NE
BD
A                                         A
AB                                       AB
00      01       11       10             00       01       11       10
ABD
CD                                       CD
00   0    0        0       0             00   0     1        1       1                                        BCD

01   1    0        0       0             01   0     0        1       1                                        ABC
D                                        D
BCD
11   1    1        0       1             11   0     0        0       0
C                                        C
10   1    1        0       0             10   0     0        1       0

B                                        B
EQ NE LT   GT
K-map for LT                             K-map for GT

55:032 - Introduction to Digital Design                          Page 14
Complex Programmable Logic Devices

 Complex PLDs typically combine PAL
combinational logic with FFs
   Organized into logic blocks
   Fixed OR array size
   Combinational or registered output
   Some pins are inputs only
 Usually enough logic for simple counters,
state machines, decoders, etc.
 e.g. 22G10, 20V8, etc.

55:032 - Introduction to Digital Design   Page 15
16V8 CPLD

OLMC (Output Logic
MacroCell) has OR, FF,
output multiplexer and
I/O control logic.

Note that OLMC output is
fed back to input matrix
for use in other OLMCs.

55:032 - Introduction to Digital Design      Page 16
OLMC Structure
OE

CLK

11   T
10   S
01   M
00   U
vcc              X

AC0

AC1(n)

P
O
T
M                                                       O   O
U                                                           M
1   X                                                           U                     I/O(n)
Q             1   X
FROM
AND
ARRAY                                                D    Q

XOR(n)

F   10-
M   11-
FEEDBACK                                             U   0-1
X   0-0

FROM
OUTPUT(m)
CLK       AC1(n)                    OE

55:032 - Introduction to Digital Design                                        Page 17
Field Programmalble Gate Arrays (FPGAs)

 FPGAs have much more logic than CPLDs
 2K to >50M equivalent gates
 Requires different architecture
 FPGAs can be RAM-based or Flash-based
 RAM FPGAs must be programmed at power-on
– External memory needed for programming data
– May be dynamically reconfigured
 Flash FPGAs store program data in non-volitile
memory
– Reprogramming is more difficult
– Holds configuration when power is off

55:032 - Introduction to Digital Design   Page 18
FPGA Structure
 Typical organization in 2-D array
 Configurable logic blocks (CLBs) contain
functional logic
 Combinational functions plus FFs
 Complexity varies by device
 CLB interconnect is either local or long line
 CLBs have connections to local neighbors
 Horizontal and vertical channels use for long distance
 Channel intersections have switch matrix
 IOBs (I/O logic Blocks) connect to pins
 Usually have some additional C.L./FF in block
55:032 - Introduction to Digital Design    Page 19
FPGA Structure
Input/Output            IOB        IOB        IOB        IOB
Block

IOB
IOB
CLB        CLB        CLB        CLB            Switch
Matrix
SM         SM         SM

IOB
IOB

CLB        CLB        CLB        CLB
SM         SM         SM

IOB
IOB

CLB        CLB        CLB        CLB
Configurable               SM         SM         SM
Logic
Block

IOB
IOB

CLB        CLB        CLB        CLB

IOB        IOB        IOB        IOB

55:032 - Introduction to Digital Design           Page 20
FPGA IOB Structure

55:032 - Introduction to Digital Design   Page 21
FPGA CLB Structure

55:032 - Introduction to Digital Design   Page 22

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