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									Microprocessors
           TEE-211
           4(3-0-2)



            TEE-211: Microprocessors
   Department of Electrical Engineering, College of
         Technology, GBPUAT, Pantnagar                1
Evaluation
   First Pre-final                     20 Marks
   Second Pre-final                    20 Marks
   Lab Assignments/Quizzes/Attendance 20 Marks
   Final                               40 Marks
   Total                              100 Marks




                        TEE-211: Microprocessors
               Department of Electrical Engineering, College of
                     Technology, GBPUAT, Pantnagar                2
Book
   Microprocessor Architecture, Programming,
    and Applications with 8085/8080A

    By

    Ramesh S. Gaonkar


                         TEE-211: Microprocessors
                Department of Electrical Engineering, College of
                      Technology, GBPUAT, Pantnagar                3
Microprocessor
   A multipurpose, programmable, logic
    device
                        that
    reads binary instructions from memory
    accepts binary data as inputs
    processes data according to the
    instructions, and
    provides results as output.
                          TEE-211: Microprocessors
                 Department of Electrical Engineering, College of
                       Technology, GBPUAT, Pantnagar                4
Microprocessor
   A miniaturized CPU
   Heart of a computer




                         TEE-211: Microprocessors
                Department of Electrical Engineering, College of
                      Technology, GBPUAT, Pantnagar                5
A typical programmable machine




                    TEE-211: Microprocessors
           Department of Electrical Engineering, College of
                 Technology, GBPUAT, Pantnagar                6
Microprocessor based system

   Three components:
       work together
       interact with each other
            to perform a given task

   Therefore they comprise a system



                                 TEE-211: Microprocessors
                        Department of Electrical Engineering, College of
                              Technology, GBPUAT, Pantnagar                7
Microprocessor based systems
   microcomputer
   microprocessor-based product
                or
    embedded system




                         TEE-211: Microprocessors
                Department of Electrical Engineering, College of
                      Technology, GBPUAT, Pantnagar                8
Microprocessor based system
(with bus architecture)




                   TEE-211: Microprocessors
          Department of Electrical Engineering, College of
                Technology, GBPUAT, Pantnagar                9
Arithmetic/Logic Unit (ALU)
   The area of the microprocessor where
    various computing functions are performed




                          TEE-211: Microprocessors
                 Department of Electrical Engineering, College of
                       Technology, GBPUAT, Pantnagar                10
Computing functions
   Arithmetic operations:
          addition, subtraction etc.

   Logic operations:
          AND, OR, XOR etc.




                                TEE-211: Microprocessors
                       Department of Electrical Engineering, College of
                             Technology, GBPUAT, Pantnagar                11
Register Array
   The area of the microprocessor that
    consists various registers

   Registers: Primarily used to store data
    temporarily during the execution of a
    program


                          TEE-211: Microprocessors
                 Department of Electrical Engineering, College of
                       Technology, GBPUAT, Pantnagar                12
Control Unit
   Provides necessary timing and control
    signals to all the operations

   Controls the flow of data between
    microprocessor, memory and peripherals




                          TEE-211: Microprocessors
                 Department of Electrical Engineering, College of
                       Technology, GBPUAT, Pantnagar                13
Input Device
   Transfers data and instructions from the
    outside world to the microprocessor

   Examples:
       Keyboard
       Mouse
       Teletype
       analog-to-digital converters
                              TEE-211: Microprocessors
                     Department of Electrical Engineering, College of
                           Technology, GBPUAT, Pantnagar                14
Output Device
   Transfers data and instructions from the
    microprocessor to the outside world
   Examples:
       LED
       CRT
       Printer
       magnetic tape


                             TEE-211: Microprocessors
                    Department of Electrical Engineering, College of
                          Technology, GBPUAT, Pantnagar                15
Memory
   Stores binary information
       instruction
       data


   And provides it to the microprocessor
    whenever necessary


                               TEE-211: Microprocessors
                      Department of Electrical Engineering, College of
                            Technology, GBPUAT, Pantnagar                16
Read-Only Memory (ROM)
   Used to store programs that do not need
    alteration
   e.g., monitor program of a single board
    microcomputer
   Monitor program:
          interprets the information entered through a
           keyboard
          and provides equivalent binary digits to the
           microprocessor
                             TEE-211: Microprocessors
                    Department of Electrical Engineering, College of
                          Technology, GBPUAT, Pantnagar                17
Read/ Write Memory (R/WM)
   Random-Access Memory (RAM)

   User memory

   Used to store user programs and data



                           TEE-211: Microprocessors
                  Department of Electrical Engineering, College of
                        Technology, GBPUAT, Pantnagar                18
System Bus
   A communication path between the
    microprocessor and peripherals

   A group of wires to carry bits




                           TEE-211: Microprocessors
                  Department of Electrical Engineering, College of
                        Technology, GBPUAT, Pantnagar                19
Vinytics 8085 Kit




                    TEE-211: Microprocessors
           Department of Electrical Engineering, College of
                 Technology, GBPUAT, Pantnagar                20
Vinytics 8085 Kit




                    TEE-211: Microprocessors
           Department of Electrical Engineering, College of
                 Technology, GBPUAT, Pantnagar                21
Omega 8085 Kit




                   TEE-211: Microprocessors
          Department of Electrical Engineering, College of
                Technology, GBPUAT, Pantnagar                22
How Does A Microprocessor Work?

 Program & data are entered in the R/WM
  through the input device
 Microprocessor is given a command to
  execute the program
 Microprocessor reads and executes
  instructions (one instruction at a time)
 Microprocessor sends the result to the
  output device
                       TEE-211: Microprocessors
              Department of Electrical Engineering, College of
                    Technology, GBPUAT, Pantnagar                23
Microprocessor reads and executes
instructions
    Microprocessor fetches the first instruction
     from memory, decodes it and executes it
    The sequence of fetch, decode and execute
     is continued until the microprocessor comes
     across an instruction to stop




                          TEE-211: Microprocessors
                 Department of Electrical Engineering, College of
                       Technology, GBPUAT, Pantnagar                24
During the entire process

   Microprocessor uses the system bus to
    fetch instructions & data from memory
   Microprocessor uses registers to store data
    temporarily
   Microprocessor uses ALU for computing
   Microprocessor uses the same bus lines to
    send the result to output devices
    (e.g., seven-segment LEDs)
                          TEE-211: Microprocessors
                 Department of Electrical Engineering, College of
                       Technology, GBPUAT, Pantnagar                25
Basic Terminology
   Bit: A binary digit, 0 or 1
   Byte: A group of eight bits
   Nibble: A group of four bits
   Word: A group of bits the computer
    recognizes and processes at a time
   Instruction: A command in binary that is
    recognized and executed by the
    microprocessor to accomplish a task
                          TEE-211: Microprocessors
                 Department of Electrical Engineering, College of
                       Technology, GBPUAT, Pantnagar                26
Basic Terminology
   Mnemonic: A combination of letters to
    suggest the operation of an instruction
   Machine Language: The binary medium of
    communication with a computer through a
    designed set of instructions specific to the
    computer



                          TEE-211: Microprocessors
                 Department of Electrical Engineering, College of
                       Technology, GBPUAT, Pantnagar                27
Basic Terminology
   Assembly Language: A medium of
    communication with a computer in which
    programs are written in mnemonics. It is
    computer-specific.




                          TEE-211: Microprocessors
                 Department of Electrical Engineering, College of
                       Technology, GBPUAT, Pantnagar                28
Basic Terminology
   Low-Level Language: A machine
    dependent medium of communication in
    which programs are written in machine
    language or in assembly language
   High-Level Language: A machine
    independent medium of communication in
    which programs are written in English-like
    words
                          TEE-211: Microprocessors
                 Department of Electrical Engineering, College of
                       Technology, GBPUAT, Pantnagar                29
Basic Terminology
   Compiler: A program that translates a
    high-level language program into machine
    language.
   Interpreter: Same as compiler but
    translates one statement at a time.
   Assembler: A program that translates an
    assembly language program to the binary
    machine language.
                         TEE-211: Microprocessors
                Department of Electrical Engineering, College of
                      Technology, GBPUAT, Pantnagar                30
Basic Terminology
   Monitor Program: A program that
    interprets the input from a keyboard and
    converts the input into its binary equivalent.




                           TEE-211: Microprocessors
                  Department of Electrical Engineering, College of
                        Technology, GBPUAT, Pantnagar                31
The 8085 Programming Model:

                            General Purpose Registers
                            Accumulator or Register A
                            Flag Register
                                   Zero Flag (Z)
                                   Carry Flag (CY)
                                   Sign Flag (S)
                                   Parity Flag (P)
                                   Auxiliary Carry Flag (AC)
                            Program Counter (PC)
                            Stack Pointer (SP)
                  TEE-211: Microprocessors
         Department of Electrical Engineering, College of
               Technology, GBPUAT, Pantnagar                    32
General Purpose Registers:
   8085 has 6 general purpose registers to store 8-bit data.
       B
       C
       D
       E
       H
       L
   They can be combined as register pairs to perform 16-
    bit operations.
       BC
       DE
       HL
                              TEE-211: Microprocessors
                     Department of Electrical Engineering, College of
                           Technology, GBPUAT, Pantnagar                33
Accumulator or Register A:
   An 8-bit register that is part of ALU.

   It is used to store 8-bit data and to perform
    arithmetic and logical operations.

   The result of an operation is stored in
    accumulator.

                           TEE-211: Microprocessors
                  Department of Electrical Engineering, College of
                        Technology, GBPUAT, Pantnagar                34
Flags:
   The ALU includes five flip flops which are
    set or reset after an operation according to
    data conditions of the result.




                           TEE-211: Microprocessors
                  Department of Electrical Engineering, College of
                        Technology, GBPUAT, Pantnagar                35
Flags:
   Zero Flag (Z) – set to 1 when the result is zero,
    otherwise it is reset
   Carry Flag (CY) – set to 1 if an arithmetic operation
    results in a carry
   Sign Flag (S) – set to 1 if bit D7 of the result is 1,
    otherwise it is reset
   Parity Flag (P) - set to 1 if the result has an even
    number of 1s, otherwise it is reset
   Auxiliary Carry Flag (AC) - set to 1 if a carry is
    generated by digit D3 and is passed to digit D4.
                               TEE-211: Microprocessors
                      Department of Electrical Engineering, College of
                            Technology, GBPUAT, Pantnagar                36
Status of Flags after Execution of
an Instruction:
   Data transfer and branch instructions do
    not affect the flags.
   Most of the arithmetic and logical
    operations affect the flags.
   Addition, subtraction & compare operations
    affect all the flags.
   INX and DCX do not affect flags.
   INR and DCR affect all the flags except CY.
                          TEE-211: Microprocessors
                 Department of Electrical Engineering, College of
                       Technology, GBPUAT, Pantnagar                37
Status of Flags after Execution of
an Instruction:
   OR and XOR operations affect S, Z & P
    and reset CY & AC.
   AND operations affect S, Z & P; reset CY;
    and set AC.
   Rotate operations affect only CY.
   STC and CMC do not affect any flag except
    CY.
   DAD does not affect any flag.
                         TEE-211: Microprocessors
                Department of Electrical Engineering, College of
                      Technology, GBPUAT, Pantnagar                38
Program Counter (PC):
   A 16-bit register used to sequence the
    execution of instructions. It points to the
    memory address from which the next byte
    is to be fetched.




                          TEE-211: Microprocessors
                 Department of Electrical Engineering, College of
                       Technology, GBPUAT, Pantnagar                39
Stack Pointer (SP):
   16-bit register used to point a memory
    location in RAM called the stack.




                          TEE-211: Microprocessors
                 Department of Electrical Engineering, College of
                       Technology, GBPUAT, Pantnagar                40
Program for Addition of Two
Numbers:
Mnemonics    Hex Code                                           Description
MVI A,03H    2000 3E                                            Move immediately the
             2001 03                                            hexadecimal data 03 to register
                                                                A (accumulator)
MVI B, 02H   2002 06                                            Move immediately the
             2003 02                                            hexadecimal data 02 to register
                                                                B
ADD B        2004 80                                            Add the contents of register B
                                                                to the contents of accumulator
                                                                and store the result in
                                                                accumulator itself
STA 2200H    2005      32                                       Store the contents of
             2006      00                                       accumulator to the memory
             2007      22                                       location 2200H in the RAM
HLT          2008      76                                       Halt (Stop executing)


                      TEE-211: Microprocessors
             Department of Electrical Engineering, College of
                   Technology, GBPUAT, Pantnagar                                             41
The same task can be performed
without using register B
Mnemonics   Hex Code                                           Description
MVI A,03H   2000 3E                                            Move immediately the
            2001 03                                            hexadecimal data 03 to
                                                               register A (accumulator)
ADI 02H     2002 C6                                            Add immediately the
            2003 02                                            hexadecimal data 02 to the
                                                               contents of accumulator
                                                               and store the result in
                                                               accumulator itself
STA 2200H   2004       32                                      Store the contents of
            2005       00                                      accumulator to the memory
            2006       22                                      location 2200H in the RAM
HLT         2007       76                                      Halt (Stop executing)


                     TEE-211: Microprocessors
            Department of Electrical Engineering, College of
                  Technology, GBPUAT, Pantnagar                                        42
Addition of Two Numbers Stored at
Two Memory Locations
Mnemonics   Hex Code                                       Description
LDA 2100H   2000     3A                                    Load the contents of memory
            2001     00                                    location 2100H to the
            2002     21                                    accumulator
MOV B,A     2003     47                                    Copy the contents of
                                                           accumulator into register B
LDA 2101H   2004     3A                                    Load the contents of memory
            2005     01                                    location 2101H to the
            2006     21                                    accumulator
ADD B       2007     80                                    Add the contents of register B
                                                           to the contents of accumulator
                                                           and store the result in
                                                           accumulator itself
STA 2200H   2008     32                                    Store the contents of
            2009     00                                    accumulator to the memory
            200A     22                                    location 2200H in the RAM
HLT         200B     76                                    Halt (Stop executing)

                     TEE-211: Microprocessors
            Department of Electrical Engineering, College of
                  Technology, GBPUAT, Pantnagar                                         43
Example Program 1:
   Write a program for addition of two
    numbers stored at memory locations
    2100H & 2101H. Store the result at 2200H
    and store 01H at 2201H if a carry is
    generated otherwise store 00H at this
    memory location.


                         TEE-211: Microprocessors
                Department of Electrical Engineering, College of
                      Technology, GBPUAT, Pantnagar                44
Mnemonics   Hex Code                                      Description
LDA 2100H   2000      3A                                  Load the contents of
            2001      00                                  memory location 2100H to
            2002      21                                  the accumulator
MOV B,A     2003      47                                  Copy the contents of
                                                          accumulator into register B
LDA 2101H   2004      3A                                  Load the contents of
            2005      01                                  memory location 2101H to
            2006      21                                  the accumulator
ADD B       2007      80                                  Add the contents of register
                                                          B to the contents of
                                                          accumulator and store the
                                                          result in accumulator itself
STA 2200H   2008 32                                       Store the contents of
            2009 00                                       accumulator to the memory
            200A 22                                       location 2200H in the RAM



                     TEE-211: Microprocessors
            Department of Electrical Engineering, College of
                  Technology, GBPUAT, Pantnagar                                      45
Mnemonics         Hex Code                                      Description
JC SKIP           200B      DA                                  Jump on carry to the
                  200C      14                                  memory location indicated
                  200D      20                                  by the label SKIP
MVI A,00H         200E      3E                                  Move immediately the
                  200F      00                                  hexadecimal data 00 to
                                                                register A (accumulator)
STA 2201H         2010 32                                       Store the contents of
                  2011 01                                       accumulator to the memory
                  2012 22                                       location 2201H in the RAM
HLT               2013 76                                       Halt (Stop executing)
SKIP:MVI A, 01H   2014 3E                                       Move immediately the
                  2015 01                                       hexadecimal data 01 to
                                                                register A (accumulator)
STA 2201H         2016       32                                 Store the contents of
                  2017       01                                 accumulator to the memory
                  2018       22                                 location 2201H in the RAM
HLT               2009       76                                 Halt (Stop executing)

                           TEE-211: Microprocessors
                  Department of Electrical Engineering, College of
                        Technology, GBPUAT, Pantnagar                                   46
Example Program 2:
   Write a program for the multiplication of two
    numbers stored at memory locations
    2100H and 2101H. Store the result at
    2200H. Assume that the result does not
    overflow.




                           TEE-211: Microprocessors
                  Department of Electrical Engineering, College of
                        Technology, GBPUAT, Pantnagar                47
Mnemonics   Hex Code                                       Description
LDA 2100H   2000 3A                                        Load the contents of
            2001 00                                        memory location 2100H
            2002 21                                        (multiplicand) to the
                                                           accumulator
MOV B,A     2003 47                                        Copy the contents of
                                                           accumulator into register
                                                           B
LDA 2101H   2004 3A                                        Load the contents of
            2005 01                                        memory location 2101H
            2006 21                                        (multiplier) to the
                                                           accumulator
MOVC,A      2007 4F                                        Copy the contents of
                                                           accumulator into register
                                                           C
XRA A       2008 AF                                        Clear the accumulator

                     TEE-211: Microprocessors
            Department of Electrical Engineering, College of
                  Technology, GBPUAT, Pantnagar                                    48
Mnemonics     Hex Code                                      Description
NEXT: ADD B   2009 80                                       Add the contents of
                                                            register B to the contents
                                                            of accumulator and store
                                                            the result in accumulator
                                                            itself
DCR C         200A 0D                                       Decrease the contents of
                                                            register C by one
JNZ NEXT      200B        C2                                If zero flag is not set,
              200C        09                                then jump to the label
              200D        20                                NEXT
STA 2200H     200E        32                                Store the contents of
              200F        01                                accumulator to the
              2010        22                                memory location 2200H
                                                            in the RAM
HLT           2011        76                                Halt (Stop executing)



                        TEE-211: Microprocessors
               Department of Electrical Engineering, College of
                     Technology, GBPUAT, Pantnagar                                       49
Example Program 3:
   Write a program for the multiplication of two
    numbers stored at memory locations
    2100H and 2101H. Store the high order
    byte of the result at 2200H and low order
    byte at 2201H.




                           TEE-211: Microprocessors
                  Department of Electrical Engineering, College of
                        Technology, GBPUAT, Pantnagar                50
Mnemonics   Hex Code                                      Description
LDA 2100H   2000 3A                                       Load the contents of
            2001 00                                       memory location 2100H
            2002 21                                       (multiplicand) to the
                                                          accumulator
MOV B,A     2003 47                                       Copy the contents of
                                                          accumulator into register
                                                          B
LDA 2101H   2004 3A                                       Load the contents of
            2005 01                                       memory location 2101H
            2006 21                                       (multiplier) to the
                                                          accumulator
MOVC,A      2007 4F                                       Copy the contents of
                                                          accumulator into register
                                                          C
XRA A       2008 AF                                       Clear the accumulator



                     TEE-211: Microprocessors
            Department of Electrical Engineering, College of
                  Technology, GBPUAT, Pantnagar                                   51
Mnemonics     Hex Code                                      Description
MVI D, 00H    2009 16                                       Clear register D
              200A 00
NEXT: ADD B   200B 80                                       Add the contents of register
                                                            B to the contents of
                                                            accumulator and store the
                                                            result in accumulator itself
JNC SKIP      200C D2                                       If carry flag is not set, then
              200D 10                                       jump to the label SKIP
              200E 20
INR D         200F 14                                       Increase the contents of
                                                            register D by one
SKIP: DCR C   2010 0D                                       Decrease the contents of
                                                            register C by one
JNZ NEXT      2011 C2                                       If zero flag is not set, then
              2012 09                                       jump to the label NEXT
              2013 20



                       TEE-211: Microprocessors
              Department of Electrical Engineering, College of
                    Technology, GBPUAT, Pantnagar                                           52
Mnemonics Hex Code                                        Description
STA 2201H   2014 32                                       Store the contents of
            2015 01                                       accumulator to the memory
            2016 22                                       location 2201H in the RAM
MOV A,D     2017 7A                                       Copy the contents of
                                                          register C to the
                                                          accumulator
STA 2200H   2018 32                                       Store the contents of
            2019 00                                       accumulator to the memory
            201A 22                                       location 2200H in the RAM
HLT         201B 76                                       Halt (Stop executing)




                     TEE-211: Microprocessors
            Department of Electrical Engineering, College of
                  Technology, GBPUAT, Pantnagar                                   53
Example Program 4:
   Write a program for addition of ten numbers
    stored at memory locations 2100H to
    2109H. Store the result at 2200H. Assume
    that the result does not overflow.




                          TEE-211: Microprocessors
                 Department of Electrical Engineering, College of
                       Technology, GBPUAT, Pantnagar                54
Mnemonics      Hex Code                                      Description
XRA A          2000 AF                                       Clear the accumulator to
                                                             store the low order byte
                                                             of the result temporarily
MVI C, 00H     2001 0E                                       Clear register C to store
                                                             the high order byte of the
                                                             result temporarily
MVI B, 0AH     2002 06                                       Move immediately the
               2003 0A                                       hexadecimal data 0A to
                                                             register B (counter)
LXI H, 20FFH   2004        21                                Load the hexadecimal
               2005        00                                data 2100H to the
               2006        21                                register-pair HL
NEXT: INX H    2007        23                                Increase the contents of
                                                             register-pair HL by one




                        TEE-211: Microprocessors
               Department of Electrical Engineering, College of
                     Technology, GBPUAT, Pantnagar                                    55
Mnemonics     Hex Code                                           Description
ADD M         2008          86                                   Add the contents of
                                                                 memory location
                                                                 indicated by the register-
                                                                 pair HL to the
                                                                 accumulator
JNC SKIP      2009        D2                                     If carry flag is not set,
              200A        0D                                     then jump to the label
              200B        20                                     SKIP
INR C         200C        0C                                     Increase the contents of
                                                                 register C by one
SKIP: DCR B   200D 05                                            Decrease the contents of
                                                                 register B by one
JNZ NEXT      200E C2                                            If zero flag is not set,
              200F 07                                            then jump to the label
              2010 20                                            NEXT


                       TEE-211: Microprocessors
              Department of Electrical Engineering, College of
                    Technology, GBPUAT, Pantnagar                                        56
Mnemonics   Hex Code                                      Description
STA 2201H   2011           32                             Store the contents of
            2012           01                             accumulator to the
            2013           22                             memory location
                                                          2201H in the RAM
MOV A,C     2014           79                             Copy the contents of
                                                          register C to the
                                                          accumulator
STA 2200H   2015           32                             Store the contents of
            2016           01                             accumulator to the
            2017           22                             memory location
                                                          2200H in the RAM
HLT         2018           76                             Halt (Stop
                                                          executing)

                     TEE-211: Microprocessors
            Department of Electrical Engineering, College of
                  Technology, GBPUAT, Pantnagar                               57
Example Program 5:
   Write a program for addition of ten numbers
    stored at memory locations 2100H to
    2109H. Store the high order byte of the
    result at 2200H and low order byte at
    2201H.




                          TEE-211: Microprocessors
                 Department of Electrical Engineering, College of
                       Technology, GBPUAT, Pantnagar                58
Mnemonics      Hex Code    Description
XRA A          2000 AF     Clear the accumulator to store the low order byte of the result temporarily

MVI C, 00H     2001 0E     Clear register C to store the high order byte of the result temporarily

MVI B, 0AH     2002 06     Move immediately the hexadecimal data 0A to register B (counter)
               2003 0A
LXI H, 20FFH   2004 21     Load the hexadecimal data 2100H to the register-pair HL
               2005 00
               2006 21
NEXT: INX H    2007   23   Increase the contents of register-pair HL by one
ADD M          2008   86   Add the contents of memory location indicated by the register-pair HL to the
                           accumulator
JNC SKIP       2009 D2     If carry flag is not set, then jump to the label SKIP
               200A 0D
               200B 20
INR C          200C   0C   Increase the contents of register C by one
SKIP: DCR B    200D   05   Decrease the contents of register B by one
JNZ NEXT       200E   C2   If zero flag is not set, then jump to the label NEXT
               200F   07
               2010   20
STA 2201H      2011   32   Store the contents of accumulator to the memory location 2201H in the RAM
               2012   01
               2013   22
MOV A,C        2014   79   Copy the contents of register C to the accumulator
STA 2200H      2015   32   Store the contents of accumulator to the memory location 2200H in the RAM
               2016   00               TEE-211: Microprocessors
               2017   22      Department of Electrical Engineering, College of
                                    Technology, GBPUAT, Pantnagar                                        59
HLT            2018   76   Halt (Stop executing)
Classification of 8085
Instructions:
   One-Byte Instructions:
          MOV, HLT, DCR, INR, DCX, INX, ADD, XRA


   Two-Byte Instructions:
          MVI, ADI


   Three-Byte Instructions:
          STA, JNZ, JNC, LXI

                               TEE-211: Microprocessors
                      Department of Electrical Engineering, College of
                            Technology, GBPUAT, Pantnagar                60
Classification of 8085
Instructions:
   Data Transfer Instructions:
           MOV, MVI
   Arithmetic Instructions:
           ADD, ADI, INR, INX, DCR, DCX
   Logical Instructions:
           XRA
   Branch Instructions:
           JNC, JNZ, JC, JZ
   Machine Control Instructions:
           HLT


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Data Transfer Operations
   These operations simply COPY the data from the
    source to the destination.
   MOV, MVI, LDA, and STA
   They transfer:
       Data between registers.
       Data Byte to a register or memory location.
       Data between a memory location and a register.
       Data between an I\O Device and the accumulator.
   The data in the source is not changed.
Arithmetic Operations
   Addition (ADD, ADI):
            Any 8-bit number.
            The contents of a register.
            The contents of a memory location.
       Can be added to the contents of the accumulator and the
        result is stored in the accumulator.
   Subtraction (SUB, SUI):
            Any 8-bit number
            The contents of a register
            The contents of a memory location
       Can be subtracted from the contents of the accumulator.
        The result is stored in the accumulator.
Arithmetic Operations
   Increment (INR) and Decrement (DCR):
       The 8-bit contents of any memory location or any
        register can be directly incremented or
        decremented by 1.
       No need to disturb the contents of the
        accumulator.
Logic Operations
   These instructions perform logic operations on the contents of the accumulator.
   ANA, ANI, ORA, ORI, XRA and XRI
   Source: Accumulator and
        An 8-bit number
        The contents of a register
        The contents of a memory location
   Destination: Accumulator
          ANA R/M              AND Accumulator With Reg/Mem
          ANI #                AND Accumulator With an 8-bit number

          ORA     R/M          OR Accumulator With Reg/Mem
          ORI     #            OR Accumulator With an 8-bit number

          XRA     R/M          XOR Accumulator With Reg/Mem
          XRI     #            XOR Accumulator With an 8-bit number
Logic Operations
   Cmplement:
       1’s complement of the contents of the
        accumulator.
             CMA No operand
Branch Operations
   Unconditional branch.
       Go to a new location no matter what.
   Conditional branch.
       Go to a new location if the condition is true.
Unconditional Branch
    JMP       Address
         Jump to the address specified (Go to).
    CALL Address
         Jump to the address specified but treat it as a
          subroutine.
    RET
         Return from a subroutine.
    The addresses supplied to all branch operations
     must be 16-bits.
Conditional Branch
   JZ Address        (Jump on Zero)
      Go to address specified if the Zero flag is set.
   JNZ Address       (Jump on NOT Zero)
      Go to address specified if the Zero flag is not set.
   JC Address        (Jump on Carry)
      Go to the address specified if the Carry flag is set.
   JNC Address       (Jump on No Carry)
      Go to the address specified if the Carry flag is not set.
   JP Address        (Jump on Plus)
      Go to the address specified if the Sign flag is not set
   JM Address        (Jump on Minus)
      Go to the address specified if the Sign flag is set.
Machine Control
   HLT
       Stop executing the program.
   NOP
       No operation
       Exactly as it says, do nothing.
       Usually used for delay or to replace instructions
        during debugging.
Addressing Modes:
   The microprocessor has different ways of
    specifying the data for the instruction.
    These are called “addressing modes”.
       Implied Addressing: CMA
       Immediate Addressing: MVI A,05H
       Register Addressing: MOV B,A
       Direct Addressing: OUT 01H; LDA 4000H
       Indirect Addressing: MOV M,A; LDAX B
                            TEE-211: Microprocessors
                   Department of Electrical Engineering, College of
                         Technology, GBPUAT, Pantnagar                71
Examples of Flowcharts:
   Multiplication of Two Numbers
       Result always less than FFH
       Result may also be more than FFH




                             TEE-211: Microprocessors
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                          Technology, GBPUAT, Pantnagar                72
                                  TEE-211: Microprocessors
                         Department of Electrical Engineering, College of
Result always less than FF                            Result may also be more than FFH73
                          H Technology, GBPUAT, Pantnagar
More 8085 Instructions:
   Addition & Subtraction:
            ADD, ADC, ADI, ACI, SUB, SBB, SUI, SBI, DAD
   OR, AND & XOR operations:
            ORA, ORI, ANA, ANI, XRA, XRI
   Rotate operations:
            RAL, RAR, RLC, RRC
   Compare operations:
            CMP, CPI
   Data transfer operations:
            MOV, MVI, LDA, LDAX, LHLD, LXI, STA, STAX
   Jump operations:
            JC, JNC, JZ, JNZ, JP, JM, JPE, JPO

                                      TEE-211: Microprocessors
                             Department of Electrical Engineering, College of
                                   Technology, GBPUAT, Pantnagar                74
Status of Flags after Execution of
an Instruction:
   Data transfer and branch instructions do
    not affect the flags.
   Most of the arithmetic and logical
    operations affect the flags.
   Addition, subtraction & compare operations
    affect all the flags.
   INX and DCX do not affect flags.
   INR and DCR affect all the flags except CY.
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                 Department of Electrical Engineering, College of
                       Technology, GBPUAT, Pantnagar                75
Status of Flags after Execution of
an Instruction:
   OR and XOR operations affect S, Z & P
    and reset CY & AC.
   AND operations affect S, Z & P; reset CY;
    and set AC.
   Rotate operations affect only CY.
   STC and CMC do not affect any flag except
    CY.
   DAD does not affect any flag.
                         TEE-211: Microprocessors
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                      Technology, GBPUAT, Pantnagar                76
Opcode Format:
   Instruction
    = Opcode +Operand


   Opcode : Operation Code


   e.g. “MVI A, 32H” is Instruction
       “MVI” is Opcode
       “A, 32H” Operand
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                         Technology, GBPUAT, Pantnagar                77
Codes of Registers
Code   Registers (R)
000    B
001    C
010    D
011    E
100    H
101    L
110    M
111    A

                      TEE-211: Microprocessors
             Department of Electrical Engineering, College of
                   Technology, GBPUAT, Pantnagar                78
Codes of Register-Pairs
Code   Register-Pairs (Rp)
 00    BC
 10    DE
 10    HL
 11    SP



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           Department of Electrical Engineering, College of
                 Technology, GBPUAT, Pantnagar                79
Opcode Format
  ADD                            10000
  MOV                            01
  ADC                            10001
  ANA                            10100
  ORA                            10110
  XRA                            10101
                   TEE-211: Microprocessors
          Department of Electrical Engineering, College of
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Opcode Format
  DCR R                    00RRR101
  DCX Rp                   00 Rp Rp1011
  INR R                    00RRR100
  INX Rp                   00 Rp Rp0011
  MVI R                    00RRR110
  LDAX BC/DE               000X1011
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          Department of Electrical Engineering, College of
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Opcode Format

   STAX BC/DE                 000X0011
   SBB                        10011
   SUB                        10010
   LXI Rp                     00 Rp Rp0001


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Microprocessor Architecture
and Its Operations:
   Microprocessor-initiated operations

   Internal data operations

   Externally initiated operations



                           TEE-211: Microprocessors
                  Department of Electrical Engineering, College of
                        Technology, GBPUAT, Pantnagar                83
Microprocessor-initiated operations
   Memory read

   Memory write

   I/O read

   I/O write
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                   Department of Electrical Engineering, College of
                         Technology, GBPUAT, Pantnagar                84
Microprocessor-initiated operations
To perform these operations it is required to

    Identify memory location or I/O

    Transfer data

    Provide timing signals
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               Department of Electrical Engineering, College of
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Microprocessor-initiated operations
    For this purpose following communication
    lines (system bus) are required

   Address Bus
   Data Bus
   Control Bus


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Address Bus
   a group of 16 lines

   carry address

   unidirectional

   bits flow from MPU to memory or I/O
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Data Bus
   a group of 8 lines

   carry 8-bit data or instructions

   bidirectional



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Control Bus
   various single lines

   carry timing signals

   e.g. RD, WR, IO/M, ALE



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Internal data operations
   Store 8-bit data (B, C, D, E, H, L)
   Perform arithmetic and logical operations (A,
    ALU)
   Test for conditions (Flag Register)
   Sequence the execution of instructions (PC)
   Store data temporarily in the defined RAM
    called the stack (SP)

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Externally initiated operations
   Reset: PC is cleared, all operations are
    suspended
   Interrupt: MPU is interrupted from normal
    execution, some other instructions initiated
   Ready: MPU enters into a wait state
   Hold: MPU relinquishes control of buses,
    external devices can use buses

                           TEE-211: Microprocessors
                  Department of Electrical Engineering, College of
                        Technology, GBPUAT, Pantnagar                91
An Example to Illustrate the Use
of Buses:




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How does a microprocessor read an
instruction from a memory location?
   Microprocessor places the 16-bit address on the
    address bus.
   The address is decoded by an external logic circuit.
   Memory location is identified.
   Microprocessor sends a pulse called Memory Read as a
    control signal.
   Pulse activates the memory chip.
   Contents of the memory location (8-bit data) are placed
    on the data bus.

                              TEE-211: Microprocessors
                     Department of Electrical Engineering, College of
                           Technology, GBPUAT, Pantnagar                93
Pin Diagram of an 8085
Microprocessor:




                   TEE-211: Microprocessors
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Microprocessor Architecture
Revisited
   Analog and Digital Systems:
       In an analog system, inputs and outputs can
        assume infinite number of possible values within
        the limits,

       Whereas, in a digital system, the inputs and
        outputs can assume a finite number of possible
        values.


                              TEE-211: Microprocessors
                     Department of Electrical Engineering, College of
                           Technology, GBPUAT, Pantnagar                95
Example of a simple digital system
   n- conductors can carry n-bit data




                          TEE-211: Microprocessors
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                       Technology, GBPUAT, Pantnagar                96
AND, NAND, NOR, and OR gates:




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Half Adder:
S = X1X2’+X1’X2 = X1 X2
C = X1X2


X1   X2   S     C
0    0    0     0
0    1    1     0
1    0    1     0
1    1    0     1
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                    Department of Electrical Engineering, College of
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Full Adder:
X1   X2   Cin   S            C

0    0    0     0            0
0    0    1     1            0
0    1    0     1            0
0    1    1     0            1
1    0    0     1            0
1    0    1     0            1
1    1    0     0            1
1    1    1     1            1
                         TEE-211: Microprocessors
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Full Adder:
S = X1’X2’Cin+X1’X2 Cin’+ X1X2’Cin’+X1X2 Cin
  = (X1 X2)Cin’+(X1 X2)’Cin
 = X1X2Cin

C = X1’X2Cin+ X1X2’Cin+ X1X2Cin’+ X1X2Cin
  = (X1 X2)Cin+ X1X2


                        TEE-211: Microprocessors
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Full Adder:




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Tri-State Devices:
   A tri-state logic device has a third line
    called Enable.
   When this line is activated, the tri-state
    device functions the same way as ordinary
    logic devices.
   When the third line is disabled, the logic
    device goes into high impedance state, as
    if it were disconnected from the system.
                          TEE-211: Microprocessors
                 Department of Electrical Engineering, College of
                       Technology, GBPUAT, Pantnagar                102
Tri-State Devices:
   Tri-state logic devices are essential to
    proper functioning of the bus oriented
    system, in which the same bus lines are
    shared by several components.
   These devices have three states:
       logic 1
       logic 0
       high impedance.
                             TEE-211: Microprocessors
                    Department of Electrical Engineering, College of
                          Technology, GBPUAT, Pantnagar                103
Buffer:
   The buffer is a logic circuit that amplifies
    the current or power.

   It has one input line and one output line.

   The logic level of the output is the same as
    that of the input.

                           TEE-211: Microprocessors
                  Department of Electrical Engineering, College of
                        Technology, GBPUAT, Pantnagar                104
Tri-state buffer
   Same as buffer.

   A tri-state buffer has an Enable line also.

   If required, it can be kept in high
    impedance state.


                           TEE-211: Microprocessors
                  Department of Electrical Engineering, College of
                        Technology, GBPUAT, Pantnagar                105
Various Tri-state Devices




                    TEE-211: Microprocessors
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Decoder:
   The decoder is a logic circuit that identifies
    each combination of the signals present at
    its input.




                           TEE-211: Microprocessors
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Microprocessor Architecture
   The microprocessor can be programmed to
    perform functions on given data by writing
    specific instructions into its memory.
   The microprocessor reads one instruction at a
    time, matches it with its instruction set, and
    performs the data manipulation specified.
   The result is either stored back into memory or
    displayed on an output device.

                            TEE-211: Microprocessors
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                         Technology, GBPUAT, Pantnagar                108
The 8085 Architecture
   The 8085 uses three separate busses to
    perform its operations
       The address bus.
       The data bus.
       The control bus.




                            TEE-211: Microprocessors
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The Address Bus
   16 bit wide (A15, A14, A13…A1, A0)
   The 8085 can access 65536 or 64K memory
    locations.
   Unidirectional.
   Information flows out of the microprocessor and into
    the memory or peripherals.
   When the 8085 wants to access a peripheral or a
    memory location, it places the 16-bit address on the
    address bus and then sends the appropriate control
    signals.
                             TEE-211: Microprocessors
                    Department of Electrical Engineering, College of
                          Technology, GBPUAT, Pantnagar                110
The Data Bus
   8 bits wide (D7, D6, D5, D4, D3, D2, D1, D0)
   Bi-directional.
   Information flows both ways between the
    microprocessor and memory or I/O.
   The 8085 uses the data bus to transfer the
    binary information.
   The 8085 can manipulate 8 bits data at-a-
    time.
                           TEE-211: Microprocessors
                  Department of Electrical Engineering, College of
                        Technology, GBPUAT, Pantnagar                111
The Control Bus
 There is no real control bus.
 Instead, the control bus is made up of a
  number of single bit control signals.




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Type of Operations
   Microprocessor Initiated Operations
   Internal Operations
   Peripheral Initiated Operations




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Microprocessor Initiated Operations
   These are operations that the
    microprocessor itself starts.
   These are usually one of 4 operations:
       Memory Read
       Memory Write
       I/O Read (Get data from an input device)
       I/O write (Send data to an output device)


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Microprocessor Initiated Operations
   It is important to note that the microprocessor
    treats memory and I/O devices the same way.
   Input and output devices simply look like
    memory locations to the microprocessor.
   For example, the keyboard may look like
    memory address A3F2H.
   To get what key is being pressed, the
    microprocessor simply reads the data at
    location A3F2H.
                            TEE-211: Microprocessors
                   Department of Electrical Engineering, College of
                         Technology, GBPUAT, Pantnagar                115
Microprocessor Initiated Operations
   The communication process between the
    microprocessor and peripheral devices
    consist of the following three steps:
       Identify the address.
       Transfer the binary information.
       Provide the right timing signals.




                               TEE-211: Microprocessors
                      Department of Electrical Engineering, College of
                            Technology, GBPUAT, Pantnagar                116
The Read Operation
   The microprocessor places the 16-bit address of
    the memory location on the address bus.
   The microprocessor activates a control signal called
    “memory read” which enables the memory chip.
   The memory decodes the address and identifies the
    right location.
   The memory places the contents on the data bus.
   The microprocessor reads the value of the data bus
    after a certain amount of time.
                             TEE-211: Microprocessors
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Internal Data Operations
   The 8085 can perform a number of internal
    operations, such as:
       storing data
       Arithmetic & Logic operations
       Testing for condition
   To perform these operations, the
    microprocessor needs an internal
    architecture.
                              TEE-211: Microprocessors
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                           Technology, GBPUAT, Pantnagar                118
The Internal Architecture
           Accumulator                         Flags
                  B            C
                  D            E
                  H            L
                 Program Counter
                   Stack Pointer

       Address    16                                    Data
                                                   8

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The Program Counter (PC)
   This is a register that is used to control the
    sequencing of the execution of instructions.
   This register always holds the address of
    the next instruction.
   Since it holds an address, it must be 16 bits
    wide.


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                  Department of Electrical Engineering, College of
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The Stack pointer (SP)
   The stack pointer is also a 16-bit register
    that is used to point into memory.
   The memory this register points to is a
    special area called the stack.
   The stack is an area of memory used to
    hold data that will be retreived soon.
   The stack is usually accessed in a Last In
    First Out (LIFO) fashion.
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Externally Initiated Operations
   External devices can initiate (start) one of
    the 4 following operations:
       Reset
       Interrupt
       Ready
       Hold




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Reset
   All operations are stopped and the program
    counter is reset to 0000.




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Interrupt
   The microprocessor’s operations are
    interrupted and the microprocessor
    executes what is called a “service
    routine”.
   This routine “handles” the interrupt,
    (perform the necessary operations).
   Then the microprocessor returns to its
    previous operations and continues.
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Ready
   The 8085 has a pin called RDY.
   This pin is used by external devices to stop
    the 8085 until they catch up.
   As long as the RDY pin is low, the 8085 will
    be in a wait state.




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                 Department of Electrical Engineering, College of
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Hold
   The 8085 has a pin called HOLD.
   This pin is used by external devices to gain
    control of the busses.
   When the HOLD signal is activated by an
    external device, the 8085 stops executing
    instructions and stops using the busses.
   This would allow external devices to control the
    information on the busses. Example DMA.

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                   Department of Electrical Engineering, College of
                         Technology, GBPUAT, Pantnagar                126
Memory
   Memory in a microprocessor system is
    where information (data and instructions) is
    kept. It can be classified into two main
    types:
          Primary or Main memory (RAM and ROM)
          Secondary or Storage memory (Disks , CD ROMs,
           etc.)



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Memory
   The simple view of RAM is that it is made up of
    registers that are made up of flip-flops (or
    memory elements).
   The number of flip-flops in a “memory register”
    determines the size of the memory word.
   ROM on the other hand uses diodes instead of
    the flip-flops to permanently hold the
    information.

                            TEE-211: Microprocessors
                   Department of Electrical Engineering, College of
                         Technology, GBPUAT, Pantnagar                128
Accessing Information in Memory
   For the microprocessor to access (Read or
    Write) information in memory (RAM or
    ROM), it needs to do the following:
       Select the right memory chip (using part of the
        address bus).
       Identify the memory location (using the rest of
        the address bus).
       Access the data (using the data bus).

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                     Department of Electrical Engineering, College of
                           Technology, GBPUAT, Pantnagar                129
The Basic Memory Element
   The basic memory element is similar to a D
    latch.
   This latch has an input where the data
    comes in.
   It has an enable input.
   It has an output on which data comes out.


                          TEE-211: Microprocessors
                 Department of Electrical Engineering, College of
                       Technology, GBPUAT, Pantnagar                130
The Basic Memory Element



                                               Data Output



           Enable




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         Department of Electrical Engineering, College of
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The Basic Memory Element
   Data is always present on the input and the
    output is always set to the contents of the
    latch.
   To avoid this, tri-state buffers are added at
    the input and output of the latch.




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The Basic Memory Element




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The Basic Memory Element
   The WR signal controls the input buffer.
       The bar over WR means that this is an active low
        signal.
       So, if WR is 0 the input data reaches the latch
        input.
       If WR is 1 the input of the latch looks like a wire
        connected to nothing.
   The RD signal controls the output in a
    similar manner.
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A Memory “Register”
   If we take four of these latches and connect
    them together, we would have a 4-bit
    memory register




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A Memory “Register”




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A group of
memory registers
Expanding on this
scheme to add more
memory registers we get
the diagram to the right.




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A group of memory registers




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A group of memory registers
   Using the RD and WR controls we can determine
    the direction of flow either into or out of memory.
   Then using the appropriate Enable input we
    enable an individual memory register.
   What we have just designed is a memory with 4
    locations and each location has 4 elements (bits).
   This memory would be called 4 X 4 [Number of
    location X number of bits per location].

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The Enable Inputs
   How do we produce these enable line?
   Since we can never have more than one of
    these enables active at the same time, we
    can have them encoded to reduce the
    number of lines coming into the chip.
   These encoded lines are the address lines
    for memory.

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Memory Chip




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Memory Chip
   Since we have tri-state buffers on both the
    inputs and outputs of the flip flops, we can
    actually use one set of pins only.




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Memory Chip




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Memory Chip




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The steps of writing into Memory
   The programmer issues the STA instruction.
   The microprocessor would turn on the WR
    control (WR = 0) and turn off the RD control
    (RD = 1).
   The address is applied to the address decoder
    which generates a single Enable signal to turn
    on only one of the memory registers.
   The data is then applied on the data lines and it
    is stored into the enabled register.
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Dimensions of Memory
   Memory is usually measured by two
    numbers: its length and its width (Length X
    Width).
          The length is the total number of locations.
          The width is the number of bits in each location.

   The length (total number of locations) is a
    function of the number of address lines.
               # of memory locations = 2( # of address lines)

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Dimensions of Memory
   So, a memory chip with 10 address lines
    would have
             210 = 1024 locations (1K)

   Looking at it from the other side, a memory
    chip with 4K locations would need
            Log2 4096=12 address lines


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The 8085 and Memory
   The 8085 has 16 address lines. That
    means it can address
       216 = 64K memory locations.
   Then it will need 1 memory chip with 64 k
    locations, or 2 chips with 32 K in each, or 4
    with 16 K each or 16 of the 4 K chips, etc.
   How would we use these address lines to
    control the multiple chips?
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Chip Select
   Usually, each memory chip has a CS (Chip
    Select) input. The chip will only work if an active
    signal is applied on that input.
   To allow the use of multiple chips in the make
    up of memory, we need to use a number of the
    address lines for the purpose of “chip selection”.
   These address lines are decoded to generate
    the 2n necessary CS inputs for the memory
    chips to be used.
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Chip Selection Example
  Assume that we need to build a
   memory system made up of 4 of the 4 X
   4 memory chips we designed earlier.
  We will need to use 2 inputs and a
   decoder to identify which chip will be
   used at what time.
  The resulting design would now look
   like the one on the following slide.
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Memory Map and Addresses
   The memory map is a pictorial
    representation of the address range
   It shows where the different memory chips
    are located within the address range.




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Address Range of a Memory Chip
   The address range of a particular chip is the list of all
    addresses that are mapped to the chip.
   An example for the address range and its relationship to
    the memory chips would be the Post Office Boxes in the
    post office.
   Each box has its unique number that is assigned
    sequentially. (memory locations)
   The boxes are grouped into groups. (memory chips)
   The first box in a group has the number immediately
    after the last box in the previous group.
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Address Range of a Memory Chip
   The above example can be modified slightly to
    make it closer to our discussion on memory.
   Let’s say that this post office has only 1000
    boxes.
   Let’s also say that these are grouped into 10
    groups of 100 boxes each.
   Boxes 0000 to 0099 are in group 0, boxes 0100
    to 0199 are in group 1 and so on.

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Address Range of a Memory Chip
   We can look at the box number as if it is made
    up of two pieces:
   The group number and the box’s index within
    the group.
   So, box number 436 is the 36th box in the 4th
    group.
   The upper digit of the box number identifies the
    group and the lower two digits identify the box
    within the group.
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The 8085 and Address Ranges
   The 8085 has 16 address lines.
   It can address a total of 64K memory locations.
   If we use memory chips with 1K locations each, then
    we will need 64 such chips.
   The 1K memory chip needs 10 address lines to
    uniquely identify the 1K locations. (log21024 = 10)
   That leaves 6 address lines which is the exact
    number needed for selecting between the 64
    different chips (log264 = 6).

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The 8085 and Address Ranges
   Now, we can break up the 16-bit address of
    the 8085 into two pieces.
       A15 - A10
       A9 - A0
   Depending on the combination on the
    address lines A15 - A10 , the address range
    of the specified chip is determined.

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The 8085 and Address Ranges




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Chip Select Example
   A chip that uses the combination A15 - A10 =
    001000 would have addresses that range from
    2000H to 23FFH.
   10 address lines on the chip gives a range of
    00 0000 0000 to 11 1111 1111 or 000H to
    3FFH for each of the chips.
   The memory chip in this example would
    require the following circuit on its chip select
    input.
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Chip Select Example




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Chip Select Example
   If we change the above combination to the
    following:




   Now the chip would have addresses ranging
    from: 2400 to 27FF.
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Chip Select Example




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High-Order vs. Low-Order
Address Lines
   The address lines from a microprocessor
    can be classified into two types:
       High-Order
            Used for memory chip selection
       Low-Order
            Used for location selection within a memory chip.
   This classification is highly dependent on
    the memory system design.
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Data Lines
   All of the above discussion has been
    regarding memory length.
   Lets look at memory width.
   We said that the width is the number of bits
    in each memory word.
   We have been assuming so far that our
    memory chips have the right width.
   What if they don’t?
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Data Lines
   It is very common to find memory chips that
    have only 4 bits per location.
   How would you design a byte wide memory
    system using these chips?
   We use two chips for the same address range.
   One chip will supply 4 of the data bits per
    address and the other chip supply the other 4
    data bits for the same address.

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The 8085 and Its Busses
   The 8085 is an 8-bit general purpose
    microprocessor that can address 64K Byte
    of memory.
   It has 40 pins and uses +5V for power. It
    can run at a maximum frequency of 3 MHz.




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The 8085 and Its Busses
   The pins on the chip can be grouped into 6
    groups:
       Address Bus.
       Data Bus.
       Control and Status Signals.
       Power supply and frequency.
       Externally Initiated Signals.
       Serial I/O ports.

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The Address and Data Busses
   The address bus has 8 signal lines A15 –
    A8 which are unidirectional.
   The other 8 address bits are multiplexed
    (time shared) with the 8 data bits
    (AD7 – AD0 ).
   AD7 – AD0 are bi-directional and serve as
    A7 – A0 and D7 – D0 at the same time.

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The Address and Data Busses
   During the execution of the instruction,
    these lines carry the address bits during the
    early part, then during the late parts of the
    execution, they carry the 8 data bits.
   In order to separate the address from the
    data, we can use a latch to save the value
    before the function of the bits changes.

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The Control and Status Signals
   ALE: Address Latch Enable. This signal is a
    pulse that become 1 when the AD7 – AD0 lines
    have an address on them. It becomes 0 after
    that. This signal can be used to enable a latch
    to save the address bits from the AD lines.

   RD: Read (Active low).

   WR: Write (Active low).
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The Control and Status Signals
   IO/M: This signal specifies whether the
    operation is a memory operation (IO/M=0)
    or an I/O operation (IO/M=1).

   S1 and S0 : Status signals to specify the
    kind of operation being performed .Usually
    un-used in small systems.

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Frequency Control Signals
   X0 and X1 are the inputs from the crystal or
    clock generating circuit.
   The frequency is internally divided by 2.
   So, to run the microprocessor at 3 MHz, a
    clock running at 6 MHz should be
    connected to the X0 and X1 pins.
   CLK (OUT): An output clock pin to drive the
    clock of the rest of the system.
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Microprocessor Communication
and Bus Timing
   Study the process of communication
    between the microprocessor and memory
    during a memory read or write operation.

   Lets look at timing and the data flow of an
    instruction fetch operation.


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Steps For Fetching an Instruction
   Assume that we are trying to fetch the
    instruction at memory location 2005H.
   The program counter is set to 2005H.
   The following is the sequence of
    operations.
   The program counter places the address
    value on the address bus.

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Steps For Fetching an Instruction
   The control unit of the microprocessor
    issues an RD signal.
   The memory’s address decoder gets the
    value and determines which memory
    location is being accessed.
   The value in the memory location is placed
    on the data bus.

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Steps For Fetching an Instruction
   The value on the data bus is read into the
    instruction decoder inside the
    microprocessor.
   The instruction is decoded.
   After decoding the instruction, the control
    unit issues the proper control signals to
    perform the operation.

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Timing Signals For Fetching an
Instruction
   At T1, the high order 8 address bits (20H) are
    placed on the address lines A15 – A8 and the
    low order bits are placed on AD7–AD0.
   The ALE signal goes high to indicate that AD7–
    AD0 are carrying an address.
   At exactly the same time, the IO/M signal goes
    low to indicate a memory operation.
   At the beginning of the T2 cycle, the low order 8
    address bits are removed from AD7– AD0.
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Timing Signals For Fetching an
Instruction
   The controller sends the Read (RD) signal to
    the memory.
   The signal remains low (active) for two clock
    periods to allow for slow devices.
   During T2 , memory places the data from the
    memory location on the lines AD7– AD0 .
   During T3, the RD signal is Disabled (goes
    high).

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Timing Signals For Fetching an
Instruction
 This turns off the output Tri-state buffers
  in the memory.
 That makes the AD7– AD0 lines go to
  high impedence mode.




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Demultiplexing AD7-AD0
   The AD7– AD0 lines are serving a dual purpose
    and that they need to be demultiplexed to get all
    the information.
   The high order bits of the address remain on the
    bus for three clock periods.
   The low order bits remain for only one clock
    period and they would be lost if they are not
    saved externally.


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Demultiplexing AD7-AD0
   The low order bits of the address disappear
    when they are needed.
   To make sure the availability of the entire
    address for the full three clock cycles, we
    use an external latch to save the value of
    AD7– AD0 when it is carrying the address
    bits.
   We use the ALE signal to enable this latch.
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Demultiplexing AD7-AD0
 Given that ALE operates as a pulse during
  T1, we will be able to latch the address.
 When ALE goes low, the address is saved
  and the AD7– AD0 lines can be used for
  their purpose as the bi-directional data
  lines.


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Demultiplexing AD7-AD0




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Cycles and States
   T- State:
      A T-state lasts for one clock period.

      An instruction’s execution length is usually measured in a
        number of T-states. (clock cycles).
   Machine Cycle:
      The time required to complete one operation of accessing
        memory, I/O, or acknowledging an external request.
      This cycle may consist of 3 to 6 T-states.

   Instruction Cycle:
      The time required to complete the execution of an instruction.

      This may consist of 1 to 6 machine cycles.

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Generating Control Signals
   The 8085 generates a single RD.
   This signal needs to be used with both
    memory and I/O.
   It is combined with the IO/M signal to
    generate different control signals for the
    memory and I/O.
   RD, WR,and IO/M signals are combined to
    generate the right set of signals.
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Generating Control Signals




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The ALU
   In addition to the arithmetic & logic circuits,
    the ALU includes the accumulator, which is
    part of every arithmetic & logic operation.
   Also, the ALU includes a temporary register
    used for holding data temporarily during the
    execution of the operation.
   This temporary register is not accessible by
    the programmer.
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The Flags register
   There is also the flags register whose bits are affected
    by the arithmetic & logic operations.
      S-sign flag

      Z-zero flag

      AC-Auxiliary Carry

      P-Parity flag

      CY-carry flag




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Flags
   S-sign flag
      The sign flag is set if bit D7 of the accumulator is set after an arithmetic or
        logic operation.
   Z-zero flag
      Set if the result of the ALU operation is 0. Otherwise is reset. This flag is
        affected by operations on the accumulator as well as other registers. (DCR
        B).
   AC-Auxiliary Carry
      This flag is set when a carry is generated from bit D3 and passed to D4. This
        flag is used only internally for BCD operations.
   P-Parity flag
      After an ALU operation if the result has an even # of 1’s the p-flag is set.
        Otherwise it is cleared. So, the flag can be used to indicate even parity.
   CY-carry flag
      This flag is set when a carry is generated from bit D7 otherwise reset.

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8085 Operations
   Memory Read and Write.
   I/O Read and Write.
   Request Acknowledge.




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Opcode Fetch Machine Cycle
   The first step of executing any instruction is
    the Opcode fetch cycle.
   In this cycle, the microprocessor brings in
    the instruction’s Opcode from memory.
   To differentiate this machine cycle from the
    very similar “memory read” cycle, the
    control & status signals are set as follows:
       IO/M = 0, s0 = 1, s1 = 1.
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Opcode Fetch Machine Cycle
   This machine cycle has four T-states.
   The 8085 uses the first 3 T-states to fetch
    the opcode.
   T4 is used to decode and execute it.
   It is also possible for an instruction to have
    6 T-states in an opcode fetch machine
    cycle.

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Memory Read Machine Cycle
   The memory read machine cycle is exactly
    the same as the opcode fetch except:
   It only has 3 T-states
   The s0 signal is set to 0 instead of 1.




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Memory Read Machine Cycle
   To understand the memory read machine
    cycle, let’s study the execution of the
    following instruction:
          MVI A, 32H
   In memory, this instruction looks like:
          The first byte 3EH represents the opcode for
           loading a byte into the accumulator (MVI A).
          The second byte is the data to be loaded.

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Memory Read Machine Cycle
 The 8085 needs to read these two bytes
  from memory before it can execute the
  instruction.
 It will need at least two machine cycles.
 The first machine cycle is the opcode fetch
 discussed earlier.
 The second machine cycle is the Memory
 Read Cycle.
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Machine Cycles vs. Number of
bytes in the instruction
   Machine cycles and instruction length, do
    not have a direct relationship.
   To illustrate lets look at the machine cycles
    needed to execute the following instruction.
         STA 2065H
   This is a 3-byte instruction requiring 4 machine cycles
    and 13 T-states.


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STA 2065H




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STA 2065H
This instruction requires the following 4
machine cycles:
       Opcode fetch to fetch the opcode (32H) from location 2010H,
        decode it and determine that 2 more bytes are needed (4 T-
        states).
       Memory read to read the low order byte of the address (65H) (3
        T-states).
       Memory read to read the high order byte of the address (20H) (3
        T-states).
       A memory write to write the contents of the accumulator into the
        memory location.

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    The Memory Write Operation
        The 8085 places the address (2065H) on the
         address bus
        Identifies the operation as a memory write
         (IO/M=0, s1=0, s0=1).
        Places the contents of the accumulator on
         the data bus and asserts the signal WR.
        During the last T-state, the contents of the
         data bus are saved into the memory location.

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Memory Interfacing
   There needs to be a lot of interaction between
    the microprocessor and the memory for the
    exchange of information during program
    execution.
   Memory has its requirements on control signals
    and their timing.
   The microprocessor has its requirements as well.
   The interfacing operation is simply the matching
    of these requirements.
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Memory structure & its
requirements
   The process of interfacing the RAM & ROM is
    the same.
   However, the ROM does not have a WR signal.




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Memory structure & its
requirements




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Interfacing Memory
   Accessing memory can be summarized into
    the following three steps:
         Select the chip.
         Identify the memory register.
         Enable the appropriate buffer.




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Interfacing Memory
   Translating this to microprocessor domain:
          The microprocessor places a 16-bit address on
           the address bus.
          Part of the address bus will select the chip and the
           other part will go through the address decoder to
           select the register.
          The signals IO/M and RD combined indicate that a
           memory read operation is in progress. The MEMR
           signal can be used to enable the RD line on the
           memory chip.
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Address decoding
    The result of address decoding is the identification
     of a register for a given address.
    A large part of the address bus is usually connected
     directly to the address inputs of the memory chip.
    This portion is decoded internally within the chip.
    What concerns us is the other part that must be
     decoded externally to select the chip.
    This can be done either using logic gates or a
     decoder.


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The Overall Picture




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Interfacing the 8155
   The 8155 is a special chip designed to
    work with the 8085 to demonstrate the
    interfacing of the 8085.
   the 8155 has 256 bytes of RAM, 2
    programmable I/O ports and a timer.
   It is usually used in systems designed for
    use in university labs.

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Interfacing the 8155 memory section
   The 8155 contains all the circuitry needed
    to interface to the 8085 directly.
   It has 8 lines that match the AD0-AD7 of
    the 8085.
   It has 5 control lines that match the control
    and status lines of the 8085.


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Interfacing the 8155 memory section
   The address/data lines are demultiplexed
    internally inside the 8155 and the control
    signals needed for the memory are also
    generated internally.
   All that is needed to interface the 8155 to
    the 8085 is logic to control the 8155 to
    determine the starting address of the
    memory segment.
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Don’t care address lines and fold back
memory
   It is possible in a small computer system to
    use multiple addresses for the same memory
    location.
   In that case, memory is small and limited, so it
    doesn’t make sense to use all of the address
    lines to specify each of the locations.
   Some of the address lines are left
    unconnected.

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Don’t care address lines and fold
back memory
   This results in don’t care address lines.
   Same set of memory registers is used when the
    user enters the different addresses.
   This process is called memory fold back. i.e. the
    new address range is folded back over the old
    address.
   This allows the use of a much simpler decoding
    circuit for the address lines.

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Testing Memory Interfacing Circuits
   Testing a memory chip in an existing system is
    as easy as loading a byte at a specific address
    and then verifying that it was loaded.
   A few more addresses should also be
    checked.
   In case of fold back memory, one should test
    the different address ranges for the don’t care
    address lines.

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Interfacing I/O Devices
   Using I/O devices, data can be transferred
    between the microprocessor and the outside
    world.
   This can be done in groups of 8 bits using
    the entire data bus. This is called parallel I/O.
   The other method is serial I/O where one bit
    is transferred at a time using the SI and SO
    pins on the Microprocessor.
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Dealing with I/O Devices
   There are two ways to deal with I/O
    devices.
       Memory-mapped I/O.
       I/O-mapped I/O or Peripheral-mapped I/O.
       Consider them like any other memory location.
             They are assigned a 16-bit address within the address
              range of the 8085.
             The exchange of data with these devices follows the
              transfer of data with memory. The user uses the same
              instructions used for memory.
             This is called memory-mapped I/O.
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       Treat them separately from memory:
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Memory-mapped I/O
   Consider them like any other memory
    location.
   They are assigned a 16-bit address within
    the address range of the 8085.
   The exchange of data with these devices
    follows the transfer of data with memory.
   The user uses the same instructions as
    used for memory.
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I/O-mapped I/O or Peripheral-
mapped I/O
   Treat them separately from memory:
   I/O devices are assigned a “port number”
    within the 8-bit address range of 00H to
    FFH.
   The user in this case would access these
    devices using the IN and OUT instructions
    only.

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Basic interfacing concepts
   The first step in interfacing an I/O device would
    be to determine which instructions will be used
    to access it.
   If you want the user to use the IN/OUT
    instructions, then it should be interfaced as a
    peripheral-mapped I/O device.
   If the user should use regular data transfer
    instructions (LDA, STA, etc.) then it should be
    interfaced as a memory-mapped I/O device.
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Peripheral I/O instructions
   There are two instructions:
       IN brings data (8-bits) from an input device to the
        accumulator
       OUT brings data (8-bits) from the accumulator to
        an output device.
   They are both 2 byte instructions with the
    second byte holding the 8-bit address of
    the device.

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Peripheral I/O instructions
   Given that there are separate instructions
    for input and output, the 8085 can actually
    communicate with
       256 different input devices
       AND
       an additional 256 different output devices.




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The execution of the OUT instruction
   The OUT instruction requires 3 machine
    cycles and 10 T-states.
   The first cycle is an opcode fetch cycle to
    fetch the 1st byte of the instruction from
    memory (OUT).
   The second cycle is a memory read cycle
    to bring the 8-bit port number from the next
    location.
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The execution of the OUT instruction
   The third cycle is an I/O write cycle.
   In this cycle, the 8085 places the port
    number on AD7-AD0 AND A15-A8.
   The signal WR is set low (active).
   Since the device address is placed on both
    AD7-AD0 as well as A15-A8, there is no
    need for de-multiplexing AD0-AD7. A15-A8
    can be used directly to identify the device.
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The execution of the IN instruction
   The execution of the IN instruction is
    almost identical to that of the OUT
    instruction.
   3 machine cycles, 10 T-states.
   The first machine cycle is the opcode fetch.
   The second cycle is the memory read to
    get the port number.

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The execution of the IN instruction
   The third is an I/O Read cycle.
   Again, in T1 the port address (8-bits) is
    placed on both AD7- AD0, and A15-A8.
   The IO/M signal is set high to indicate an
    I/O operation.
   At the beginning of T2, the RD signal is set
    low (active) and the I/O device responds by
    placing the 8-bit data on the data bus.
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The interfacing of output devices
   Output devices are usually slow.
   Also, the output is usually expected to
    continue appearing on the output device for
    a long period of time.
   Given that the data will only be present on
    the data lines for a very short period
    (microseconds), it has to be latched
    externally.
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The interfacing of output devices
   To do this the external latch should be enabled
    when the port’s address is present on the address
    bus, the IO/M signal is set high and WR is set low.
   The resulting signal would be active when the
    output device is being accessed by the
    microprocessor.
   Decoding the address bus (for memory-mapped
    devices) follows the same techniques discussed
    in interfacing memory.
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Interfacing of input devices
   The basic concepts are similar to
    interfacing of output devices.
   The address lines are decoded to generate
    a signal that is active when the particular
    port is being accessed.
   An IOR signal is generated by combining
    the IO/M and the RD signals from the
    microprocessor.
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Interfacing of input devices
   A tri-state buffer is used to connect the
    input device to the data bus.
   The control (Enable) for these buffers is
    connected to the result of combining the
    address signal and the signal IOR.




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Interfacing the LEDs
   Let’s first design the external circuit.
   The data on the data bus from the
    microprocessor stays for an extremely
    short amount of time.
   In order to keep it long enough for
    displaying, we will need an external latch.


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Interfacing the LEDs
   We will use an 8-bit latch to hold the data
    we need to connect the 8 LED to the
    latches outputs.
   However, the latch will not be able to
    source enough current. So, we will use the
    inverted outputs and make it sink the
    current instead.

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When should the latch be enabled?
   It needs to be enabled when the data is on
    the data bus.
   That happens when the ALE signal is low.
    However, we only want to display the data
    that is being sent to the I/O, we don’t want
    to display the data being saved in memory.



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When should the latch be enabled?
   So, the latch needs to be enabled only
    during I/O operations. That happens when
    IO/M=1
   Finally we only want to display data
    intended for our port. We must decide on a
    port number.
          Let’s say FFH.
   Now, we can design the control circuit.
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Interfacing the LEDs (Control Circuit)
   The Latch will be enabled when:
       WR = 0
       IO/M = 1
       The address on A15 – A8 = FFH




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Interfacing the LEDs (Latch & LEDs)




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Interfacing the LEDs (the program)
   When a bit on the AD bus is 1, the
    corresponding Q’ will be zero and the LED
    will have 5 volts on the anode and 0 on the
    cathode. Therefore, it will be on.
   Finally, to write the program:
       MVI A, Data            ;load the data to be displayed
       OUT FF                  ;send the data to output port FF
       HLT                    ;End

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Interfacing the switches
   The binary value from the switches will have to be carried by
    the data bus.
   The data bus is a shared bus.
   The switches must be connected to the data bus using Tri-
    state buffers.
   Similar to the latch, the buffers must be enabled only on I/O
    Read operation from this I/O port.
   Let us choose I/O port 0FH for the switches. So, the buffers
    must be enabled when:
           RD = 0
           IO/M = 1
           A15-A8 = 0FH
Interfacing the Switches (Control
Circuit)
Interfacing the Switches (Latch & Switches)
Interfacing the Switches (the program)
   Finally, the program:
       IN 0FH        ;input data from port 0F into A
       HLT           ;END


   If we combine both circuits, then we can write the
    following program:
    INPUT:      IN 0FH
                OUT FFH
                JMP INPUT
Interfacing a Memory-Mapped I/O device
   Instead of using 8-bit address, the full 16-
    bits of the address bus must be used.
   Instead of using IOR and IOW, use MEMR
    and MEMW.
Counters
   A loop counter is set up by loading a register
    with a certain value
   Then using the DCR (to decrement) and INR (to
    increment) the contents of the register are
    updated.
   A loop is set up with a conditional jump
    instruction that loops back or not depending on
    whether the count has reached the termination
    count.
Counters
Delays
   Each instruction passes through different
    combinations of Fetch, Memory Read, and
    Memory Write cycles.
   Knowing the combinations of cycles, one can
    calculate how long such an instruction would
    require to complete.
   Knowing how many T-States an instruction
    requires, and keeping in mind that a T-State is
    one clock cycle long, we can calculate the time
    using the following formula:
          Delay = No. of T-States / Frequency
Delays
   For example a “MVI” instruction uses 7 T-
    States. Therefore, if the Microprocessor is
    running at 2 MHz, the instruction would
    require 3.5 microseconds to complete.
Delay loops
   We can use a loop to produce a certain amount of
    time delay in a program.
   The following is an example of a delay loop:
      MVI C, FFH     7 T-States
LOOP: DCR C          4 T-States
      JNZ LOOP       10 T-States
                                  the loop counter and
 The first instruction initializes
    is executed only once requiring only 7 T-States.
   The following two instructions form a loop that
    requires 14 T-States to execute and is repeated
    255 times until C becomes 0.
Delay loops
   In the last iteration of the loop, the JNZ
    instruction will fail and require only 7 T-States
    rather than the 10.
   Therefore, we must deduct 3 T-States from the
    total delay to get an accurate delay calculation.
   To calculate the delay, we use the following
    formula:
                     Tdelay = TO + TL
      Tdelay = total delay
      TO = delay outside the loop
      TL = delay of the loop
Delay loops
   TO is the sum of all delays outside the loop.
   TL is calculated using the formula
              TL = T X Loop T-States X N10
   TO = 7 T-States
       Delay of the MVI instruction
   TL = (14 X 255) - 3 = 3567 T-States
       14 T-States for the 2 instructions repeated 255
        times (FFH = 25510) reduced by the 3 T-States for
        the final JNZ.
   TDelay = (7 + 3567) X 0.5 mSec = 1.787 mSec
       Assuming f = 2 MHz
Using a Register Pair as a Loop Counter
   Using a single register, one can repeat a loop for
    a maximum count of 255 times.
   It is possible to increase this count by using a
    register pair for the loop counter instead of the
    single register.
       A minor problem arises in how to test for the final count
        since DCX and INX do not modify the flags.
       However, if the loop is looking for when the count
        becomes zero, we can use a small trick by ORing the two
        registers in the pair and then checking the zero flag.
Using a Register Pair as a Loop Counter
   The following is an example of a delay loop
    set up with a register pair as the loop
    counter.

            LXI B, 1000H    10 T-States
LOOP:       DCX B           6 T-States
            MOV A, C        4 T-States
            ORA B           4 T-States
            JNZ LOOP        10 T-States
Using a Register Pair as a Loop Counter
   TO = 10 T-States
       The delay for the LXI instruction
   TL = (24 X 4096) - 3 = 98301 T- States
       24 T-States for the 4 instructions in the loop
        repeated 4096 times (100016 = 409610) reduced
        by the 3 T-States for the JNZ in the last iteration.
   TDelay = (10 + 98301) X 0.5 mSec =
    49.155 mSec
Nested Loops
   Nested loops can be easily setup in
    Assembly language by using two registers
    for the two loop counters and updating the
    right register in the right loop.
   In the figure, the body of loop2 can be
    before or after loop1.
Nested Loops
Nested Loops for Delay
   Instead (or in conjunction with) Register
    Pairs, a nested loop structure can be used
    to increase the total delay produced.

            MVI B, 10H      7 T-States
LOOP2:      MVI C, FFH      7 T-States
LOOP1:      DCR C           4 T-States
            JNZ LOOP1       10 T-States
            DCR B           4 T-States
            JNZ LOOP2       10 T-States
Delay Calculation of Nested Loops
   The calculation remains the same except that it the
    formula must be applied recursively to each loop.
   Start with the inner loop, then plug that delay in the
    calculation of the outer loop.
   Delay of inner loop
       TO1 = 7 T-States
            MVI C, FFH instruction
       TL1 = (255 X 14) - 3 = 3567 T-States
            14 T-States for the DCR C and JNZ instructions repeated 255
             times (FF16 = 25510) minus 3 for the final JNZ.
       TLOOP1 = 7 + 3567 = 3574 T-States
Delay Calculation of Nested Loops
   Delay of outer loop
       TO2 = 7 T-States
            MVI B, 10H instruction
       TL1 = (16 X (14 + 3574)) - 3 = 57405 T-States
            14 T-States for the DCR B and JNZ instructions and 3574
             T-States for loop1 repeated 16 times (1016 = 1610) minus 3
             for the final JNZ.
       TDelay = 7 + 57405 = 57412 T-States
   Total Delay
       TDelay = 57412 X 0.5 mSec = 28.706 mSec
Increasing the delay
   The delay can be further increased by
    using register pairs for each of the loop
    counters in the nested loops setup.
   It can also be increased by adding dummy
    instructions (like NOP) in the body of the
    loop.
The Stack
   The stack is an area of memory identified by the
    programmer for temporary storage of information.
   The stack is a LIFO structure (Last In First Out).
   The stack normally grows backwards into
    memory.
   In other words, the programmer defines the
    bottom of the stack and the stack grows up into
    reducing address range.

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The Stack




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The Stack
   Given that the stack grows backwards into
    memory, it is customary to place the bottom of
    the stack at the end of memory to keep it as far
    away from user programs as possible.
   In the 8085, the stack is defined by setting the
    SP (Stack Pointer) register.
                      LXI SP, FFFFH
   This sets the Stack Pointer to location FFFFH
    (end of memory for the 8085).
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Saving Information on the Stack
   Information is saved on the stack by
    PUSHing it on.
   It is retrieved from the stack by POPing it off.
   The 8085 provides two instructions: PUSH
    and POP for storing information on the stack
    and retrieving it back.
   Both PUSH and POP work with register pairs
    ONLY.
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The PUSH Instruction
   PUSH B
       Decrement SP
       Copy the contents of register B to the memory
        location pointed to by SP
       Decrement SP
       Copy the contents of register C to the memory
        location pointed to by SP



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The PUSH Instruction




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The POP Instruction
   POP D
       Copy the contents of the memory location
        pointed to by the SP to register E
       Increment SP
       Copy the contents of the memory location
        pointed to by the SP to register D
       Increment SP



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The POP Instruction




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Operation of the Stack
   During pushing, the stack operates in a “decrement
    then store” style.
   The stack pointer is decremented first, then the
    information is placed on the stack.
   During poping, the stack operates in a “use then
    increment” style.
   The information is retrieved from the top of the the
    stack and then the pointer is incremented.
   The SP pointer always points to “the top of the stack”.

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LIFO
   The order of PUSHs and POPs must be opposite of
    each other in order to retrieve information back into its
    original location.
       PUSH B
       PUSH D
       ...
       POP D
       POP B
   Reversing the order of the POP instructions will result in
    the exchange of the contents of BC and DE.
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The PSW Register Pair
   The 8085 recognizes one additional register pair called
    the PSW (Program Status Word).
   This register pair is made up of the Accumulator and the
    Flags registers.
   It is possible to push the PSW onto the stack, do
    whatever operations are needed, then POP it off of the
    stack.
   The result is that the contents of the Accumulator and
    the status of the Flags are returned to what they were
    before the operations were executed.

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Subroutines
   A subroutine is a group of instructions that will be
    used repeatedly in different locations of the
    program.
   Rather than repeat the same instructions several
    times, they can be grouped into a subroutine that is
    called from the different locations.
   In Assembly language, a subroutine can exist
    anywhere in the code.
   However, it is customary to place subroutines
    separately from the main program.
                             TEE-211: Microprocessors
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                          Technology, GBPUAT, Pantnagar                269
Subroutines
   The 8085 has mainly two instructions for
    dealing with subroutines.
   The CALL instruction is used to redirect
    program execution to the subroutine.
   The RET insutruction is used to return the
    execution to the calling routine.


                          TEE-211: Microprocessors
                 Department of Electrical Engineering, College of
                       Technology, GBPUAT, Pantnagar                270
The CALL Instruction
 CALL    4000H
    Push the address of the instruction
     immediately following the CALL onto the
     stack
    Load the program counter with the 16-bit
     address supplied with the CALL
     instruction.

                         TEE-211: Microprocessors
                Department of Electrical Engineering, College of
                      Technology, GBPUAT, Pantnagar                271
The CALL Instruction




                  TEE-211: Microprocessors
         Department of Electrical Engineering, College of
               Technology, GBPUAT, Pantnagar                272
The RET Instruction
 RET
    Retrieves the return address from the top
     of the stack
    Loads the program counter with the
     return address.




                         TEE-211: Microprocessors
                Department of Electrical Engineering, College of
                      Technology, GBPUAT, Pantnagar                273
The RET Instruction




                   TEE-211: Microprocessors
          Department of Electrical Engineering, College of
                Technology, GBPUAT, Pantnagar                274
Cautions
   The CALL instruction places the return address at the
    two memory locations immediately before where the
    Stack Pointer is pointing.
   You must set the SP correctly BEFORE using the CALL
    instruction.
   The RET instruction takes the contents of the two
    memory locations at the top of the stack and uses these
    as the return address.
   Do not modify the stack pointer in a subroutine. You will
    loose the return address.

                              TEE-211: Microprocessors
                     Department of Electrical Engineering, College of
                           Technology, GBPUAT, Pantnagar                275
Passing Data to a Subroutine
   In Assembly Language data is passed to a subroutine
    through registers.
   The data is stored in one of the registers by the calling
    program and the subroutine uses the value from the
    register.
   The other possibility is to use agreed upon memory
    locations.
   The calling program stores the data in the memory
    location and the subroutine retrieves the data from the
    location and uses it.

                               TEE-211: Microprocessors
                      Department of Electrical Engineering, College of
                            Technology, GBPUAT, Pantnagar                276
Call by Reference and Call by Value
   If the subroutine performs operations on the
    contents of the registers, then these modifications
    will be transferred back to the calling program upon
    returning from a subroutine.
      Call by reference

   If this is not desired, the subroutine should PUSH
    all the registers it needs on the stack on entry and
    POP them on return.
      The original values are restored before execution
        returns to the calling program.
                             TEE-211: Microprocessors
                    Department of Electrical Engineering, College of
                          Technology, GBPUAT, Pantnagar                277
Cautions with PUSH and POP
   PUSH and POP should be used in opposite
    order.
   There has to be as many POP’s as there are
    PUSH’s.
   If not, the RET statement will pick up the wrong
    information from the top of the stack and the
    program will fail.
   It is not advisable to place PUSH or POP inside
    a loop.
                            TEE-211: Microprocessors
                   Department of Electrical Engineering, College of
                         Technology, GBPUAT, Pantnagar                278
Conditional CALL and RET Instructions
   The 8085 supports conditional CALL and
    conditional RET instructions.
   The same conditions used with conditional
    JUMP instructions can be used, e.g.
       CC, call subroutine if Carry flag is set.
       CNC, call subroutine if Carry flag is not set
       RC, return from subroutine if Carry flag is set
       RNC, return from subroutine if Carry flag is not set


                                TEE-211: Microprocessors
                       Department of Electrical Engineering, College of
                             Technology, GBPUAT, Pantnagar                279
Some Intel Peripheral Devices
   8255 – Parallel Communication Interface (PPI)
   8251 – Serial communication Interface (USART-
    Universal Synchronous/Asynchronous
    Receiver/Transmitter)
   8257 – DMA Controller
   8279 – Keyboard/Display Controller
   8259 – Programmable Interrupt controller
   8254 – Programmable Timer


                            TEE-211: Microprocessors
                   Department of Electrical Engineering, College of
                         Technology, GBPUAT, Pantnagar                280

								
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