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ELEN 665 (ESS) A M S C Analog and Mixed-Signal Center Receiver Architectures: Fundamentals and Properties 1 Analog and Mixed Signal Center- Texas A&M University (ESS) How can we relax or solve this image rejection problem ? A possible solution is the use of more than one IF stage. This can relaxed the specs of the filters and other building blocks. How many IF stages are required ? This depends on the design specs, a rule of thumb is to keep the ratio between the operating frequency before and after a downcoversion should be lower than 10. Say for a signal at 900 MHz can be first downconverted to an IF of 250 MHz, then filter out unwanted signal and second downconverted to 50 MHz and in a third downconversion the IF is 10 MHz. 2 How complex will be the filtering, power consumption and cost? Automatic Gain LNA Control X Y Z BPF BPF BPF ωLO1 ωLO2 X ω0 ω LO1 ωLO1 ω Y ω0 - ωLO1 ω LO2 ωLO2 ω Z ω 3 Double Superheterodyne Architecture Multi-Stage IF Receivers • From stage to stage the desired signal is further and further downconverted until the desired final IF is obtained. • The ratio between the operating frequency before and after downconversion is usually kept lower than 10, say 4. For instance a 1800 MHz signal is first downconverted to a first IF of 450 MHz, then consecutively to 90 MHz and finally to 18 MHz. • Note that each downconvertion stage has the same mirror frequency trouble than the single-stage IF receiver. • Significant filtering between stages is required. This filtering is done with off chip filters to further complicate the sensitivity to parasitic components, also the power consumption will be high. 4 The Image-Reject Receiver or Super Heterodyne Receiver with Quadrature Down-conversion D/A Image 90o Reject A Filter D C D LNA AGC 90 S A P D C PLL PLL 0o D/A • Good performance in terms of image and spurious suppression. • A complex mixer is required. • In the DSP a complex non-linear algorithm control the DC-level dynamically. • Low integration due to the use of SAW filters. • Limited multi-standard ability. Due to the difficulty to design broadband I/Q phase shifters an alternative solution (Weaver) solution is next discussed. 5 Analog and Mixed Signal Center, TAMU The Barber-Weaver Receiver RF 0 or Low IF1 Mixers IF1 Filter Mixers AGC IF2 Filter and ADC LNA AGC + • Double the silicon area and power dissipation 0 or Low I Q IF1 Filter I Q LO1 LO2 • Difficult Matching of I & Q Paths • Operates with low IF1 and IF2 6 +j +j Signals in the Weaver 0 ω Architecture 0 ω 0 -j -j ω Desired BPF I Channel A Image sinω1 t sinω2 t - cosω1 t cosω2 t + -ω1 0 ω1 ω + 0 ω B BPF Main drawback of this architecture is 0 ω incomplete image rejection due to phase and gain mismatch. Harmonics of the second 0 ω LO frequency may downconverted unfiltered interferers from the first IF to the second. 0 ω 7 Analog and Mixed Signal Center, TAMU What other receiver structures alternatives can be considered and with what properties ? Can we make the IF very low, say to DC ? How and at what price ? 8 Direct Conversion or Zero-IF front end Receiver Low Noise Amplifier (LNA) BPF LPF ω0 ω 0 ω ω0 • The LPF can be integrated. No image signal exists • The RF spectrum is translated to the baseband in the first downconversion. • The LO is equal to the input carrier frequency. • This architecture operates only with double-sideband AM signals because it overlaps negative and positive parts of the input spectrum. • For frequency and phase-modulated signals, the downconversion needs 9 quadrature outputs. Two sides of FSK (or QPSK) carry different information. Direct Conversion Front End Receiver With Quadrature Down-Conversion for FSK (digital) Demodulation Phase Detector Limiting and Tone I I Detector LPF LNA sinω0 t D BPF cosω0 t Ck Q LPF Q Zero IF • No image rejection filter is needed. • Offset voltages can degrade the S/N and saturate the following stages. Isolation between ports is not ideal. • I/Q mismatch degrades the downconversion constellation 10 Analog and Mixed Signal Center, TAMU FSK Direct Conversion Receiver.- The frequency shift keyed signals appear with opposed relative phase at the phase detector, giving a binary mark or space output according to weather the input signal is lower or higher than the local oscillator frequency. Let assume these inputs (mark and space) signals are: S M = cos( ω + ω D )t S S = cos( ω − ω D )t The quadrature oscillator signals to the mixers are: LO I = cos ω t LO Q = sin ω t The mixer outputs when a mark is sent are: I M = S M ⋅ LO I = cos( ω + ω D )t ⋅ cos ω t I M = 0.5[cos( ω + ω D ) + cos ω D t ] 11 QM = S M ⋅ LOQ = cos(ω + ω D )t ⋅ sin ωt QM = 0.5[sin(2ω + ω D )t − sin ω D t ] Similarly when a space is sent: I S = 0.5[cos ω D t + cos( 2ω + ω D )t QS = 0.5[sin(2ω − ω D )t + sin ω D t ] The double frequency components of I and Q are removed in the LPF of each channel, yielding: I M = +0.5 cos ωD t QM = −0.5 sin ω D t I S = +0.5 cos ωD t QS = +0.5 sin ωD t 12 Direct-Conversion Receiver (continues) An alternative implementation A AGC D C D LNA 90 S A P D AGC C üAllow for high level integration. ü Low power consumption. PLL ü Eliminate passive IF filters ü Good for SSB digital modulation ü Good Multi-standard ability. Ø DC offset problem. Ø Increased ADC dynamic range. Because of limited filtering Ø Need of a high-Q VCO. • Moves design efforts to baseband. • Unprotected LO leakage into antenna. • I/Q match required over high gain range 13 Analog and Mixed Signal Center, TAMU Low IF Receiver Architecture • All advantages of direct conversion. • More difficult image rejection. • DC spur (offset) outside the signal bandwidth. • Digital processing includes adjacent channel image rejection. • All weakness of direct conversion without the DC offset problem. • In Band image rejection. 14 Image Rejection Mixer Analysis ( same as in previous pages 11 & 12) I (t ) = cos (ω LO t ) ⋅ cos (ω RF t ) Image Reject Mixer = 0 .5 {cos [(ω LO − ω RF t )] + cos [(ωLO + ωRF )t ]} cos (ωRFt) Q(t) Adjacent Channel Q(t ) = sin (ω LO t ) ⋅ cos (ωRF t ) = 0.5 {sin [(ω LO − ω RF )t ] + sin [(ωLO + ωRF )t ]} LPF Qlp (t) Filter BPF LNA I lp ` (t ) = 0.5 cos[(ω LO − ωRF )t ] = 0 .5 cos (ωIF t ) -90 + BPF Ilp (t) Qlp (t ) = 0.5 sin [(ω LO − ω RF )t ] = 0 .5 sin (ω IF t ) I(t) LPF -90 Ilp’ (t) cos (ωLOt) ~ (ωLO > ωRF) ( ) I lp (t ) = 0 .5 cos ωIF − 90 o = 0 .5 sin (ω IF t ) v o (t ) = I lp (t ) + Qlp (t ) = sin (ω IF t ). The image input signal, for high-side injection of the LO, is v l,lm (t)=cos[(ω LO + ωIF )t]. I (t ) = cos[(ω LO + ω IF )t ] ⋅ cos (ω LO t ) = 0.5{cos (ωIF t ) + cos [(2ω LO + ω IF )t ]} I lp ` (t ) = 0.5 cos (ω IF t ) I lp (t ) = 0 .5 sin (ω IF t ) Q (t ) = sin (ω LO t ) ⋅ cos [(ω LO + ω IF )t ] = 0.5 sin (− ωIF t ) + 0 .5 sin [(2ω LO + ω IF )t ] Qlp (t ) = − 0.5 sin (ω IF t ) vo ,Im (t ) = I lp (t ) + Qlp (t ) = 0 ; Image response can be completely suppressed. 15 0.35µm CMOS Bluetooth Low-IF Receiver IC: An example of a Low-IF topology 2.4GHz 2MHz Demodulator I RF filter LNA Offset Q Polyphase Cancellation Filter /Decision PLL Developed in about 1 ½ years by : Authors:Wenjun Sheng, Bo Xia,Ahmed Emira, Chunyu Xin, Ari Ari Valero-Lopez, Sung Tae Moon and Edgar Sanchez-Sinencio. 16 0.35µm CMOS Bluetooth Low-IF Receiver IC • Publications: – 2002 RFIC Conference, Best Student Paper Award (third place). – Journal of Solid-State Circuits: January 2003 (Receiver) and August 2003 (Demodulator). – Transactions on Circuits and Systems – II: November 2003 (Complex Filter). 17 TRANSCEIVER CELLULAR RADIO BLOCK DIAGRAM Antenna Power Amplifier Data, Voice A/D and D/A Frequency Duplexer Transmitter Converters Interface Digital Signal Receiver Processor (DSP) Reference Frequency Oscillator Synthesizer µ Processor 18 GSM RECEIVER SYSTEM REQUIREMENTS Signal Level (dBm) 0 Blocking -23 dBm Blocking -43 dBm -40 Wanted-120dBm -80 -120 f fo +1MHz +2MHz +3MHz Gain of wanted signal > 100 dB Noise Figure of LNA input less than 8 dB 19 Subsampling Receiver IF to Baseband RF Stage RF to IF Digital Mixer RF=1846MHz I Digital LPF Subsampling AGC fs o RF LNA IMG IF BPF ADC 90 BPF REJ 246 MHz Digital Q RF LO LPF 1.6 GHz LO Example: 1.8 GHz GSM Specifications: IF carrier frequency = 246 MHz, Channel BW = 200 KHz, Input Dynamic Range = 90 dB . q 2 digital low frequency mixers, no noise and distortion. q Easier I&Q matching. q No DC offset and 1/f noise. Aliasing q More digital means easier integration on a CMOS process. q SNR degradation due to noise folding q ADC & SH have to run at high clock to minimize noise 20 folding. Sub-sampling Receiver: Basic Idea fs/4 fs/4 BW fs 2fs 4fs f IF=246MHz Aliased signal IF Signal to baseband • The sampling rate, fs, can be much less than the IF carrier. • But, fs > 2×BW must be satisfied (to avoid destructive aliasing). 21 Wideband IF Receiver: The mirror signal is different from the wanted signal. Image Rejection Architecture A D C D LNA 90 S A P D C HF LO PLL PLL LF LO 4 Allow for high level integration. 4 Relaxed RF PLL specification, VCO could be made on-chip. 4 Channel-selection performed by IF PLL lower the required divider ratio. 4 Good Multi-standard ability. 4 Alleviated DC offset problem. 8 Increase of 1dB compression point of second set of mixer. 8 Increased ADC dynamic range because limited filtering in comparison with the heterodyne receiver. 22 8 Feasibility has not been proven for GSM. Analog and Mixed Signal Center, TAMU Receiver Architectures Wideband Digital IF Receiver LNA AGC ADC DDC DSP PLL vMore digital parts allow for higher level integration. v Relaxed RF PLL specification. v No I&Q mismatch. v Good Multi-standard ability. v Increase of 1dB compression point of LNA and mixer. v Critical performance required of ADC. v High performance required of DSP. 23 Receiver Technology Trends Traditional Superheterodyne Increasing Integration Borrows from handset chip integration, or new architecture like direct-conversion. IF-Sampling/Digital I&Q Reduces receiver size by eliminating IF stages New architectures using more digital processing Multi-mode, Wideband Large reduction in receiver size Major architectures shift to DSP-intensive radio, highly programmable 24 Software Receiver LNA ADC DDC DSP Band Select High Intercept High Intercept Wide Dynamic Fixed Function Fast DSP Filter Point Amplifiers Point Mixers Range ADC DSP digitally with on-chip Remove Amplify signals translate digitize entire selects and Memory unwanted without the input spectrum spectrum for filters the demodulates spectrum introduction of to ADC signal digital channel channel of signal significant bandwidths selection interest intermodulation products 25 Analog and Mixed Signal Center, TAMU SOFTWARE RADIO Antenna Digital RF bitstream (1-2 GHz) LNA+ BPF VGA ADC DSP Ø Idea introduced in 1991 by Joe Mitola Ø Direct RF digitization Ø Single / multiple channels sets ADC BW Ø Reconfiguration by DSP software programs 26 SOFTWARE DEFINED RADIO Antenna IF RF (1-2 GHz) (100-200 MHz) Digital IF bit stream BPF LNA VGA ADC LO1 Ø IF digitization Ø No specific standard for IF location Ø Reduced DC offset, flicker noise problems 27 Literature survey Ref Type Fo Fs SNR Power Tech GHz GHz 1 MHz BW (mW) Vessal (JSSC 04) Nyquist (FI) 0 - 0.7 2 48 dB û3500 SiGe HBT Kaplan (CICC 03) CT BP S? 1.3 4.3 ü62 dB û6200 InP HBT Chandrasekaran SC LP S? 0.9 0.1 25 dB 30 0.25µm (CICC 02) with mixer (bad SNDR) CMOS Cherry (TCAS 2000) CT BP S? 1 4 51 dB 450 0.5µm SiGe Gao (VLSI 98) CT BP S? 1 4 48 dB 350 0.5µm SiGe Jayaraman (GaAs 97) CT BP S? 0.8 3.2 55 dB 1800 GaAs 28 Examples of Standards ( simplified versions) Bluetooth 802.11b (Wi-Fi) Data rate 1Mb/s 1-11Mb/s Power Lower Higher Modulation FH-GFSK DSSS-CCK Frequency 2.4 – 2.48GHz 2.4 – 2.48GHz Band 29 IEEE 802.15.4 (“Zigbee”) Parameter North America North America Europe Frequency 2402-2480 902-928 MHz 2412-2472 Range MHz MHZ Channel 5 MHz 5 MHz 5 MHz spacing Multiple access CSMA/CA CSMA/CS TDMA method Duplex method FDD FDD FDD Users per 255 255 255 channel Modulation OPQSK, OPQSK, GFSK,BT=0.5 BT=0.5 BT=0.5 Peak bit rate 250 kHz 40 kHz 250 KHz 30 Parameter 800 MHz 1900 MHz Asia Summary of IS-95 CDMA Mobile-to-base 824-849 MHz 1850-1910 1920-1980 frequency MHz MHz Base-to-mobile 869-894 MHz 1930-1990 2110-2170 frequency MHz MHz Channel 1250 kHz 1250 kHz 1250 kHz spacing Number of 20 48 48 channels Multiple access CDMA/FDM CDMA/FDM CDMA/FDM method Duplex method FDD FDD FDD Users per More than 15 More than 15 More than 15 channel Modulation QPKK/OQPSK QPKK/OQPSK QPKK/OQPSK Channel bit 1.2288 Mb/s 1.2288 Mb/s 1.2288 Mb/s 31 rate (chip rate) UMTS/DCS1800 Specifications DCS1800 UMTS Frequency Band 1805 - 1880 MHz 2110 - 2170 MHz Channel BW 200 kHz 5 MHz System Sensitivity -102 dBm -117 dBm(@32ksps) BER 1e-3 1e-3 600 - 800 kHz: -43 dBm 10 - 15 MHz: -56 dBm Blocking 800 - 1600 kHz: -43 dBm 15 - 60 MHz: -44 dBm Characteristics 1600 - 3000 kHz: -33 dBm 60 - 85 MHz: -30 dBm > 3000 kHz: -26 dBm > 85 MHz: -15 dBm Cochannel: -9 dBc Adjacent Channel 200 kHz: 9 dBc 5 MHz: -52 dBm Interference 400 kHz: 41 dBc 600 kHz: 49 dBc 32 Multi-Channel, Multi-Mode Dynamic Range (1) DCS1800 -15 dBm BW=2170-1805 BW=max(band) =365 MHz =75 MHz -99 dBm -114 dBm LNA Amp ADC 0 dBm -4 dBm 13 dBm -84 dBm -60 dBm -99 dBm -77 dBm Gain: 15 dB Gain: 10 dB Gain: 17 dB Fullscale Voltage: Input 1dB Input 1dB Input 1dB 2 Vpp compression: -13 dBm compression: 2 dBm compression: 0 dBm 33 Multi-Channel, Multi-Mode Dynamic Range (2) DCS1800 Blocker PB = 13 dBm PB CW carrier Wanted Signal Px = -60 dBm Px Noise PSD To ensure that the quantization noise power is negligible compared to that of In channel interferers and other sources of thermal quantization noise BW=200 kHz and device noise, choose SNRQF = 20 dB With Fs = 150 MHz, calculated resolution of ADC is 11 bits. The SFDR (for single blocker) can be calculated by: SFDR = PB - Px + SNRQF = 93 dB Required ADC Spec.: FS >= 150 MHz, b = 11, SFDR = 93 dB Current State of the art ADC: Fs = 80 MHz, b = 14, SFDR = 100 dB(AD6644) 34 How much Conversion Gain is required? LNA Amp ADC -26 dBm(DCS1800) 13 dBm -30 dBm(UMTS) • Between the antenna and the ADC, 39 dB(for DCS1800) or 43 dB (for UMTS) of power gain is required for a maximum signal to drive the ADC to full-scale. • However, since several signals could phase align, some guard-banding is needed. Since it is not very probable that multiple signals will phase align converter clipping is not likely. • Gain is distributed between the antenna and the ADC, low noise components should be used to maintain sensitivity, key specifications are Noise Figure and Third Order Intercept Point. 35 Sensitivity (DCS1800/UMTS) • The maximum signal -26 dBm(DCS1800) or -30 dBm(UMTS) is at FS, therefore SNR of the signal is : - DCS1800 68 + 28 = 96 dB (68 dB is from 11 bits ADC, 28 dB is from processing gain) - UMTS 68 + 15 +21 = 104 dB • Most processing algorithms require 10 dB SNR minimum for a reasonable bit error rate - Therefore, the -26 dBm signal can be reduced by 86 dB (96 - 10) for DCS1800 and -30 dBm signal can be reduced by 94 dB (104 - 10) for UMTS before too little SNR remains. • Sensitivity would be -112 dBm (-26-86) or -124 dBm (-30-94) minus NF and multi-carrier guarding. 36 REFERENCES [1] B. Leung, “VLSI for Wireless Communication” Prentice Hall, Upple Saddle River,NJ 2002 [2] T. Lee, The Design of CMOS Radio Frequency Integrated Circuits, Cambridge University Press, 1998. [3] C. Chien , Digital Radio Systems on a Chip, Kluwer Academic Publishers, Boston, 2001. [4] B. Razavi, RF Microelectronics, Prentice Hall, Upple Saddle River,NJ 1998 [5] A. Bensky, “ Short-range Wireless Communication: Fundamentals of RF System Design and Application”, 2 nd Edition, Amsterdam, -Newnes-Elsevier 2004 Analog and Mixed Signal Center- Texas A&M University (ESS) 37

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posted: | 10/15/2012 |

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Description:
• From stage to stage the desired signal is further and further
downconverted until the desired final IF is obtained.
• The ratio between the operating frequency before and after
downconversion is usually kept lower than 10, say 4. For instance
a 1800 MHz signal is first downconverted to a first IF of 450 MHz,
then consecutively to 90 MHz and finally to 18 MHz.
• Note that each downconvertion stage has the same mirror frequency
trouble than the single-stage IF receiver.
• Significant filtering between stages is required. This filtering is done
with off chip filters to further complicate the sensitivity to parasitic
components, also the power consumption will be high.

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