An IF Digitizing Receiver for a Combined GPS/GSM Terminal by YAdocs


									          An IF Digitizing Receiver for a Combined GPS/GSM Terminal

              K. Boehm*, T. Hentschel**, T. Mueller*, F.Oehler***, G.Rohmer***
*       Daimler-Benz Research Ulm, FT2/HM, Wilhelm-Runge-Str. 11, 89081 Ulm, Germany
**      Dresden University of Technology, Endowed Chair for Mobile Communications Systems
***     Fraunhofer Institute for Integrated Circuits, Erlangen, Germany

For the purpose of traffic telematics (route guidance, fleet management etc.) one needs terminals on the vehicle for the
quasi-simulteanuos reception of cellular phone (GSM) and satellite navigation (GPS). A conventional approach uses two
complete receivers for this two tasks. We describe a cost-saving solution for a combined receiver which relies on the TDM
structure of the GSM signal. Our solution is based on an bandpass-sigma-delta ADC for IF digitizing.

Key words: Traffic telematics, GPS, GSM, IF-digitizing, bandpass-Σ∆-ADC, combined receiver, decimation

Introduction                                                   to an IF of 44 MHz. The application of an image rejection
The ever increasing traffic density poses problems which       mixer was impossible due to the large bandwidth
can be partially solved by means of modern                     (935MHz-1575MHz). Two separate local oscillators (LO)
communication systems: Route guidance, collision               are switched alternately to the mixer (Motorola
notification, emergency call, stolen vehicle tracking,         MC13143). An improved version may be later on realized
roadside assistance, fleet- and traffic management as well     with a single, rapid settling (< 200 µs) LO. The mixer is
as road pricing are tasks of traffic telematics. For the       followed by a SAW-filter (Siemens X6959M) with a
purpose of traffic telematics one needs terminals on the       bandwidth of 2MHz in order to reduce intermodulation
vehicle for the quasi-simulteanuos reception of cellular       products in the variable gain amplifier and to prevent
phone(GSM)       and     satellite navigation(GPS).     A      aliasing in the ADC. For mobile applications power
conventional approach uses two complete separate               consumption is a critical issue. For IF-digitizing the
receivers for this two tasks. In order to reduce the           bandpass-Σ∆-ADC has the potential of lower power
complexity of the total set-up and therefore achieve a         consumption compared with other ADCs [Jan97]. The
reduction of volume, power and cost we propose a               choice of the IF is a compromise between the
solution with a combined receiver which relies on the          requirements on the ADC (low IF wanted) and the image-
TDM structure of the GSM signal.                               rejection filter (high IF wanted). Due to the prefiltering
                                                               with an bandwith of 2 MHz an instanteanuos dynamic
System Architecture                                            range of 70 dB is sufficient for the ADC. The GSM specs
The GPS and the GSM signals can be processed in the            require a (noninstaneuos) dynamic range of total 110 dB.
same signal processing chain from the antennas down to         The difference of 40 dB is supplied by the variable gain
the baseband. This is possible due to the time division        amplifier (RF2611) and the attenuators in the RF-part.
multiplex structure of the GSM signal. The GSM needs           In an first implementation (proof of principle) only the
3/8    of the available time slots which leaves an             GPS baseband processing is realized with a PC-based
appromately 50% duty cycle for GPS.                            evaluation board (12-channel receiver) from Plessey.
The set-up is depicted in the schematic of Fig. 1: The         From this board the RF-frontend is bypassed and the
signals from the antennas (GPS=1.575GHz, GSM=.935-             decimator output is connected directly to the correlator
.960GHz) become bandpass-filtered (ceramic-filter              chip GP 2021 on this board. The PC is used for control of
Murata) in order to suppress strong out of band signals        the correlator, calculation of the coordinates, control of
which could otherwise give rise to intermodulation or          the VCO and the variable gain amplifier and other system
blocking in the preamplifier (Siemens CGY59). After the        control tasks.
preamps variable attenuators (up to 20 dB) can be
activated by the system control. Two SAW-Filters               The Σ∆-modulator
(Siemens B4678) help to suppress the image frequencies.        Because only one IF-filter of 2 MHz (BW) is used for the
A SPDT-switch (MACOM SW-335) serves for the time-              combined reception of both standards (GPS, GSM), the
duplexing of the two signals. The signals are mixed down       modulator has to digitize the 200 kHz GSM-band with an
SNR of 70 dB in the presence of strong interferers in the        The total power dissipation of the modulator including the
neighbour channels. The maximum signal swing at the              clock buffer, the track and hold and the digital
input is 400 mV at an fIF = 43.875 MHz and fS = 19.5             cancellation filters is 150 mW on a 5 V supply.
MHz. Fig. 2 shows the block diagram of the modulator
architecture. It is an eighth order four stage 2-2-2-2           Base-Band Processing
cascade with a fourth order noise shaping function and 1         The base-band processing is realised by means of „off-
bit quantizers in each stage. The modulator output Y(z) in       the-shelf“ products, namely the Siemens GOLD GSM
the Z-domain is described ideally after digital cancellation     base-band processor and the Plessey GPS Correlator
as:                                                              GP2021. Since the ADC obeys the Software Radio
                                                                 principle, i.e. it digitises the GSM- as well as the GPS-
Y(z) = z-8 X(z) + (1+z-2)4 Q(z)                        (1)       signals, the digitised signals have to be adapted to the
                                                                 constraints defined by the interface specifications of the
where X(z) is the Z-transform of the signal and Q(z) the         two base-band processors. These constraints are given in
quantization error of the last stage.                            Tab. 1 together with the characteristics of the signal at the
                                                                 output of the ADC. Since the Plessey GPS correlator is
The cascaded structure was chosen to have no stability           flexible with respect to its master clock rate, however the
problems and less internal gain which is necessary to            GSM base-band processor has to be clocked with
maximize the ratio between signal swing and supply               13 MHz, the overall systems master clock has been
voltage and to reduce the power consumption thereby. The         selected to be a multiple of 13 MHz. Therefore, the
internal gain increases at higher orders and therefore the       figures for sample rate and center frequency for the
input signal swing must be reduced to keep distortion low.       Plessey GPS correlator are based on that common clock
                                                                 rate, but are not the standard values suggested by Plessey.
Track and Hold/Clock Buffer                                      The bandwidth of the signal at the output of the ADC is
To reduce the apertur jitter and the input impedance a           determined by an analog channel filter preceding the AD
fully differential, bipolar only track and hold (T/H) is         conversion
used in front of the modulator. For the IF-frequency of
43,875 MHz and the sampling rate of 19,5 Msps the                                ADC Output    Siemens GSM     Plessey GPS
linearity of the T/H is 72 dB. To realize a signal                Sample Rate    4.875 MHz     13 MHz          4.875 MHz
feedthrough in the range of 70 dB with the hold capacitor         Word Length    7 bit         1 bit Σ∆ mod.   2 bit
of 700 fF two transistor switches are combined in series.         Bandwidth      app. 2 MHz    200 kHz         app. 2 MHz
The integrated clock buffer delivers a clock signal with a        Center         DC            DC              1.219 MHz
swing of 500 mV for the T/H and two differential non              Frequency
overlapping CMOS clocks for the loop filters,                     Resolution                   10 bit          2 bit
comparators and transmission gates in the DAC.                   Tab. 1: Signal Parameters given at the Output of the
                                                                 ADC and required at the Input of the Base-Band
The Time Discrete Loop Filters                                   Processors
Fig. 3 shows the SC-implementation of the second order
bandpass filters using Forward Euler loops. The                  From Tab. 1 the functionalities of a circuitry that adapts
integrators of the filters are fully differential single stage   the output signal of the ADC to the two base-band
folded cascode amplifiers with a time continous common           processors is obvious. These are
mode feedback (CMFB) to keep switching noise low, as             • Scaling, conversion from two’s complement to sign-
shown in Fig. 5. The unity gain frequency of this OTA is             magnitude representation, and up-conversion of the
1.7 GHz with a phase reserve of 62 o . Due to different              signal in the GPS branch, and
loading conditions and to reduce the power dissipation 2         • Channelisation, up-sampling, and Sigma-Delta
versions with different transistor widths are used.                  modulation of the signal in the GSM branch.
                                                                 For reasons of power-consumption the filters for
Simulation Results                                               channelisation are implemented using CIC-filters [Hog81]
In Fig. 4 the simulated noise shaping function is shown.         and multiplier-free FIR filters (multi-rate filter
This is the result from a full Spice simulation with a two-      implementation). This is feasible, for mobile
tone signal, each in a distance of 600 kHz from the IF           communications signals are to a certain degree immune to
center frequency and with a signal power 12 dBm below            slight pass-band ripple of the filters. Moreover, the
the maximum input signal power. Because of the long              characteristics of the decimation filter at the input of the
simulation time which is needed, this spectrum is                GSM base-band processor has been incorporated to the
calculated by an FFT over only 3000 points.                      channelisation task, enabling a further simplification of
the adaptation hardware. Quantisation noise resulting from      rate systems on FPGAs at maximum clock rates of
rounding in the FIR- and CIC-filters at the input of the        approximately 40 MHz is still a problem, especially if the
Sigma-Delta modulator compensates for missing dithering         divided clocks are generated on the FPGAs. However, this
of the 1-bit-quantiser in the modulator. Since the signals at   internal clock generation is essential if scaleable and
the output of the filters still show the typical                parameterisable decimation filters have to be
characteristics of Sigma-Delta modulated signals, the           implemented, which will be the case in the next
rounding operations have to be chosen and placed                generation of such receivers as the GSM-GPS receiver,
carefully. Another block in the GSM branch is a digital         where there will be no longer two dedicated signal paths,
AGC, that scales the word-length of the filtered signal         but the Software Radio principle will be extended to the
depending on its strength, which itself depends on the          digital domain by using general hardware, which is
actual interferer situation at the input of the receiver.       programmable or parameterisable by means of software.
As to the GPS-branch the ratio between sample rate and
center frequency has been chosen to be a quarter. This          Acknowledgement
enables a simple up-conversion by a complex                     We would like to thank Dr. J.-F. Luy (Daimler Benz) for
multiplication of the signal with the sequences [1 0 -1 0]      initiating this project, helpful discussions and constant
and [0 1 0 -1], being the digital representations of the        encouragement. The authors are grateful to Mr. W.Sehr
cosine- and sine-function, respectively, at a quarter of the    and Mr. S. Urquijo (both Fraunhofer Erlangen) for their
sample rate. All synchronisation tasks of GPS are handled       efforts in the design of the Σ∆-converter
within the Plessey GPS processor.
In Fig. 6 the block-diagram of the signal-adaptation
circuitry is shown, indicating the multi-rate filter with the
                                                                [Jan97] S.A. Jantzi, R. Schreier, W.M. Snelgrove, " The
digital AGC and the low-pass Sigma-Delta modulator in
                                                                design of bandpass delta-sigma ADCs" in "Delta-Sigma-
the GSM branch, as well as the up-conversion, the scaling,
                                                                Data Converters: Theory, Design and Simulation", New
and the signal-representation conversion in the GPS
                                                                York, IEEE Press, 1997, ch. 9, pp. 282-308
The implementation of the signal-adaptation circuitry has
                                                                [Hog81] Hogenauer, E.B.: "An Economical Class of
been realised using FPGAs. However, the intended
                                                                Digital Filters for Decimation and Interpolation", IEEE
achievement in power consumption by using multiplier-
                                                                Trans. ASSP, Vol. 29, Apr. 1981, pp. 155-162
free multi-rate filters is only realisable with an ASIC
implementation. Actually, the implementation of multi-

Fig. 1: System Architecture of GSM/GPS receiver
In            +   -1/(1+z 2)   Comp.
     & Hold
                                       z -6    1+z -2

              +   -1/(1+z 2)   Comp.
                                       z -4   (1+z -2) 2
                    DAC                                        4 bit
                                                           +     Out
              +   -1/(1+z 2)   Comp.
                                       z -2   (1+z -2) 4

              +   -1/(1+z 2)   Comp.
                                       z -0   (1+z -2) 6

Fig. 2: Block diagram of the cascaded 8th order
bandpass Σ∆-modulator
                                                                       Fig. 4: Noise shaping for a two tone signal (fIF = +600
                                                                       kHz/-600kHz; 100 mVpp)

                                                                       Fig. 5: Schematic of OTA
Fig. 3: SC-implementation of 2nd order modulator

Fig. 6 : Block diagram of Signal Adaption Circuitry (decimation)

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