Fully Complementary CMOS Networks Complex Gates by alicejenny

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									EE 5900 Advanced
Algorithms for Robust
VLSI CAD, Spring 2009


 CMOS Combinational Gate
    CMOS Combinational Circuits
   Implementation of logic gates and other structures using
    CMOS technology.
   Basic element: transistor
   2 types of transistors:
       n-channel (nMOS) and p-channel (pMOS)
       Type depends on the semiconductor materials used to implement
        the transistor.
       We want to model transistor behavior at the logic level in order
        to study the behavior of CMOS circuits  view pMOS and nMOS
        transistors as swithes.




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CMOS transistors as Switches
     3 terminals in CMOS transistors:
      G: Gate
      D: Drain
      S: Source




    nMOS transistor/switch                          pMOS transistor/switch
     X=1 switch closes (ON)                          X=1 switch opens (OFF)
     X=0 switch opens (OFF)                          X=0 switch closes (ON)
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             Networks of Switches
   Use switches to create networks that
    represent CMOS logic circuits.
   To implement a function F, create a network
    s.t. there is a path through the network
    whenever F=1 and no path when F=0.
   Two basic structures:
          Transistors in Series
          Transistors in Parallel




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Transistors in Series/Parallel
nMOS in Series                                nMOS in Parallel
           a     a    Path between                         a         a     Path between
X              X:X    points a and b                                       points a and b
                      exists if both      X            Y                   exists if either
                                                               X:X   Y:Y
                      X and Y are 1                                        X or Y are 1
 Y             Y:Y     X•Y                                                 X+Y
           b     b                                         b         b

pMOS in Series                                pMOS in Parallel
           a     a                                         a         a     Path between
                      Path between                                         points a and b
 X             X:X’   points a and b
                                          X            Y                   exists if either
                      exists if both                           X:X   Y:Y
                                                                           X or Y are 0
                      X and Y are 0                                         X’+Y’
 Y                     X’•Y’
               Y:Y’
                                                           b         b
           b     b

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Networks of Switches (cont.)
         In general:
     1.     nMOS in series is used to implement AND logic
     2.     pMOS in series is used to implement NOR logic
     3.     nMOS in parallel is used to implement OR logic
     4.     pMOS in parallel is used to implement NAND logic
         Observe that:
           1 is the complement of 3, and vice-versa
           2 is the complement of 4, and vice-versa




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                CMOS Inverter
                                                       +V



           X         F = X’                   X             F = X’

           Logic symbol

                                                        GRD
                                          Transistor-level schematic

      Operation:
       X=1  nMOS switch conducts (pMOS is open)
        and draws from GRD  F=0
       X=0  pMOS switch conducts (nMOST is open)
        and draws from +V  F=1
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Fully Complementary CMOS Networks
            Basic Gates




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       Fully Complementary CMOS
              Complex Gates
Given a function F:
1.  First take the complement of F to form F’
2.  Implement F’ as an nMOS net and connect it to GRD
    (pull-down net) and F.
3.  Find dual of F’, implement it as a pMOS net and
    connect it to +V (pull-up net) and F.
4.  Connect switch inputs.




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Fully Complementary CMOS Networks
      Complex Gates - Example

            F = (A+B)(A+C’)
            F’ = A’B’+A’C=A’(B’+C)




 6-Oct-12                  Combinational Logic   PJF - 10

								
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