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                                       For UG and grad

Using SPICE find the threshold voltage and the noise margins of the an NMOS inverter having
an enhancement load transistor with size of 1.6um/1.6um and having a depletion mode
MOSFET load transistor with size 3.2um/.8 um.



For grad

Using SPICE find the threshold voltage and the noise margins of the an CMOS inverter having an
enhancement PMOS load transistor with size of 1.6um/1.6um and enhancement driver
transistor with size 3.2um/.8 um.



Ref book PP: 12-19

				
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posted:10/5/2012
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