CSS 372A Fall 2009

							                        CSS 372 Computer Architecture                              Fall 2009
Description: Covers the micro architecture level of machine design and advanced architecture features for performance
enhancement. Subjects include I/O, bus, memory and CPU design, hardware support for operating systems, CISC/RISC
architectures, and parallelism.
Purpose: To provide a better conceptual understanding of general purpose computer fundamental structural foundations
which offer the potential for leveraging, to improve the performance of computer programs and computer systems.
Educational Objectives:
This course builds on the material from TCSS 371 and:
     teaches students how modern computer hardware supports the design of operating systems,
     shows how the hardware can be customized to improve system performance,
     explains the differences between RISC and CISC processors,
     describes how the internal operations of a computer are controlled, and
     explains how peripheral devices communicate with a processor.
Educational Outcomes:
Upon successful completion of this course a student should be able to:
    explain how a processor responds to a requests for an interrupt,
    describe how the processor communicates with and controls peripheral devices,
    explain how physical memory is organized and how cache memory enhances memory performance,
    describe the primary differences between RISC and CISC architectures and instruction sets,
    explain how microprogram control units and hard-wired control units operate,
    create a new or modify an existing instruction within a processor,
    describe how parallelism is achieved within a processor,
    describe how a computer performs arithmetic operations, and
    explain how a processors architecture supports multitasking.
Topics Investigated:
   Number representation / accuracy
   Arithmetic Computation Hardware/Algorithms
   Finite State machines (States, Transitions, Outputs)
   Buses, timing, protocol / data transfer – Programmed, Interrupt driven, DMA/Channel Controlled
   Architecture / data flow / control sequencing
   Memory Organization (Internal & External)
   Stack / Stack Organization /Activation Records / Context Switches (Program Control, Interrupt, Task Switching)
   ISA Architecture – emphasis on RISC / CISC
   Control – Hardwired vs Microprogrammed (Horizontal, Vertical, Branch Control)
   Caching – Direct / Associative / Hybrid, L1/L2/L3 caches, Cache Coherence
   Operating System Support – Process Control (state model, queues) / Scheduling (Swapping, Multitasking) / Memory
      Management (Partitioning, Paging, Virtual Memory, Segmentation)
   Error Control (Hamming code)
   Pipelining, Hazards (Resource, Data, Procedural) and Hazard Control (Prefetch, Loop Buffer, Branch Prediction, Delayed
       Branch)
   Superscalar Machines (Multiple Pipes, Instruction Issue Policy, Register Renaming)
   IA/64 EPIC – VLIW, Bundling, Predication, Control Speculation, Data Speculation, Software Pipelining, Register Stacks
   Parallel Organizations – Multicore (very tightly coupled), SMP (symmetrical tightly coupled), NUMA (non symmetrical
       coupled), Cluster (loosely coupled), Multithreading
Final Exam Preparation:
    The following is a list of topics we have studied since the last Midterm, and those areas I suggest you concentrate
    your preparation for the final exam. Any “problems” on the final will be similar to those in your homework (solutions
    are posted). Also, remember that approximately half of the exam will be questions very similar to those on our two
    Midterms. I can be available Tuesday (at our regular meeting time?) to answer any questions/discussions. Let me
    know if that would be helpful to you. If so, I will "invite" everyone.

   RISC Specific Pipelining:
     Concentrate on the use of large register files.

   MIPS Pipelining Example:
     Concentrate on the MIPS Pipelined data paths and controls. Be able to explain/show how the control signals guide
   the instruction(s)/data through the pipe.

   Superscalar Machines:
    Concentrate on Instruction Issue Policy, Register Renaming

   IA/64 EPIC:
     Concentrate on understanding the concepts of Predication, Control Speculation, Data Speculation, Software
   Pipelining, Register Stacks

   Multithreading
    Concentrate on understand the relationship between processes and threads, and the benefits of multithreading.

   Hardwired vs Microprogrammed Control
    Concentrate on the distinction in methodology and the relative benefits. Understand the distinction between
   horizontal and vertical microinstruction formats.

   Parallel Organizations:
    Understand the distinctions of Multicore (very tightly coupled), SMP (symmetrical tightly coupled), NUMA (non
   symmetrical coupled), Cluster (loosely coupled) and their relative benefits.