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									   SWITCH-MODE POWER
  SUPPLIES AND SYSTEMS
                       Lecture No 10
            Switching transformer design rules.
        Power losses analysis in switching regulators



 Silesian University of Technology

  Faculty of Automatic Control, Electronics
           and Computer Sciences

Ryszard Siurek Ph.D., El. Eng.
                           Flyback converter transformer
                                                                                                  UIN
                                                                      IT               iT (t)        t
                                D1         I0                                                     Lp
                                          IC                                       Ipmax
 UIN                             UIN       C            R0
               Zp          ZS
                                  n             U0
                                                                                   t          B
               IT                                                                       BS
                    T
                        energy storing during cycle I
                                                                                  B
 UIN  zp d
                                                                                                             H
                      B  Se
          dt
 he nce:
                                                UIN  t
 UIN  zp  Se  dB  zp  Se  B      zp 
                 dt             t              B  Se
Minimum number of zP turns assuming t = tmax, B = Bs, UIN = UINmax:
                                                     UINmax  tmax
                                         zpmin 
                                                        Bs  Se
Assuming required output power equal to P0                           zpmin – is set for the chosen core
      2
   LpIpmax           2
                  LpIpmax
E          P0                                                                 lg   Lp   P0 
      2             2T             U2
                               P0  we t
                   U               2Lp
             Imax  we tmax                                                Certain air-gap is necessary to
                    Lp                                                     achieve required output power
  Cycle II   -    transistor T is off                             ID
                                                                                                                    U0
                                                                                                 iD (t)  IDmax       t
         ID D1         I0                                                     IDmax                                 LS
                      IC                                                                                T
         ZS U0         C        R0                                        t           t’            B
                         U0
                                                                                            BS
                                                             I2
                                                           LS Dmax
                                                    E2 
Energy stored in the core is trans-                           2
fered to the output during cycle II                                                                                        H
  E        2                              U0                                   U2
    2  LSIDmax  U I  P       IDmax         t'                      LS      0     t'2
          2T       00    0                                                    2P0 T
   T                                      LS
                         2
    Lp   2
        UIN t 2         zp  2
                           UIN t 2         zp U t                U t'
        2                2                 IN       zS  zp 0
    L S U0 t'2        z 2 U0 t'2           z S U0 t'             UIN t
                        S
Selecting t’ < T-t for the maximum output power Po one decides to work with the
discontinuous magnetic flux flow in the whole range of load changes. To increase t’
one must also increase LS, and it is related to higher number of turns of the secondary
winding zS. When t’ = T-t transformer starts to operate with continuous magnetic flux
flow.                               
                                       2
                                U 
                                 IN   2
For discontinuous                n            For continuous
                                    
                                                                       U0  IN 
flux flow                  U0                flux flow                   U
                                  2LpfI0                                     n 1 
             Flyback transformer design simplified procedure
1.    Select maximum (nominal) output power Po
2.    Select switching frequency – basing on specifications of available magnetic material,
      semiconductors etc.
3.    Calculate tmax, current Imax and required value of Lp
4.    Select core dimensions accordind to Hahn diagrams or using „AP” method (same as in
      inductor design procedure)
5.    Calculate (find from diagrams) the air-gap
6.    Calculate minimum number of primary turns, calculate required number of turns zP
7.    Select operating pronciple (continuous or discontinuous flux flow)
8.    Calculate secondary number of turns zS



     Usually discontinuous flux flow is observed in flyback converters due to the following
     reasons :
         -    lower number of winding turns (lower „copper” power losses)
         -    lower level of EMC disturbances (transistor switches on with current equal to 0)
         -    self-oscillating converter is very easy to design (low-cost solution)
                         Forward converter transformer
                                                                 Ip                              ΙS
           Ip                 IS
                                                                                                 n
                                                                       IM
     UIN        Zp       ZS US                                           Lp        US n



           transformer                                                equivalent circuit

                            UIN                 ΙS     UIN  t
                     IM        t       02                 Lp 
                            Lp         n                    I
                                                       0,2  S
                                                             n
1.   Selection of the core - basing on diagrams (nomograms etc.) relating core
     dimensions to total power for certain converter topology
2.   Calculation of minimum number of turns for the primary winding to avoid saturation
     in most unfavourable operating conditions
                                                     UINmax  tmax     Equation identical for any
                                         zpmin 
                                                        Bs  Se             converter topology

3.   Selection of wire cross section (diameter) taking into account primary current RMS
     value and calculation of number of turns for required winding inductance Lp (using
     Al constant for selected core) – the following condition must be performed: zp > zpmin
4.    Calculation of secondary winding (windings) number of turns

                                 zS                      U0 1
                        U0          UIN    z S  zp
                                 zp                      UIN 


 5.    Calculation of wire cross section area (copper strip, litz wire) for secondary winding
       resulting from secondary current RMS value ISrms=nIprms
 6.    Checking if it is enough space to place windings in the core (bobbin) window area –
       required isolation and winding arrangement according to safety standards must be
       considered

      secondary                                                           bobbin
      windind
                                                                           magnetic core
leakage distance
(6 mm)                                                                 Safety insulation
                                                                       (3 layers)
 primary
 winding




                                                                 functional insulation
                          3 mm
                                                                 (between winding layers)
                                    General notes
1.   Core power loses are higher when frequency and flux density amplitude increase -
     that is why the high value of primary inductance Lp is desirable
2.   High Lp value is related to more primary turns – more trouble with placing the winding
     in the bobbin and higher „copper” losses - look for optimum settlemet!
3.   Chose the magnetic core with best available performance – high saturation flux
     density Bs, lowest power losses, smallest dimensions
4.   Small air-gap in transformer core may be considered (forward converter) – better
     utilisation of the core may be achieved by lowering magnetic remanence


                                   B


      B - without air-gap
                                                             B - with small air -gap




                                                         H

5.   Remember that Bs value decreases with temperature – at 100oC it is lower by 20% – 25%
     in comparison to the value specified at 25oC
                     Switching regulator power losses analysis
1. Switching power losses (dynamic)

   UT                LL                L   IL       I0                      IL                  ILmax
            IT                                                                                                  I0
                               ID
      T
    UIN                            D           C Ro
                                                                                            t                    T
  Ucontr


            0                              t
                                                ILmax                                                    dIT
       IT                                                                                IRmax  2QR
                                                                                                          dt
    ILmin                                  ts
                                                                           QR - diode reverse charge [mC]
                td                                 tf    ILmax
                      ,
      ID             t1
                          t1
    ILmin



                                                         overvoltage due to leakage
      UT                  -IRmax                         inductance
     UIN

 ITrmsrds                                                                  Discharging of transistor capacitances CBCand CBE
                                                                           (bipolar transistors)

  Eloss
        Swith-mode power supply power losses - review

1.   Power losses in passive components
           - winding resitances (skin and proximity effects)
           - capacitor series resitance (ESR) – output filer electrolytic capacitors
           - magnetic core losses (hysteresis and eddy currents)
           - power losses in snubbar circuits
2.   Static power losses in semiconductors:
           - related to ON- resistance of MOSFET transistor or saturation voltage drop
             across bipolar transistor
           - related to voltage drop across rectifier diodes (mains input rectifier)
             and fast swiching output diodes

IMPORTANT!
     for bipolar transistors and diodes            for MOSFET trnasistors

                Ploss  Iav Uces                   Ploss  Irms rdson
                                                             2

3.   Switching (dynamic) power losses
          - related to semiconductor switching times, reverse charges
          - depandant on base (gate) drive circuits
           How to minimize power losses – general rules
1.   Power losses in passive components
           - select proper wire diameter, use copper stripes or litz wire
           - select low ESR capacitors (for switching applications), as big (dimensions)
             as possible, connected in parallel,
           - make wide and thick copper paths on the PCB
           - select modern ferrite cores with best performance at specified operating
             frequency and smallest dimensions
           - avoid high amplitude of flux density changes
           - recover the magnetising energy – do not dissipate it
           - use converter topologies with low overvoltages – decrease the influence of
             leakagae inductances (eg. two-transistor „forward” topology)
2.   Static power losses in semiconductors:
           - select MOSFET trnasistors with low on-resistance
           - in high power and high voltage applications use IGBT modules (simple
             MOSFET drive circuits, low saturation voltage drop as for bipolar transistors)
           - use Shottky diodes if possible (voltage drop below 0,5V)
           - use synchronous rectification technique



                                   After switching on the internal body diode the
                                   transistor with very low on-resistisance switches on –
                                   the voltage drop across the conducting transistor is
                                   much lower than across the diode
3.   Transistor dynamic power losses
           - select fast transistors (low tr anf tf times)
           - use special converter topologies with zero-current or zero-voltage switching
             (eg. resonant topologies)
           - design carefully snubbar circuits



                                                     Voltage UT rise without snubbar circuit

                                             IT
                           Zp
                CIN                          UT
                                                                  Charging of the capacitor
                                                                  delays voltage rise across the
       UIN                                                        switching transistor
                                   Cs                             decreasing significantly
                           IT
                                        UT                        transistor power losses
                           T                                              t
                                 Ds



     It is possible to select such value of the capacitor Cs, that the overall power loss in
     the transistor and snubbar circuit reaches minimum.

								
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