# Wires and Devices

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```					     EE 587
SoC Design & Test

Partha Pande
School of EECS
Washington State University
pande@eecs.wsu.edu
SoC Physical Design Issues

Wire Inductance
Wire Inductance

   Wide wires in clock distribution & upper level metal layers
   These wires have low resistance
   Exhibit significant inductive effects
   New materials with low-resistance interconnect
Inductance
   Complete interconnect model should include inductance
+   V    -
V=Ldi
R         i       L             C         dt
   With increasing frequency and a decrease in resistance due to wide
wires and the use of copper, inductance will begin to influence
clocks/busses:
Z = R + jL

   Inductance, by definition, is for a loop not a wire
   inductance of a wire in an IC requires knowledge of return path(s)
   inductance extraction for a whole chip is virtually impossible...
Evolution of Interconnect Model
Transmission Line Model

Inductance Effects
   Lumped RLC line
Vin                                                VO
VO = Zo         Vin
R                 L                  C                       Zt

Treat RC problem as a resistive divider:
1
sC                                     n = 1/sqrt(LC)
Zo
=
Zt                1                                        z=RC/2sqrt(LC) = damping factor
sC     + (R + sL)

1                                            n2
=                                       =
s2LC   + sRC + 1                          s2 + s2zn + n2

z > 1 we have two real poles (RC effects)
Poles are P1,2 = n [ z + sqrt(z 21)]
-                    z < 1 we have two complex poles (RLC effects)
Inductance Effects

Other Inductance Effects

   For most gates Ron is in the order of K so typically R >> jL
   response is dominant by RC delay for most signals
   Only the large drivers have a small enough Ron to allow the
inductance to control the dynamic response
   clocks
   busses
   For clocks, self-inductance term can dominate the response
(especially if shielding is used)
   For busses, mutual inductance term dominates and creates
noise events that could cause malfunction
   For power supplies, inductance can also be a problem due to
the Ldi/dt drop (in addition to the IR drop) as supplies scale
down
Capacitive and Inductive Noise

For most wires, jL < (Rwire+Rdrive) for the
frequency and R of interest. So, for delay, L is
R               L               C           not a big issue currently.
But L can be  20 - 30% of R so noise may be
seen on adjacent line (mutual coupling)

Dangerous scenario is a combination
of localized capacitive coupling noise and
long range mutual inductive coupling noise                                            +               -
R                L               C
-               +
R                L               C

R               L               C                           Return path current
R               L               C

R               L                C           Double noise events
Gate Driving an RLC Transmission Line
Propagation Delay

 C  CL ( Rt  Rtr ) 
L

he
time constantfor charging the load capacitance through t gate and wire resistance

Lt
Z ol        Characteri impedence of a lossless transmiss line
stic                              ion
Ct

 f  Lt Ct 
ion
Time of flight of the signals propagating across the transmiss line

Rt=Rl, Lt=Ll, Ct=Cl, CT=CL/Ct
Propagation Delay (Cont’d)

     50% propagation delay

2.9 1.35
(e              1.48 )               wn 
1
t pd 
wn                            Lt (Ct  CL )

1        Rt     Rtr  CL 
                            
2 1  CT ) 
 2Z ol Z ol  f 

• where ζ and wn are the damping factor and natural
frequency of the circuit
•Function of both the interconnect and gate impedance
Propagation Delay (Cont’d)

   If the ratio of the total resistance of the line to the lossless
characteristic impedance increases, inductive effects can be
neglected
   If the ratio of the driver resistance to the lossless characteristic
impedance increases, inductive effects can be neglected
   If the ratio between the time required to charge the load
capacitance through the gate and wire resistance to the time of
fight increase then inductive effects can be neglected
Effect of inductance on Signal Delay
Dependence of Delay on Interconnection Length

   If the gate parasitic impedances
(CL and Rtr ) are neglected then the
propagation delay can be expressed
as
0.37RCl 2

2
•For the limiting case where L →0, the above equation reduces to 0.37RCl
•For the limiting case R ->0, the delay is given by   l LC
Repeater Insertion revisited

•Lower repeater size and less number of repeaters
•The amount of inductance effects present in an RLC line depends on the ratio
between the RC and the LC time constants of the line
•As Inductance effect increases the LC time constant dominates the RC time
constant and the delay of the line changes from a quadratic to a linear
dependence on the line length.
•Optimum number of repeaters for the minimum propagation delay decreases
Inductance & Power Dissipation

   The dynamic power is given
Pdyn  CVDD f
2
as
   Increasing inductance effects
results in fewer number of
repeaters as well as smaller
repeater size
   Significantly reduces total
capacitance
   Faster rise time results in
lower short-circuit power
Inductance Extraction

   Inductance can only be defined for a closed current loop
   The inductance of the loop is proportional to the area of the loop
   At low frequency resistive impedance dominates
   Current uses as many returns as possible to have parallel resistances
   Situation is different at higher frequencies
Mutual Inductance

   Causes extra noise and delay effects

di1       di2
v1  L1      M
dt        dt
di1      di2
v2  M        L2
dt        dt
Inductive Noise in a bus

   Physically, a wide bus with all the lines switching in the same direction
behaves as one wide line
   Hence, the effective inductance of a line that is part of a bus is far
larger than the self-inductance of that line
   LC time constant of the line becomes much larger
L di/dt effects on the Power Supply
Antenna Effects

      As each metal layer is placed on the chip during fabrication,
charge builds up on the metal layers due to CMP1, etc.
      If too much charge accumulates on gate of MOS transistor, it
could damage the oxide and short the gate to the bulk terminal
+++++++++++
Metal 2
Metal 1
Areawire
+++++++++++++++++++++++++++
Antenna
Ratio =         Areagate
Poly                            This transistor could be damaged

      Higher levels of metal accumulate more charge so they are
more troublesome (i.e., metal 5 is worse than metal 1)
      Need to discharge metal lines during processing sequence to
avoid transistor damage (becomes a design/layout issue)
1. CMP is chemical mechanical polishing which is used to planarize each layer before the next layer is placed on the wafer.
Preventing Antenna Effects

   A number of different approaches for antenna repairs:
   Diode Insertion - Make sure all metal lines are connected to
diffusion somewhere to discharge the metal lines during
fabrication
+++++++++++++++++++++++++++     -diodes costs area
- need to optimize number
and location
n+                                   - causes problems for
p                                     design verification tool

Antenna diode
Preventing Antenna Effects

   Note that there are always diodes connecting to source/drain
regions of all transistors and charge on each layer is drained
before next layer is added…so why are we worried?

Should put antenna
diode here.

Keep area of upper layer metals
small near next transistor

   Gate input of next device may not be connected to a diode until
it’s too late…charge accumulation on metal exceeds threshold
Preventing Antenna Effects

   Second approach is to add buffers to interconnect to break up
long wire routes and provide more gate area for antenna ratio
   Third approach is to use metal jumpers to from one layer of
metal to another
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + ++++++++      ++++++++
Metal 1/polish

vias (charge removed)

++++

Metal2/polish
Class Presentation

   The first class presentation assignment will be posted soon.
   One of you has to present the basic concepts discussed in the
paper to the class
   Presentation time ~20 minutes
   After the presentation everybody has to participate in the
discussion

```
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