1 2 8085 architecture b

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					 Introduction to
Microprocessors
               AGENDA
• Architecture
• Microprocessor Communication and Bus Timings
• Demultiplexing Address and Data Lines
Architecture of 8085

 • Reveals the internal logic of a Microprocessor
 • 8085 Architecture consists of following blocks:
    –   ALU logic
    –   Register Logic
    –   Timing and Execution Logic
    –   Interrupt Logic
    –   Serial I/O Logic
Flag Register

          S     Z    X   AC    X      P   X    C


   Sign                                                 Carry


  Zero                                                   Parity

                    Auxiliary Carry


                                              X - Unspecified
Register Section
• General Purpose Registers
   • A, B, C, D, E, H, and L
   • BC, DE, and HL
• Special Function Registers
   • Program Counter
   • Stack Pointer
Timing and Execution Logic

                    Instruction
                     Register


                    Instruction
                     Decoder



              Timing and Control Unit



                  Control Signals
Interrupt Logic

• Consists of 5 interrupts with following properties:
   • Priority
   • Maskable and Non Maskable
   • Vectored and Non – Vectored
• INTA is an output signal
Serial I/O Logic
• Supports serial I/O using 2 lines
   • SID – Serial Input Data
   • SOD – Serial Output Data
Mp communication and Bus Timings - 1


 The instruction code 0100 1111 (4FH – MOV C, A)
     is stored in memory location 2005H. Illustrate
     the steps and the timing of data flow when it is
     being fetched
Mp Communication And Bus Timings - 2

                                             Data Bus
                    4F



        Internal Data Bus
                                                          Memory
                                                                   2000
                            B        C
          Instruction       D        E
  ALU       Decoder
                                                   2005     4F     2005
                            H        L

                                SP
                                PC


          Control                    Address Bus            4F

           Logic


                    RD
Timing Diagram
Demultiplexing Address & Data Lines
Probable Questions..
  Explain with a neat diagram, the architecture of
   8085 microprocessor
   Explain the flag register of 8085.
   With a neat diagram, explain how to separate
   multiplexed address and data lines in 8085.
  Explain opcode fetch machine cycle.
   What Signals are activated when I/O port at
   address ABCD H is read by 8085 ?

				
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posted:10/3/2012
language:English
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