VLSI JYO

Document Sample
VLSI JYO Powered By Docstoc
					    Introduction to VLSI Design
    Custom and semi custom design




DAVIET        Digital circuit logic Design   Slide-1
         IC Evolution (1/3)

     • SSI – Small Scale Integration (early 1970s)
        • contained 1 – 10 logic gates
     • MSI – Medium Scale Integration
        • logic functions, counters
     • LSI – Large Scale Integration
        • first microprocessors on the chip
     • VLSI – Very Large Scale Integration
        • now offers 64-bit microprocessors,
          complete with cache memory (L1 and often L2),
          floating-point arithmetic unit(s), etc.




DAVIET                Digital circuit logic Design   Slide-2
         IC Evolution (2/3)

     • Bipolar technology
        • TTL (transistor-transistor logic)
        • ECL (emitter-coupled logic)
     • MOS (Metal-oxide-silicon)
        • although invented before bipolar transistor,
           was initially difficult to manufacture
         • nMOS (n-channel MOS) technology developed in 1970s
           required fewer masking steps, was denser, and
           consumed less power than equivalent bipolar ICs => an
           MOS IC was cheaper than a bipolar IC and led to
           investment and growth of the MOS IC market.




DAVIET                  Digital circuit logic Design     Slide-3
         IC Evolution (3/3)

          • aluminum gates are replaced by polysilicon by early 1980
          • CMOS (Complementary MOS): n-channel and p-channel
          MOS transistors =>
          lower power consumption, simplified fabrication process
     • Bi-CMOS - hybrid Bipolar, CMOS (for high speed)
     • GaAs - Gallium Arsenide (for high speed)
     • Si-Ge - Silicon Germanium (for RF)




DAVIET                    Digital circuit logic Design   Slide-4
         VLSI Benefits




         •   Smaller Size
         •   Higher Performance
         •   Higher Functionality
         •   Higher Reliability
         •   Lower Power Consumption
         •   Design Security




DAVIET                 Digital circuit logic Design   Slide-5
         VLSI Design Styles (1/2)

     • Full-Custom ASICs
        • Some (possibly all) logic cells
          are customized and
          all mask layers are customized
     • Semicustom ASICs
        • All logic cells are predesigned
          (defined in cell library) and
          some (possibly all) of the mask
          layers are customized
        • Types:
          Standard-cell based and Gate-
          array-based ASICs



DAVIET                 Digital circuit logic Design   Slide-6
         VLSI Design Styles (2/2)

     • Programmable ASICs
       • All logic cells are predesigned and
            none of the mask layers are customized
          • Types: PLD (Programmable Logic Device) like
            SPLD, CPLD, and FPGA (Field Programmable Gate
            Array)




DAVIET                 Digital circuit logic Design   Slide-7
DAVIET   Digital circuit logic Design   Slide-8
         Full-custom ASICs (1/3)
 • Engineers design some or all of the logic cells, circuits, or layout
   specifically for one ASIC
    • Full-custom ICs are the most expensive to manufacture and to
      design
    • Manufacturing lead time (the time it takes just to make an IC – not
      including design time) is typically 8 weeks
 • When does it make sense?
    • there are no suitable existing cell libraries available
    • existing logic cells are not fast enough
    • logic cells are not small enough
    • logic cells consume too much power
    • ASIC is so specialized that some circuits must be custom designed
 • Trends: fewer and fewer full-custom ICs are being designed
   (excluding mixed analog/digital ASICs)



DAVIET                    Digital circuit logic Design     Slide-9
DAVIET   Digital circuit logic Design   Slide-10
         Full-custom ASICs (2/3)
    • Each circuit element carefully “handcrafted”
    • Huge design effort
    • High Design & NRE Costs
    • High Performance
    • Until Recently, Unthinkable
          Expensive Development
          Risky
          Special Skills
          Lack of Manpower
    • Justified in Only the Most Desperate Cases
    • optimize design, gain maximum speed, area
    • usually for large volume product, Typically used for
      high-volume applications

DAVIET                Digital circuit logic Design   Slide-11
                   Full-custom ASICs (3/3)


       • All layers are optimized for an embedded system’s
         particular digital implementation
          • Placing transistors
          • Sizing transistors
          • Routing wires
       • Benefits
          • Excellent performance, small size, low power
       • Drawbacks
          • High NRE cost (e.g., $300k), long time-to-market



 DAVIET
Vahid & Givargis             Digital circuit logic Design   Slide-12
         Semi-Custom


         • Design with Pre-Designed Building Blocks
           (Standard Cell)
               - Low Level Design
               +Minimized Needed IC Design Skills

         • Uses Pre-Implemented Layout (Gate Array)
              +Pre-Characterized and Tested
              +Minimize Tooling
              - Density Sacrifice




DAVIET                 Digital circuit logic Design   Slide-13
         Standard-Cell-Based ASICs (1/5)

     •   Cell-Based ASIC (CBIC) uses pre-designed cells
         (AND, OR gates, multiplexers, flip-flops, ...)
     •   Standard-cell areas are built of rows of standard cells
     •   Standard-cell areas can be used in combination with larger pre-
         designed cells (microcontrollers, or even microprocessors), known
         as mega-cells

     A cell-based
     ASIC (CBIC) die
     with a single
     standard-cell
     area combined
     with 4 fixed
     blocks




DAVIET                     Digital circuit logic Design     Slide-14
DAVIET   Digital circuit logic Design   Slide-15
  x1                                                                f2

  x2

  x3
                                                                    f1




         A section of two rows in a standard-cell chip


DAVIET            Digital circuit logic Design           Slide-16
           Standard-Cell-Based ASICs(2/5)
 • Characteristics
    • The layout of individual gates (standard cells) is pre-
         designed and stored in a library.
    •    custom blocks can be embedded;
         ASIC designer defines only the placement of the
         standard cells and the interconnect in a CBIC
    •    standard cells can be placed anywhere on a silicon =>
         all mask layers of a CBIC are customized
    •    manufacturing lead time is 8 weeks
    •    The chip layout can be created automatically by CAD
         tools because of the regular arrangement of logic gates
         (cells) in rows.




DAVIET                    Digital circuit logic Design   Slide-17
         Standard-Cell-Based ASICs (3/5)

     • Advantages
       • designers save time, money, and reduce risks using a
          predesigned, pretested, and precharacterized standard-cell
          library
       • standard cells in the library are constructed using full-custom;
          each standard cell can be optimized individually
          (for example, to maximize speed, minimize area, etc);
     • Disadvantages
       • time or expense of designing or buying the standard-cell library
       • time needed to fabricate all layers of the ASIC for each new
          design




DAVIET                    Digital circuit logic Design     Slide-18
         Standard-Cell-Based ASICs(4/5)

     •   Standard-cells are designed
         to fit horizontally together to form rows
     •   Internal construction of a cell




                                             - 25 microns wide (lambda is 0.25)
                                             - AB: abutment box
                                             - BB: bounding box
                                             - Power supplies: VDD, GND
                                             - Each different shaded and
                                             labeled pattern represents a
                                             different layer
                                             - Connections: A1, B1, Z

DAVIET                       Digital circuit logic Design       Slide-19
         Standard-Cell-Based ASICs (5/5)
                                                   - Interconnections
     • Routing the CBIC                            between cells use
                                                   spaces (called
                                                   channels) between
                                                   rows
                                                   - 2 separate layers of
                                                   metal interconnect
                                                   (metal1 and metal2)
                                                   running at right angles
                                                   to each other
                                                   - Feedthrough: refers
                                                   either to the piece of
                                                   metal that is used to
                                                   pass a signal through
                                                   a cell or to a space in
                                                   a cell waiting to be
                                                   used as a feedthrough

DAVIET              Digital circuit logic Design          Slide-20
         Gate-Array-Based ASICs

     • In gate-array-based ASIC
         transistors are predefined on the silicon wafer
          • Base cell – the smallest element that is replicated
          • Base array – the predefined pattern of transistors
     • Masked Gate Array (MGA): only layers which define the
         interconnect between transistors are defined by the designer
         using custom masks
     •   Designer chooses from a gate-array library pre-designed and
         pre-characterized logic cells (often called macros)
          .




DAVIET                     Digital circuit logic Design    Slide-21
DAVIET   Digital circuit logic Design   Slide-22
         Gate-Array-Based ASICs (1/4)

     • Since only metal interconnections are unique for MGA,
         we can use prefabricated wafers
         (with completed transistor layers)
         • the turnaround time is reduced to a few days or at most a
           couple of weeks
         • the costs for all the initial prefabrication steps for MGA
           are shared for each consumer => the cost of an MGA is
           reduced compared to FC and CBIC
     • Types: Channeled, Channelless, and Structured Gate Array




DAVIET                     Digital circuit logic Design   Slide-23
         Gate-Array-Based ASICs (2/4)

     •   Channeled gate array
         • we leave space between the rows of transistors for wiring
     •   Characteristics
         • only interconnect is customized
         • the interconnect uses predefined spaces between rows
         • manufacturing lead time is between 2 days and 2 weeks




DAVIET                       Digital circuit logic Design        Slide-24
          Gate-Array-Based ASICs (3/4)
  •   Channelless gate array (sea-of-gates
      or SOG)
      • there are no predefined areas set aside
          for routing between cells
      •   we customize the contact layer that
          defines the connections between metal1
          and transistors
      •   when use area of transistor for routing,
          do not make any contacts to the device
          underneath
  •   Characteristics
      • only some (the top few) mask layers
          are customized – the interconnect
      •   Transistor layers on the silicon wafer are
          first fabricated to produce a gate-array
          template.
      •   Connecting wires are then fabricated on
          the template to produce a user´s circuit.
      •   The technology is also known as a sea-of-
          gates technology
      •   manufacturing lead time is
          between 2 days and 2 weeks




DAVIET                            Digital circuit logic Design   Slide-25
         A sea-of-gates gate array


DAVIET     Digital circuit logic Design   Slide-26
                                                f1




         x1




         x2




         x3




              An example of a logic function in a gate array


DAVIET                  Digital circuit logic Design           Slide-27
         Gate-Array-Based ASICs (4/4)

  • Structured gate array or embedded gate array
         • combines features of CBIC and MGA
         • motivation: MGA has only fixed gate-array base cell;
           difficult and inefficient implementation of memory
         • we set aside some IC area and dedicate it to a specific function
           (contain different cells, more suitable for building memory cells, for
           example, or complete block, such as a microcontroller)
  •   Characteristics
         • only some (the top few) mask layers
           are customized – the interconnect
         • custom blocks can be embedded
         • manufacturing lead time is
           between 2 days and 2 weeks
         • problem: embedded function is fixed



DAVIET                           Digital circuit logic Design          Slide-28
            Semi-custom

          • Lower layers are fully or partially built
             • Designers are left with routing of wires and maybe
               placing some blocks
          • Benefits
             • Good performance, good size, less NRE cost than a
               full-custom implementation (perhaps $10k to $100k)
          • Drawbacks
             • Still require weeks to months to develop




 DAVIET
Vahid & Givargis           Digital circuit logic Design   Slide-29
         Programmable Logic (PLDs, FPGAs)

     • Pre-manufactured components with programmable
       interconnect
     • CAD tools greatly reduce design effort
     • Low Design Cost / Low NRE Cost / High Unit Cost
     • Lower Performance




DAVIET              Digital circuit logic Design   Slide-30
DAVIET   Digital circuit logic Design   Slide-31
         Programmable Logic Devices(1/2)

     • PLDs
       • standard ICs, available in standard configurations
       • sold in high volume to many different customers
       • PLDs may be configured or programmed to create
         a part customized to specific application
     • Characteristics
       • no customized mask layers or logic cells
       • fast design turnaround
       • a single large block of programmable interconnect
       • a matrix of logic macrocells that usually consists of
         programmable array logic followed by a flip-flop or latch




DAVIET                    Digital circuit logic Design     Slide-32
         Programmable Logic Devices(2/2)

 • Types of PLDs
     • PROM: uses metal fuse that can be blown permanently)
     • EPROM: used programmable MOS transistors whose characteristics
       are altering by applying a high voltage
     • PAL – Programmable Array Logic
          • programmable AND logic array or AND plane,
            and fixed OR plane
     • PLA – Programmable Logic Array
          • programmable AND plane
            followed by programmable OR plane
 • Depending on how
    the PLD is programmed
     • erasable PLD (EPLD)
     • mask-programmed PLD


DAVIET                       Digital circuit logic Design   Slide-33
         Field-Programmable Gate Arrays (FPGA)
 • FPGA
    • a step above the PLD in complexity;
      it is usually larger and more complex than a PLD
    • rapidly growing in importance
 • Characteristics
    • none of mask layers are customized
    • a method for programming basic cells
      and the interconnect
    • the core is regular array
      of programmable basic logic cells
      (combinational + sequential)
    • a matrix of programmable interconnect
      that surrounds the basic cells
    • programmable I/O cells around the core
    • design turnaround is a few hours



DAVIET                    Digital circuit logic Design   Slide-34
DAVIET   Digital circuit logic Design   Slide-35
DAVIET   Digital circuit logic Design   Slide-36
DAVIET   Digital circuit logic Design   Slide-37
DAVIET   Digital circuit logic Design   Slide-38
DAVIET   Digital circuit logic Design   Slide-39
         Economics of ASICs

     • Goal
        • discuss the economics of using ASICs in a product and
          compare the most popular types of ASICs:
          an FPGA, an MGA, and a CBIC
     • Warning!
        • costs change rapidly and IC industry is notorious for keeping
          its costs, prices, and pricing strategy closely guarded secrets,
          so the numbers we will use to illustrate the different
          components of cost are approximate
     • Part cost
        • vary enormously: from a few dollars to several hundreds
        • FPGAs are more expensive per gate than MGAs
        • MGAs are more expensive per gate than CBICs




DAVIET                     Digital circuit logic Design     Slide-40
    VLSI Design Cycle




DAVIET         Digital circuit logic Design   Slide-41
         VLSI Design Cycle (1/9)


           System Specification                   Circuit Design



           Architectural Design                 Physical Design



            Functional Design                      Fabrication


              Logic Design                          Packaging


DAVIET                   Digital circuit logic Design       Slide-42
         VLSI Design Cycle (2/9)

          System Specification – Specification of the size,
          speed, power and functionality of the VLSI system.
          Architectural Design – Decisions on the
          architecture, e.g., RISC/CISC, # of ALU’s, pipeline
          structure, cache size, etc. Such decisions can
          provide an accurate estimation of the system
          performance, die size, power consumption, etc.




DAVIET                  Digital circuit logic Design   Slide-43
         VLSI Design Cycle (3/9)

          Functional Design – Identify main functional units
          and their interconnections. No details of
          implementation.




DAVIET                  Digital circuit logic Design   Slide-44
         VLSI Design Cycle (4/9)

          Logic Design – Design the logic, e.g., boolean
          expressions, control flow, word width, register
          allocation, etc. The outcome is called an RTL
          (Register Transfer Level) description. RTL is
          expressed in a HDL (Hardware Description
          Language), e.g., VHDL and Verilog.




                     X = (AB+CD)(E+F)
                     Y= (A(B+C) + Z + D)
DAVIET                  Digital circuit logic Design   Slide-45
         VLSI Design Cycle (5/9)

          Circuit Design – Design the circuit including gates,
          transistors, interconnections, etc. The outcome is
          called a netlist.




DAVIET                  Digital circuit logic Design   Slide-46
         VLSI Design Cycle (6/9)

     • Net list:                              • Component list:
          net1: top.in1 in1.in                    top: in1=net1 n1=topin1
          net2: i1.out xxx.B                          n2=topin2 n3=topine
          topin1: top.n1 xxx.xin1                     out=outnet
          topin2: top.n2 xxx.xin2                 i1: in=net1 out=net2
          botin1: top.n3 xxx.xin3                 xxx: xin1=topin1 xin2=topin2
                                                      xin3=botin1 B=net2
          net3: xxx.out i2.in                         out=net3
          outnet: i2.out top.out                  i2: in=net3 out=outnet




DAVIET                       Digital circuit logic Design        Slide-47
         VLSI Design Cycle (7/9)


               Component hierarchy

                               top




               i1              xxx                  i2




DAVIET               Digital circuit logic Design        Slide-48
         VLSI Design Cycle (8/9)

          Physical Design – Convert the netlist into a
          geometric representation. The outcome is called a
          layout.




DAVIET                  Digital circuit logic Design   Slide-49
         VLSI Design Cycle (9/9)

          Fabrication – Process includes lithography,
          polishing, deposition, diffusion, etc., to produce a
          chip.
          Packaging – Put together the chips on a PCB
          (Printed Circuit Board) or an MCM (Multi-Chip
          Module)




DAVIET                   Digital circuit logic Design   Slide-50
         VLSI Design Cycle


           System Specification                            Netlist
         Architectural                                          Physical
               Design                                           Design

                Architectural                              Layout
                Specification          Circuit Design
                                             or                  Fabrication
           Functional
                                       Logic Synthesis
              Design
                                                            Chips
         Timing & relationship
         between functional units                               Packaging

               Logic                                 Packaged and
              Design                                 tested chips
                RTL in HDL

DAVIET                      Digital circuit logic Design             Slide-51
         VLSI Design Process




DAVIET            Digital circuit logic Design   Slide-52
         VLSI Design Process




DAVIET            Digital circuit logic Design   Slide-53
         VLSI Design Process




DAVIET            Digital circuit logic Design   Slide-54
         VLSI Design Process




DAVIET            Digital circuit logic Design   Slide-55
         The Hard Part

         •   A real design will have at least 1 million polygons and 100K
             transistors
         •   Mistakes are really expensive
              • A full set of masks for 0.13µ is about $600,000
         •   Any single error in any of the polygons can ruin the chip
         •   No one person can really comprehend 1 million of anything
              • Much less 1 billion
         •   Need to attack the problem with the standard engineering tools
              • Hierarchy and abstraction
              • Design reuse
              • Computer automation




DAVIET                        Digital circuit logic Design       Slide-56
         Design Methodologies and Flows
    • Left fork: Full custom
      design flow
    • Center fork: “Semi custom ASIC” flow
    • Right fork: System on Chip
      (SOC) flow




DAVIET                    Digital circuit logic Design   Slide-57
         Full Custom Design Flow
 • Has the best performance
 • Is the most labor intensive




DAVIET                    Digital circuit logic Design   Slide-58
         Schematic Capture/Simulation
         • Circuit drawn at transistor,
           gate, and block level
         • Blocks can be recursively
           placed inside one another
         • Utility programs produce
           netlists for simulation tools




DAVIET                      Digital circuit logic Design   Slide-59
         Layout


 • Draw and place transistors for all
   devices in schematic
 • Rearrange transistors to
   minimize interconnect length
 • Connect all devices with routing
   layers
 • Possible to place blocks within
   other blocks
    • Layout hierarchy should
      match schematic hierarchy




DAVIET                    Digital circuit logic Design   Slide-60
          Design Rule Checking (DRC)
         • Fab has rules for relationships between polygons in
           layout
            • Required for manufacturability
         • DRC checker looks for errors
            • width
            • space
            • enclosure
            • overlap
         • Violations flagged for later fixup




DAVIET                       Digital circuit logic Design   Slide-61
         Layout Versus Schematic (LVS)
     • Extracts netlist from layout
       by analyzing polygon
       overlaps
     • Compares extracted netlist
       with original schematic
       netlist
     • When discrepancies occur,
       tries to narrow down
       location




DAVIET                    Digital circuit logic Design   Slide-62
         Layout Parasitic Extraction (LPE)




         • Estimates capacitance between structures in the layout
         • Calculates resistance of wires
         • Output is either a simulation netlist or a file of interblock
            delays


DAVIET                       Digital circuit logic Design      Slide-63
         “Semi custom ASIC” Design Flow



 • Separate teams to
   design and verify
 • Physical design is
   (semi-) automated
 • Loops to get device
   operating frequency
   correct can be
   troubling




DAVIET                   Digital circuit logic Design   Slide-64
         Register Transfer Level (RTL)




         • Sections of combinational Goo separated by timing
           statements
            • Defines behavior of part on every clock cycle boundary


DAVIET                      Digital circuit logic Design        Slide-65
         Logic Synthesis



  • Changes cloud of combinational
    functionality into standard cells
    (gates) from fab-specific library
  • Chooses standard cell flip-flop/
    latches for timing statements
  • Attempts to minimize delay and
    area of resulting logic




DAVIET                    Digital circuit logic Design   Slide-66
         Standard Cell Placement and Routing




  • Place layout for
    each gate
    (“cell”) in design
    into block
  • Rearrange cell
    layouts to
    minimize routing
  • Connect up cells




DAVIET                   Digital circuit logic Design   Slide-67
         System on Chip Design Flow

  • Can buy “Intellectual Property” (IP) from various vendors
  • “Soft IP”: RTL or gate level description
     • Synthesize and Place and Route for
       your process.
     • Examples: Ethernet, MAC, USB
  • “Hard IP”: Polygon level description
     • Just hook it up
     • Examples: XAUI Backplane driver,
       embedded DRAM
  • Also: Standard cell libraries for ASIC flow




DAVIET                     Digital circuit logic Design   Slide-68
         CAD Design Flow for SPLD




DAVIET               Digital circuit logic Design   Slide-69
         FPGA Design Flow



                      Design Entry



                  Design Implementation



                    Design Verification



                   FPGA Configuration




DAVIET             Digital circuit logic Design   Slide-70
         Design Entry


               Schematic                     HDL


                              Compile



                           Logic Equations


                              Minimize                Test vectors


                              Reduced
                           Logic Equations             Simulation
                              (Netlist)



DAVIET                 Digital circuit logic Design            Slide-71
         Design Implementation

     • Input: Netlist Output: bitstream
     • Map the design onto FPGA resources
        • Break up the circuit so that each block has
            maximum n inputs
          • NP-hard problem
          • However, optimal solution is not required




DAVIET                  Digital circuit logic Design   Slide-72
         Design Implementation (Cont.)

     • Place: assigns logic blocks created during
       mapping process to specific location on FPGA
        • Goal: minimize length of wires
        • Again NP-hard
     • Route: routes interconnect paths between logic
       blocks
        • NP-hard




DAVIET               Digital circuit logic Design   Slide-73
         Design Implementation Techniques

     •   Simulated annealing
     •   Genetic algorithm
     •   Mincut method
     •   Heuristic method




DAVIET                Digital circuit logic Design   Slide-74
         Design Verification & FPGA Configuration

     • Functional Simulation
     • Timing Simulation
     • Download bitstream into FPGA




DAVIET               Digital circuit logic Design   Slide-75
         Advantages of FPLD compared with ASIC

     • A reduction in development time (rapid
       propotyping) by 3 to 4
     • In-circuit reprogrammability
     • Lower NRE costs resulting in more ecomomical
       designs for solutions requiring less than 1000 units




DAVIET               Digital circuit logic Design   Slide-76
          Comparison



          Technology   Performance/     Time until   Time to high   Time to change code
                       Cost             running      performance    functionality



          ASIC         Very High        Very Long    Very Long      Impossible




                                                                                          Flexibility
  Speed




          FPGA         Medium           Medium       Long           Medium


          ASIP/        High             Long         Long           Long
          DSP

          Generic      Low-Medium       Very         Not            Very Short
                                        Short        Attainable




DAVIET                             Digital circuit logic Design             Slide-77

				
DOCUMENT INFO
Shared By:
Categories:
Tags:
Stats:
views:0
posted:10/1/2012
language:Latin
pages:77