Device Isolation ppt

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					LOCal Oxidation of Silicon (LOCOS)
        Pad Oxidation

Pad oxide




            P-type substrate


                               2
       CVD Nitride


                  Pad oxide
Silicon nitride


          P-type substrate


                              3
    Photoresist Coating

Pad oxide

                         Photoresist
   Silicon nitride


             P-type substrate


                                       4
      LOCOS Mask



                      Photoresist
Silicon nitride


          P-type substrate


                                    5
LOCOS Mask Exposure



                       Photoresist
 Silicon nitride


           P-type substrate


                                     6
      Development



                      Photoresist
Silicon nitride


          P-type substrate


                                    7
        Etch Nitride



                      Photoresist
Silicon nitride


          P-type substrate


                                    8
   Strip Photoresist



Silicon nitride


          P-type substrate


                             9
    Isolation Implantation



    Silicon nitride
p                     p+
+

              P-type substrate


                                 10
        Thermal Oxidation



     Silicon nitride   SiO2
p+                      p+
                 P-type substrate


                                    11
     Strip Nitride




          SiO2
p+         p+
      P-type substrate


                         12
Sealed Interface Localized Oxidation (SILO)
             Why SILO..?

 The main limitations of the LOCOS process.

    Bird’s Beak : encroachment into the
     active region.
                 Why : Etching
            IntroductionSILO..?




.. To optimize the   Bird’s Beak profile
              SILO...contd...




 Seals the silicon surface under the nitride mask
  by nitridizing the silicon.

 This prevents the Bird’s Beak formation by
  blocking the lateral diffusion and reaction of
  oxidant molecules.
SideWAll Mask Isolation (SWAMI)
               SWAMI Process

• Step1 .(Pre Oxidation)
  – A thin oxide (Pad Oxide) layer is grown on the
    wafer.
  – To reduce the stress that occurs in the Si substrate
    during oxidation.




                                                       19
               SWAMI Process

   Step 2.
    – A layer of Si3N4 (Silicon Nitride) is
      deposited above the thin oxide layer.
    – The nitride act as the barrier to the
      diffusion of the oxidant preventing
      oxidation in selected regions of the Silicon.




                                                      20
              SWAMI Process

• Step 3.
  – The area in which the devices being fabricated is
    selected by lithography.




                                                        21
              SWAMI Process

   Step 4.
    – Etching the nitride and pad oxide layers.




                                                  22
              SWAMI Process


   Step 5.
    – Photoresist removal.




                              23
              SWAMI Process


   Step 6.
    – Silicon is etched to a depth of about half
      the desired oxide thickness.




                                                   24
            SWAMI Process

• Step 7.
  – Side Wall Masking.
  – Second nitride coating.




                              25
            SWAMI Process

• Step 8.
  – Thermal Oxidation for field oxide.




                                         26
Trench Isolation
         Trench Isolation

 Two methods.
    Shallow Trench Isolation

    Deep Trench Isolation
STI: Photoresist Coating



                          Photoresist


       P-type substrate


                                        29
STI: STI Mask Alignment



                          Photoresist


       P-type substrate


                                        30
STI: STI Mask Exposure



                      Photoresist


       P-type substrate



                                    31
STI: Etch Nitride



                   Photoresist


    P-type substrate


                                 32
STI: Etch Silicon



                   Photoresist


    P-type substrate


                                 33
STI: Channel Stop Implantation,
            Boron



    Photoresist
    Silicon                 Photore
                            Photoresist

                             Channel Stop
         P-type substrate    Implantation

                                            34
STI: Channel Stop Implantation,
            Boron




                            Channel Stop
         P-type substrate   Implantation

                                           35
    STI: CVD Oxide



CVD Oxide



                         Channel Stop
      P-type substrate   Implantation

                                        36
STI: Photoresist Coating


             PR
CVD Oxide



                        Channel Stop
     P-type substrate   Implantation

                                       37
STI: Oxide Etch Back




         CVD Oxide
                       Channel Stop
    P-type substrate   Implantation

                                      38
Deep Trench Isolation
        Deep Trench Isolation

• Area selection.
       Deep Trench Isolation

• DeepTrench formation.
        Deep Trench Isolation

• Channel stop Implant.
        Deep Trench Isolation

• Thin oxide coating.
         Deep Trench Isolation

• Polysilicon filling.
        Deep Trench Isolation

• Etching the surface polysilicon layer.
        Deep Trench Isolation

• Final oxidation above the trench.
Deep Trench Isolation
Deep Trench Isolation
Silicon on Insulator Isolation
                Introduction
- SOI – Silicon-on-Insulator

- Si layer on top of an insulator layer to build
  active devices and circuits.

- The insulator layer is usually made of SiO2
                Three methods

- Dielectric Isolation

- SIMOX (Separation by IMplantation Of
  oXygen)

- Wafer bonding
         Dielectric Isolation
Deep grooves are first etched in the
surface of the wafer.
                  Dielectric Isolation



• The wafer is oxidized and a thick layer of
  polysilicon is deposited.
               Dielectric Isolation



• The wafer is turned over and
  mechanically ground untill the groves
  penetrate through the wafer.
               BOX

SIMOX                    SIMOX
               silicon

        heat

				
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Description: Micro Electronic Technology (MET) Device Isolation ppt