COMPUTER ORGANIZATION & ARCHITECTURE by PLeIE5

VIEWS: 12 PAGES: 15

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                                         BC0040
       COMPUTER ORGANIZATION AND ARCHITECTURE
                                      [1 MARK EACH]

1. EDSAC stands for

a. Electronic display storage automatic calculator
b. Electronic delay storage automatic circuit
c. Electronic delay storage automatic calculator
d. Electronic display automatic circuit

2. The smallest machines are called as ______________

a. Microcomputers
b. Mini computer
c. Micromini computers
d. Mainframe computer

3. __________ computers are used for business data processing

a. Micro
b. Mini
c. Micro mini
d. Mainframe

4. ___________ defines the way in which the components of a computer are interrelated

a. Structure
b. Function
c. Architecture
d. Organization

5. _________ Refers to those attributes of a computer system which are visible to a programmer

a. Structure
b. Function
c. Architecture
d. Organization

6. _________ Refers to the operational unite of a computer and their interconnections and how
they implement the architecture of the system

a. Structure
b. Function
c. Architecture
d. Organization


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7. Structure of Babbage’s Difference Engine consists of ________

a. Number of registers
b. Number of Mechanical registers
c. Number of Electro mechanical register
d. Number of Electrostatic registers

8. Memory is a large ___________

a. Array of bytes
b. Array of bits
c. Stock
d. none of the above

9. The number of bits in each word is called as of the computer.

a. Word length
b. Word width
c. Word width
d. Word height

10. RAM is usually called ________

a. Physical memory
b. Logical Memory
c. Conceptual memory
d. Users Memory

11. Carry, Overflow, negative, zero result are also called ___________

a. Flag bits
b. Conditional bits
c. Status bits
d. None of the above

12. ________ is the core of CPU

a. CU
b. ALU
c. Memory
d. None of the above

13. Control Inputs tell the circuit _______ with the data

a. When do



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b. What to do
c. What and when to do
d. None of the above

14. ________ control unit determines the address of the next instruction to be executed and loads
it into program counter

a. Instruction Interpretation
b. Instruction sequencing
c. Instruction regulation
d. Instruction composition

15. A bus consists of _________wires

a. Exactly One
b. 0 or 1
c. 1 or less
d. 1 or more

16. There are _________ kinds of buses

a. One
b. Two
c. Three
d. Four


17. Which of them is a CPU register

a. PC
b. MAR
c. MDR
d. All of the above

18. _________ is a special purpose register designated to hold the result of an operation
performed by the ALU

a. PC
b. IR
c. MDR
d. ACC


19. Program counter is _________

a. User- visible required



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b. Control register
c. Status register
d. Data register

20. _______________ can be assigned to a variety of functions by the programmer

a. Data register
b. General purpose registers
c. Address registers
d. Index registers

21. Generals purples registers can be considered for

a. Orthogonal usage
b. Non orthogonal usage
c. Orthogonal and non-orthogonal usage
d. None of the above




22. Stock instructions like push, pop and others need not contain an _________ stock operand

a. Explicit
b. Implicit
c. Static
d. Dynamic

23. Condition codes are also referred to as ________________

a. Index register
b. Stock pointer
c. Segment pointer
d. Flag

24. PSW stands for

a. Program status word
b. Process status word
c. Program status width
d. process status width


25. Which of the operation is not performed by CPU

a. Fetch instruction



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b. Interpret instruction
c. Fetch data
d. Input data

26. Most popular computer architecture is :

a. The stock machine
b. Accumulator machine
c. Load/store machine
d. All of the above

27. The CPU of 8085 is organized around _____________

a. Multiple 16-bit internal bus
b. Single 8-bit internal bus
c. Single 16 bit internal bus
d. Multiple 8-bit internal bus


28. MBR stands for

a. Memory buffer register
b. Machine buffer register
c. Memory backward reader
d. Machine backward register


29. Stock pointer is a _________ register

a. 8-bit
b. 16-bit
c. 32-bit
d. 64-bit

30. ___________ is used as a high order 8 bits of MAR.

a. Data buffer
b. Memory buffer register
c. Address buffer
d. Address/data buffer


31. 8000 Machine consists of _________ 16-bit general purpose register

a. Eighteen
b. Sixteen



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c. Twenty
d. Nineteen

32. In which machine every register is a general purpose register

a. z8000
b. MC 68000
c. Intel 8085
d. Intel 8086

33. The processing required for a single instruction is called ____________

a. Fetch cycle
b. Execution cycle
c. Instruction cycle
d. Branch cycle

34. The fetched instruction is stored in the CPU register known as

a. IRC Instruction register
b. PC Program counter
c. MARC Memory address Register
d. MDRC memory Data Register


35. __________ instruction specify the require of execution is atttered

a. Control
b. CPU-memory transfer
c. CPU-I/O transfer
d. None of the above

36. I AC stands for

a. Instruction address circuit
b. instruction Address calculation
c. Interleaved address calculation
d. None of the above

37. IOD stands for

a. Instruction operand decoding
b. Instruction opcode decoding
c. Instruction operation decoding
d. None of the above




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38. OAC stands for

a. Operand Address calculation
b. Operator address calculation
c. Operation address calculation
d. None of the above

39. A computer consists of ______ basic types of modules

a. One
b. Two
c. Three
d. Four

40. Collection of paths connecting the modules is called _____________

a. Interconnection structure
b. Intercalated structure
c. Inter-related structure
d. None of the above

                                       [2 MARKS EACH]

41. I Address granularity is concerned for addresses that refers to the memory other than
registers
II. Address range is related to the number of address bits

a. I is true
b. II is true
c. Both are true
d. Both are false

42. I. If both numbers are positive and the result is negative, then report underflow
II. If both numbers are negative and the result is positive, then report overflow

a. I is true
b. II is true
c. Both are true
d. Both are false

43. I. For random access memory, Access time is the time taken to perform read or write
operation.
II. For non-random-accessing memory, access time is the time taken in positioning the read-
white mechanism at the desired location.

a. I is true



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b. II is true
c. Both are true
d. Both are false
44. I. A semiconductor memory constructed using bipolar transistors or MOS transistor stores
information in the form of a flip-flop voltage levels is called static RAM.
II. Semiconductor memory designed using MOS with a capacitor stores the information in the
form of charge on a capacitor is called dynamic RAM.

a. I is true
b. II is true
c. I & II both are true
d. Both are false

45. I. In look aside design of cache, the communication between CPU and cache is through a
separate bus, which is isolated from the main system bus.

II. In look through design both CPU and main memory are directly connected to the system bus.

a. I is true
b. II is true
c. I and II are true
d. I and II are false

46. During read or write operation.

I. Head is stationary
II. Platter rotates beneath it

a. I is true
b. II is true
c. Both are true
d. Both are false

47. An I/o module-

I. Is a mechanical connector that wire as device into the system bus.
II. They’re intelligent devices
III. Contains the logic for performing a communication function between the peripheral and the
bus.

a. I & II are true
b. II & III are true
c. All are false
d. All are true

48. ________ and ________ always occurs in every instruction cycle



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a. Fetch & Indirect
b. Indirect & execute
c. Execute & Interrupts
d. Fetch & execute

49. The control unit issues control signals:
I. Internal to the processor to move data between registers, to cause ALU to perform a specified
functions and to regulate other internal operations.
II. External to the processor to cause data exchange with memory and I/O modules.
a. I is true
b. II is true
c. Both are true
d. Both are false

50. I. Control unit causes the CPU to step through a series of micro operations in proper
sequence based on the program being executed.
II. The control unit causes each micro-operation to be performed.

a. I is true
b. II is true
c. Both are true
d. Both are false

51. The control unit issues control signals:
I. Internal to the processor to move data between registers, to cause ALU to perform a specified
functions and to regulate other internal operations.
II. External to the processor to cause data exchange with memory and I/O modules.

a. I is true
b. II is true
c. Both are true
d. Both are false

52. Von Neumann Architecture is based on

I. Data and Instructions are stored in multiple read write memory.
II. The content of this memory is addressable by location, with regard to the type of data
contained there
III. Execution occurs in a non sequential fashion unless explicitly modified from one instruction
to the next

a. I, II are true
b. II, III, are true
c. All are true
d. All are false



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53. I user visible registers enables the machine or assembly language programmer to minimize
main memory references by use of registers
II. Control and status registers are used by the control unit to control the operation of the CPU
and by privileged operating system programs to control the execution of programs

a. I is true
b. Only II is true
c. Both are true
d. Both are false

54. I. Data registers can be used to hold data
II. Data registers can be used in calculation of an operand address

a. I is true
b. II is true
c. Both I and II are true
d. Both I & II are false

55. I Index registers are used for index addressing
II. Index registers may be auto Indexed

a. Only I is true
b. Only II is true
c. Both I and II are true
d. Both I and II are false

56. The instruction cycle consists of ____________ and __________ cycle

a. Fetch & execution
b. Execution and Branch
c. Branch & Fetch
d. None of the above

57. Data may be transferred to/from the outrside word by transferring between ________ and
_________

a. CPU-Memory
b. CPU-I/O
c. PC to IR
d. None of the above

58. PCI is a ________ bit interface in a _____

a. 32,64
b. 64,64



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c. 32,32
d. 64,32

59. I if MSB is 1 the number is considered as negative
    II. If MSB is 1 the member is considered as +ve

a. I is True
b. II is true
c. Both are true
d. Both are false

60. I. Packed decimal strings have a length from 1 to 16 bytes with 4 bits holds the sign

II. Un packed numeric strings stores 1 digit in ASCII representation, per byte upto 31 bytes of
length

a. I is true
b. II is true
c. Both are true
d. Both are false

                                        [4 MARKS EACH]

61. Arrange in ascending order

I. The computer accepts information through the input unit and transfers it into the memory

II. All activities inside the machine are controlled by a control unit.

III. Processed information is transferred to the output unit

IV. Information stored in the memory is fetched into arithmetic and logic unit to perform the
desired operations

a. I, II, III, IV
b. I, III, IV, II
c. I, IV, III, II
d. I, IV, II, III


62. Match the following:

I. PC                          A. It contains a word of data to be written to I/O device
II. IR                         B. Contains the address of a I/O
III. I/o AR                    C. Contains an address of an instruction to be fetched
IV. I/O BR                     D. Contains the instruction most recently fetched



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a. I:C,II:D, III:B, IV:A
b. I:A,II:D, III:D,IV:B
c. I:D,II:C, III:B, IV:A
d. I:B,II:A, III:C,IV:D


63 Match the following:

A code segment                I where the data is placed
B data segment                II acts like a stock
C stock segment               III where the code is written

a. A:I, B:II, C:III
b. A:III, B:I, C:II
c. A:II, B:III, C:I
d. None of the above

64. Match the following:

A. Sign flag                         I. Set if logical compare result is equality
B. Zero flag                         II. Contains the sign bit of the result of the last
                                         arithmetic operation
C. Equal flag                        III. Sets when the result is O
D. Overflow flag                     IV. Used to indicate arithmetic overflow


a. A:I, B:III, C:IV, D:II
b. A:II, B:III, C:IV, D:I
c. A:II, B:III, C:I, D:IV
d. A:III, B:II, C:IV, D:I

65. Arrange the instructions in increasing order for the instruction ADD B.

A. ALU performs the add operation on its inputs
B. ALU updates the flags to reflect the results of the add
C. Control unit moves the contents of register B to the temporary register
D. The result is places on the internal CPU bus and copied into accumulator

a. A,B,C,D
b. D,C,B,A
c. C,A,B,D
d. C,A,D,B

67. Arrange in increasing order for execution cycle




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a. Set status flags attached to the CPU
b. Decode the instruction
c. Perform the required calculation
d. Store results in registers of memory

a. A,B,C,D
b. D,C,B,A
c. C,D,B,A
d. B,C,D,A

68. Arrange in increasing order the sequence of operations that takes place in memory write
operation

a. It sees the input control signal is MW
b. The position of memory is located using the input address
c. The input data is placed in the location of the memory
a. A,B,C
b. B,C,A
c. B,A,C
d. A,C,B

69. Match the following types of transfers between the modules:

I. Memory to CPU                      A. The processor sends data to the I/O device
II. I/O to CPU                        B. Processor reads data from I/O device a an I/O
                                         Module
III. CPU to I/O                       C. Processor reads an instruction or a unit of data
                                          from memory
IV CPU to memory                      D. The process or writes a unit of data to memory

a. I:C, II:B, III:A, IV:D
b. I:A, II:D, III:C, IV:B
c. I:B, II:C, III:A, IV:D
d. I:D, II:B, III:A, IV:C

70. Match the following
A: Serial trans mission               I less costly
B: Paralled trans mission             II more costly
                                      III. Low speed
                                      IV. High speed
                                      V. Low through put
                                      VI High through put

a. A:I, III, V B:II, IV, VI
b. A:II, IV, VI B:I, III, V
c. A:I, IV, VI B:II, III, V



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d. A:II, IV, V   B:I, III, Vi

71. Arrange the following in increasing order the steps of actions that are performed so that
address and data information may be transmitted over the same set of lines

A Each module is given sufficient period of time to copy the address and determine if it is the
addressed module
B. The address is placed on the bus with the ALE line activated
C. The addresses removed from the bus and then same bus connections are used for subsequent
read and write data transfer with the ALE signal deactivated

a. A, B, C
b. B, C, A
c. B, A, C
d. C, A, B


72. Match the following

A. Operation Code                     I. Tells the CPU where to fetch the next instruction
                                       after the execution of current instruction is
                                      complete
B. Source operant Reference           II. Stores the results produced by the operated
C. Result operand Reference           III. Operands that are the inputs for the operation
D. Next instruction Reference         IV. The operation specified by a binary code

a. A:I, B:II, C:III, D:IV
b. A:IV, B:III, C:IV, D:I
c. A:III, B:I, C:IV, D:II
d. A:II, B:IV, C:I, D:III

73. Arrange in sequence for the instruction
       X=X+Y
Where X is stores at 624 and Y is stored at 625

a. Store the contents of register in memory location 624
b. Load a register with contents of memory location 624
c. Add the contents of memory location 625 to the register

a. B, C, A
b. A, B, C
c. C, B, A
d. B, A, C

74. Match the following instructions and their operations




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A. data processing                          I. I/O instructions
B. Data Storage                             II. Test & Branch instructions
C. Data movement                            III. Arithmetic & logic Instructions
D. Control                                  IV. Memory Instructions

a. A:I, B:II, C:III, D:IV
b. A:IV, B:III, C:II, D:I
c. A:III, B:IV, C:I, D:II
d. A:II, B:I, C:IV, D:III

75. Match the following:

A. Operation Repertoire                     I. How many and which data upon which
                                               operations are performed
B. Instruction format                       II. The mode or modes by which the address
                                                of an operand is specified
C. Addressing                               III. Various types of data upon which
                                                 operations are performed
D. Data types                               IV. Specifies Instruction length, number of
                                                 addresses etc


a. A:I, B:IV, C:II, D:III
b. A:I, B:II, C:III, D:IV
c. A:IV, B:III, C:II, D:I
d. None of the above




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