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					       EE 715
Final Design Review

 Temporary Memory
    Goffredo Marocchi
     Robert Bogucki
Project Objectives
   100 MHz SRAM block
       Up to 4,096 words.
       32 bits word-length.
       Separate Input and Output pins.
       0 cycles load-use penalty for CPU memory
        accesses.
       Synchronous design.
Project Objectives (cont.)
Project Objectives (cont.)
   I/O pin-out:
       12 bits address bus.
       32 bits Input bus.
       32 bits Output bus.
       Vdd, GND, CLK and RE/we_n pins.
       A total of 80 pins are needed: we have 40
        available.
   Size limitations ?
Project Status
   Sub-modules have been laid out, tested
    and verified:
       The majority of components have been
        custom designed and routed for optimal
        size and performance.
       Control Logic was designed at the logical
        level and laid out automatically using
        Mentor Graphics’ IC Station.
Project Status (cont.)
   The sub-modules have been integrated
    as a system.
   Final Timing analysis and Pad-frame-to-
    chip connection need to be performed.
Floorplan


Floor-plan
   Why custom-layout ?
       Pro’s:
            Very Compact design (SRAM array is ~1/4 of
             the total available area and about the same
             size as the control logic).
            Closer to optimal routing and ports layout.
       Con’s:
            Very Time consuming: a large part of the our
             R&D time was spent manually laying out and
             routing sub-components.
Floor-plan (cont.)
   Sub-components’ physical layout and
    logical layout:




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Row Decoder
Row decoder (cont.)
Row-decoder (cont.)
Read_write logic
Read_write logic (cont.)
Tree-decoder logic
Tree-decoder (cont.)
Tree Decoder (cont.)
Control logic
Control Logic (cont.)
References and Thanks
   EE 715 Introduction to VLSI Text-book.
   Google.
   EE 612 Computer Architecture Text-
    book.
   The EE 715 VLSI forum and all the EE
    715 project teams.

				
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posted:10/1/2012
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