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System in Package SiP SoP Packaging

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System in Package SiP SoP Packaging Powered By Docstoc
					Package Trends for Today’s and
Future mm-Wave Applications
Maciej Wojnowski, Klaus Pressel, Grit Sommer, Mario Engl
Outline


    Introduction

    Package Overview

    Thin Small Leadless Package (TSLP)

    Embedded Wafer-Level Ball Grid Arry (eWLB)

    Through Silicon Vias (TSV)

    Experimental Results

    Conclusion

                                                 Page 2
Outline


    Introduction

    Package Overview

    Thin Small Leadless Package (TSLP)

    Embedded Wafer-Level Ball Grid Arry (eWLB)

    Through Silicon Vias (TSV)

    Experimental Results

    Conclusion

                                                 Page 3
Introduction

                Increasing industrial demands

                          Functionality
                       (System Integration)



               Speed                          Size

                               Cost &
                               Time to
                               Market




           Thermal                             Low/High
         Performance                            Power
                         Reliability &
                        Failure Analysis

                                                          Page 4
Package Evolution
Until Today and Towards Tomorrow
                                                                 22 mm
                                                                                               Functionality
                                                                                               Functionality
                P-DIP                                                                      Ele
                                                                                          Th ctric
                                                                                            erm al P
                                                                                                al    e
                                                                 13 mm
                                                                                                   Pe rform
                                                                                               Pin rfo
                                                                                                   Co rma ance
     Package Downsizing




                                           P-TQFP                                                    un   nc
                                                                 9,34 mm                                t    e
                                                           BGA

                                                                                                 System Integration
                                                                                                 System Integration
                                   P-TSOP I/II                                       Modules
                                                 Chip Scale
                                                 Chip Scale                           (SoB)
                                                  Package
                                                  Package                                     System in Package
                                                                                                   SiP/SoP
                    Packing                                      Flip-Chip
                                                                 Flip-Chip              3D-Packaging
                    Packing
                     Size                                         - in Package
                      Size                                        - on Board

      1st                                    2nd                     3rd                    4th
   Evolution                              Evolution               Evolution              Evolution       Technology
   THT                    SMD            SMD        Grid Array             High performance
                          (Peripheral)              (Area)
                                                                           Stacked Chips /3D Packaging
                                                                           Wafer Level Packaging


                                                                                                                      Page 5
Packaging – Growing Challenges

IC Chip – Peripheral Pad Pitch                                                   Frontend
                                                                                 Waferfab
(100    30 µm)


                                      Thermal            Size of
                                     interface         component
                           RF-                                          Cost
                                                                                 Backend
                       Performance
                                                                                 Production
Package as Interposer                      Interconnect
Bridging the        Electrical                 Gap                             Shielding
                    interface
Interconnect Gap
                            Environmental                           Reliability &
                              protection         Signal interface Failure Analysis
Customer Board                                      (Sensors)

(1000    500 µm)
in special cases                                                                 Customer
400µm, but high
board cost!!

                                                                                           Page 6
Semiconductor Development
Impact on Packaging
                Wireless
                                                                                                                                Automotive
                                                                                Analog/RF                                                                                  Medical
                                                                                     More than Moore: Diversification

  2008                                                                                                                   HV               Sensors
                                                                            Analog/RF   Passives                                                                 Biochips
                                                                                                                        Power            Actuators
                                 Baseline CMOS: CPU, Memory, Logic
   More Moore: Miniaturization




                                                                     130nm                                     Interacting with people and
  Logic                                                                                                                environment
  DRAM                                                                                  Co
                                                                     90nm                    m                           Non-digital content
  Flash                                                                                          bi                      System-in-package
                                                                                                    n   in
                                                                                                           g                   (SiP)
                                                                     65nm                                      So
                                                                                                                    C
                                                                              Information                               an
                                                                                                                           d
                                                                     45nm      Processing                                      Si
                                                                                                                                 P:
                                                                                                                                      Hi
                                                                             Digital content                                            gh
                                                                     32nm                                                                  er
                                                                             System-on-chip                                                   V   al
                                                                                  (SoC)                                                              u   e
                                                                     22nm                                                                                    Sy
                                                                       .                                                                                        st
                                                                       .                                                                                          em
                                                                       .
                                                                       V                                                                                               s



                                                                       Beyond CMOS
                                                                                                                                                                                     Page 7
Technology for System in Package:
Infineon’s Technology Tree for BGA type
                                             MCM
             side-by-side
                             passive
                                             Modules
                             integration




                                                              Increasing integration density
                                                 WB/WB

                                                 FC/ WB

    >1 die                                       >2 dies


                                       F2F       µ-FlipChip
                            stacked
                              die             Si thru hole

             stacked
                            stacked        Pack. on Pack.
                            package
                                           Pack. on SiP


             embedded                              eWLB

                                                                                               Page 8
Trends in Packaging: System-in-Package

Laminate based
BGA
                                                  Form Factor
                                             Interconnect Size, Cost
Today




Tomorrow
                             L       C




Embedded Wafer Level BGA
impedance-matched low loss TLs, integrated
passives (L, C)
                                                                   Page 9
Outline


    Introduction

    Package Overview

    Thin Small Leadless Package (TSLP)

    Embedded Wafer-Level Ball Grid Arry (eWLB)

    Through Silicon Vias (TSV)

    Experimental Results

    Conclusion

                                                 Page 10
Package Overview/Evolution


   THD through hole              SMD gull wing          SMD solder balls         SMD leadless
    DIP, TO 220                   SO, QFP                   BGA                   VQFN, TSLP

 Dual Inline Plastic Package    Small Outline             Ball Grid Array
                                Quad Flat Package                             Very thin Quad Flat No Lead
                                                                              Thin Small Leadless Package




Pitch: 2.54mm                  DSO-Pitch: 1.27mm             Pitch:             Pitch:
                               SSOP-Pitch:               1.5...1.27...1.0mm     0.8, 0.65, 0.5 mm
                               0.65...0.5mm                                     [0,4; staggered lands]
                                                        0.8…0.65...0.5mm
                               QFP-Pitch.
                                                        [0.4…0,3]
                               0.8...0.65...0.5...0.4mm




                                                                                                     Page 11
Technology Development & Package
Development
    Processes
      Thinning and Dicing
      Die attach
      Wire bonding                                                               Materials&Substrates
      Flip chip in Package                                                         Green
      Molding                                                                      Laminate substrates
      Thin film technology                                                         (xBGA)
      WLP processes                                                                Leadframes (TSLP,
      …                                                                            UFLGA, VQFN, ...)

    Physics of Package
      Signal Integrity                                                           Methods/CCN
      RF capability                                                                Co-design
      Heat dissipation                                                             Simulation&Modeling
      Reliability Physics                                                          BDR
      FA incl. adhesion                                                            Test
      Miniaturisation                                                              KGD
      Power                           System in                Integration
                                                                                   Standards
                                       Package                   enabler




                             Leadframe       Leadless
                                                        Laminate        WLB
                             Packages        Package
                                                s


      Package
       Package                 QFP                QFN   BGA/SGA/LGA    SG-WLB
                               DSO
      Platforms
      Platforms               TSSOP
                                                         RF-Modules    PG-eWLB



                                                                                                   Page 12
Outline


    Introduction

    Package Overview

    Thin Small Leadless Package (TSLP)

    Embedded Wafer-Level Ball Grid Arry (eWLB)

    Through Silicon Vias (TSV)

    Experimental Results

    Conclusion

                                                 Page 13
The Leadless Package Concept TSLP

 TSLP – Thin Small Leadless Package
   Leadless package based on a leadframe concept
   Low to medium pin count (< 80 I/Os)
   Green package
   Wirebond and Flip-Chip capabilities


 Main advantages
   Small dimensions (few mm)
   Short interconnects
   Excellent RF capabilities
   Improved thermal
   performance
                                                   Page 14
The Leadless Package Concept TSLP

                                     Die
 Au - Layer              Cu Leadframe         NiAu Contact
                                                             2a. Flip-Chip Bonding



 Ni - Bump    50 µm          1. Die Bonding

                                                               2b. Wirebonding




                                                              4. Copper Removal
                             3. Molding                          and Final Plating




                             5. Singulation                    6. Electrical Test 15
                                                                                Page
The Leadless Package Concept TSLP

 Flexible leadframe concept
   Typical padsizes range from 100 µm to 300 µm
   Nearly arbitrary pad geometries
   ¬ Circular
   ¬ Rectangular
   ¬ …
   Improved thermal performance
   Power / GND supply




                                                  Page 16
Wirebond Interconnects – Wire Length
Variation

            0
            -5
           -10
           -15
           -20
S11 [dB]




           -25
           -30
           -35                                                             0

           -40                               l = 1000 µm
                                             l = 600 µm                    -1
           -45                               l = 300 µm
           -50
                                                                           -2
                 0   10         20          30             40

                                                                S21 [dB]
                          Frequency [GHz]
                                                                           -3


                                                                           -4
                                                                                                           l = 1000 µm
                                                                           -5                              l = 600 µm
                                                                                                           l = 300 µm
                                                                           -6
                                                                                0   10         20          30            40
                                                                                         Frequency [GHz]
                                                                                                                    Page 17
Wirebond Interconnects – Padsize Variation

            0


           -10


           -20
S11 [dB]




           -30

                                                                          0
           -40                               w = 100 µm
                                             w = 200 µm
                                             w = 300 µm
           -50
                 0   20         40          60            80              -2
                          Frequency [GHz]
                                                               S21 [dB]


                                                                          -4

                                                                                   w = 100 µm
                                                                                   w = 200 µm
                                                                                   w = 300 µm
                                                                          -6
                                                                               0      20          40          60      80
                                                                                            Frequency [GHz]
                                                                                                                   Page 18
Flip-Chip Interconnects – Padsize Variation

            0


           -10


           -20
S11 [dB]




           -30


           -40
                                                                          0

           -50                               w = 300 µm
                                             w = 200 µm
                                             w = 100 µm
           -60
                 0   20         40          60            80              -1
                          Frequency [GHz]
                                                               S21 [dB]


                                                                          -2

                                                                                   w = 300 µm
                                                                                   w = 200 µm
                                                                                   w = 100 µm
                                                                          -3
                                                                               0       20             40          60      80
                                                                                                Frequency [GHz]
                                                                                                                       Page 19
Outline


    Introduction

    Package Overview

    Thin Small Leadless Package (TSLP)

    Embedded Wafer-Level Ball Grid Arry (eWLB)

    Through Silicon Vias (TSV)

    Experimental Results

    Conclusion

                                                 Page 20
WLB Basic Platforms
Fan-In / Fan-Out

              WLB Fan-In                                  WLB Fan-Out (eWLB)
         restricted to chip size                         offers fan-out possibility
WLB without               WLB with
       redistribution layer




                                                                                      eWLB Test Vehicle
                                   SG-UFWLB-49



WLBs Fan-In are chip size packages               Package design of Fan-Out Package
All balls must fit UNDER chip shadow             is INDEPENDENT from chip size:

                                                 • Fan-out area adaptable to needs
• Number and pitch of Interconnects
                                                 • No restrictions for ball pitch
  must be adapted to the chip size
                                                 • Fan-Out WLB actually strongly in
• Fan-in WLBs are available on
                                                   the focus of the market
  market


                                                            : Chip size
                                                            : Package size                                Page 21
Schematic Process Flow for eWLB Package




       M. Brunnbauer, et al., “Embedded Wafer Level
       Ball Grid Array (eWLB),” 8th EPTC, Dec. 2006.
                                                       Page 22
Transmission Lines in eWLB Techology
  CPW
W/S = 87/20 µm
Re Z0 = 49.2 Ω (Mold)
Re Z0 = 42.8 Ω (Si 1-100 Ωcm)
                                Mold (eWLB)/Si 1-100 Ωcm

  TFMSL
W/T = 20/3 µm
H = 10 µm                                                  BCB
Re Z0 = 49.2 Ω (BCB)

                                Si 1-100 Ωcm
  MSL
W/T = 317/35 µm
H = 130 µm
Re Z0 = 46.9 Ω (RO3003)         RO3003



                                                           Page 23
Transmission Lines cont.

 Measured performance




                                            eWLB
                  eWLB




      Excellent performance of TMLs manufactured in eWLB
   Insertion loss 0.1 dB/mm @ 10GHz, 0.25 dB/mm @ 60GHz

                                                           Page 24
Transmission Lines cont.
 Determination of charactersitic   Line Parameters RLCG
 impedance of the CPW




               R ~ √f                     G ~ ωCtanδ

                                                               tanδ = 0.017
                                                       (data-sheet = 0.026)




                                                                       Page 25
Transmission Lines cont.

 Separation of the electrical effects of the conductors and dielectrics




 where




            αC/αD = 90%                          αC/αD = 70%

        Further improvement of the performance of the
   transmission lines by applying low-loss thin-film dielectrics

                                                                          Page 26
Single-Layer Spiral Inductors

 Layout parameters




 Measured performance




                                Page 27
Single-Layer Spiral Inductors cont.

 Measured performance




    Inductors in eWLB offer significantly better performance
    compared to inductors in standard on-chip technologies

                                                               Page 28
MIM/Interdigital Inductors

 MIM capacitors




 Interdigital capacitors




                             Page 29
MIM/Interdigital Inductors cont.

 Measured Performance




         Further improvement of the quality factor of the
   integrated capacitors by using low-loss thin-film dielectrics

                                                                   Page 30
Outline


    Introduction

    Package Overview

    Thin Small Leadless Package (TSLP)

    Embedded Wafer-Level Ball Grid Arry (eWLB)

    Through Silicon Vias (TSV)

    Experimental Results

    Conclusion

                                                 Page 31
More fan out WLBs : Silicon Carrier Concept

                                      µFC interconnect
                  Silicon IC Die                     Metal layer   Via hole   Dielectric
                                                     (Cu)                     layer




               Standard Solder Ball
                                                                              Macro porous silicon




Passive Si carrier with regular grid of TSV
  High integration density (Wafer technology for RDL)
  Passive integration of L and C
  High reliability interconnects IC and carrier (CTE match)
  Low cost concept
  (Standard circuit dies, cost optimized carrier concept)
                                                                                            Page 32
Embedded Passives in Si Low Cost Technology
Inductor                                         Capacitor




 Planar L using of       Si through hole via        MIM Caps using         Trench Caps using
 RDL for loops           for inductor loops         RDL for plates         Si – trough holes




              L = 0.5 − 35 nH                     C = 35pF/mm2             C = 3000pF/mm2
              Q = 20 − 25                         Q = 500 – 2000           Q < 1000
              Fres = 1 − 35 GHz                   Fres= 1-20 GHz           Fres < 10 GHz

Resistor
 No Resistor component in focus due to costs (missing specific material)

                                                                                        Page 33
Coplanar Waveguide (CPW) over TSVs




 Measurement




                Floating TSVs         Grounded TSVs



 HFSS Model




                                Gnd
                                                      Page 34
TFMSL and CPW over Floating TSVs



                  Influence
                  of TSVs




                                      Influence of TSVs




     Excellent performance of TMLs manufactured in SC
 Insertion loss 0.1 dB/mm @ 10GHz, 0.25 dB/mm @ 60GHz
                                                          Page 35
Single/Double-Layer Spiral Inductors
 Single-layer inductors over floating TSVs




 Double-layer inductors over floating TSVs




  The inductors in SC offer significantly better performance
   compared to inductors in standard on-chip technologies
                                                               Page 36
Influence of Floating/Grounded Configuration
 Single/double-layer inductors over floating TSVs vs. grounded TSVs



                                                                             Influence
                                                                             of TSVs
                                                                             ∆Q = 12




                                                             Grounding
                                                             of TSVs




                                          Single-layer spiral inductor of L = 2.0 nH




                                                                                   Page 37
3D Spiral Inductor




    The low quality factor is caused by the losses for the
  currents induced in TSVs distributed around the windings
                                                             Page 38
Influence of Floating/Grounded Configuration
 3D inductors over floating TSVs vs. grounded TSVs



                                                                            Influence
                                                                            of TSVs
                                                                            ∆Q = 15




                                                              Grounding
                                                              of TSVs


                                         3D spiral inductor of L = 5.6 nH




                                                                                 Page 39
Outline


    Introduction

    Package Overview

    Thin Small Leadless Package (TSLP)

    Embedded Wafer-Level Ball Grid Arry (eWLB)

    Through Silicon Vias (TSV)

    Experimental Results

    Conclusion

                                                 Page 40
17 GHz WLAN Receiver

 Fully assembled in TSLP-24
   Package dimensions 3.5 mm x 3.5 mm
   Package height 400 µm


 Wirebond interconnect technology
   Au wirebonds
   500 µm wirelength at critical RF output
   Approx. 400 pH parasitic inductance


 Inductance of the wirebonds used as external impedance
 matching network


                                                          Page 41
17 GHz WLAN Receiver


                                             Polished cut image
           Mold Compound
                            Chip    Ni-Pad


  400 µm


  300 µm



                Rogers RO4003 Substrate




                Evaluation board

                                                                  Page 42
17 GHz WLAN Receiver


                             Measured gain




      Two-tone measurement

                                             Page 43
80 GHz Voltage Controlled Oscillator
 Fully assembled in TSLP-24
   Package dimensions 3.5 mm x 3.5 mm
   Package height 400 µm
 Total power consumption of 2 W
   Flip-Chip interconnect technology not possible
   Wirebond technology and die-attach to leadframe for
   efficient thermal management
 Wirebond interconnect technology
   Au wirebonds
   300 µm wirelength at critical RF output
   250 pH parasitic inductance



                                                         Page 44
80 GHz Voltage Controlled Oscillator




                                       Page 45
80 GHz Voltage Controlled Oscillator




       2.4 GHz Output
       2.4 GHz Output




 19.125 GHz Output
 19.125 GHz Output
                            80 GHz Output
                            80 GHz Output


                                            Page 46
80 GHz Voltage Controlled Oscillator



                 Vss = 5.7 V                           Vss = 6 V
            (Core temp ≈ 100°C)                   (Core temp ≈ 100°C)

    VTUNE        fVCO      Output Power   VTUNE        fVCO      Output Power

     0V       75.07 GHz        5.45 dBm    0V       74.656 GHz     5.99 dBm

     1V       79.136 GHz       5.75 dBm    1V       78.848 GHz     6.11 dBm

     2V      80.384 GHz     6.67 dBm      2V       80.128 GHz      6.92 dBm

     3V       81.088 GHz       6.4 dBm    3V        80.85 GHz      6.92 dBm

     4V       81.536 GHz       5.83 dBm    4V       81.31 GHz      6.47 dBm

     5V       81.888 GHz       5.6 dBm     5V       81.664 GHz     6.11 dBm



                                                                                Page 47
77 GHz SiGe Mixer




 Chip size 550 × 550 µm2
   Gain G = 21.4 dB @ 77 GHz
   Noise Figure NFSSB = 11.8 @ 77 GHz

                                        Page 48
Package Design for 77 GHz SiGe Mixer

 Manufactured package family
   Package size 2.5 × 1.5 mm²
   and 2.0 × 1.5 mm²
   Full surface capability
   Standard pitch 0.5 mm
 Package P1X
   extremely short RF and LO
   signal paths (about 100 µm)
 Package P2X
   longer signal paths (about
   360 µm)
   Three different RDL
   metallization profiles




                                       Page 49
77 GHz SiGe Mixer
Gain and Noise Figure Measurements




                                     Page 50
TSV - RF Demonstrator on RF Test Board




 Fully functional & fully programmable
 RX & TX chain fully functional
 VCO locks on all channels
 Key RF parameters within spec limit
 Spurious performance need improvement
 Remark:
 No design of application optimization
 was done for the Si Carrier Demonstrator
                                             Page 51
TSV - RF Demonstrator : Cross Section

        Dimensions: 7,5mm x 8,0 mm


                            Transceiver                2 Layer RDL
                                                 Si Carrier


µ-Bump 50 µm                    2st Cu RDL Layer
                                        1st Cu RDL Layer


                      RDL VIA       Dielectric




               Silicon
                  Cu-Alloy Si-Through
                                                              FC Ball 250 µm
                  Contacts                 Copper
                                                                         Page 52
Outline


    Introduction

    Package Overview

    Thin Small Leadless Package (TSLP)

    Embedded Wafer-Level Ball Grid Arry (eWLB)

    Through Silicon Vias (TSV)

    Experimental Results

    Conclusion

                                                 Page 53
Conclusion

 Thin Small Leadless Package
   Low cost solution based on leadframe concept
   Suited for low pin count applications
   Good RF performance for dedicated applications
 Embedded Wafer-Level Ball Grid Array
   Excellent RF capabilities
   High pin count
   Passive device integration capabilities
 Through Silicon Vias
   High interconnect density
   Passive device integration capabilities

                                                    Page 54

				
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