Design Criteria

							3. DEVICE DESIGN

       3.1 Broad Design Criteria

        The broad design problem posed for the design project was to construct a bio-sensor
integrated with microfluidics, which would combine rapid sample detection with fast fluidic
switching. A motivating problem for the design is the goal of achieving electronic label-free
detection of protein binding. A fundamental trade-off is the need for a low ionic strength
solution to allow the solution Debye length to be long enough to detect the attached proteins,
which works against the need for a high ionic strength solution that is required for protein
binding. A possible way to work around this problem would be to rapidly switch samples of
different ionic strengths while making measurements on a timescale shorter than the timescales
required for protein reactions to occur.
          With this very general goal in mind, a more direct preliminary goal that could act as a
starting point to drive the device design is the fabrication of a field-effect pH sensor, combined
with microfluidics. Obviously, a desirable criterion is to maximize the sensitivity and detection
resolution of the sensor, as well as to have the ability to introduce multiple different samples into
the device. Additional design goals included an option to functionalize the sensor surface with
molecules, as well as being able to clean or flush the sensor between measurements.
        Finally, another very important design constraint was to use a fabrication process that
would be possible to carry out at the Microsystems Technology Laboratories (MTL) at MIT, and
to be able to complete the design, fabrication, and testing of the device in a single academic
semester.

       3.2 Initial Design Decisions

        Following the work of Cooper et. al. [10] a capacitive electrolyte-insulator-
semiconductor (EIS) structure was selected as the sensing device. This choice was largely
driven by the relative simplicity of the EIS capacitive structure, as opposed to an ISFET design.
While more complex to fabricate and operate, the ISFET offers no advantage in sensitivity over
an EIS capacitor [ref]. The EIS, therefore, offers an easy and fast method of pH measurement
with minimal instrumentation, by taking capacitance-voltage (C-V) curves of the EIS device.
The capacitance curve as a function of DC bias voltage shifts as a function of solution pH, and
this can easily be detected by operating at an appropriately chosen bias point and AC driving
frequency. The goal is to operate as close as possible to the Nernstian physical limit of 60
mV/pH.
        To improve the accuracy of the device, and to increase its versatility, we use a differential
measurement scheme, using a pair of identical sensors placed side-by-side in the fluid channel.
This allows us to activate or functionalize the surface of one sensor while leaving the other one
as a reference measurement. Subtracting the data from the two sensors helps eliminate or reduce
common-mode drift and noise effects. This scheme can also be easily adapted to simultaneously
measuring two different samples, if they are flowed side-by-side down the fluid channel in a
laminar fashion, one over each sensor.

        In the interest of rapid and low-cost design cycles, a decision was made to use high-
resolution laser-printed transparency masks (available from PageWorks, printed at 5080 dpi).
These offer a tremendous advantage in delivery time and cost, since they are available within a
24-hour design-to-delivery cycle time, and at 1/10th the price of standard chrome and glass
photomasks. A drawback of this process is that the minimum resolution is 5m, with an actual
minimal linewidth of 25m. While this provides an additional design constraint, it is not a
significant one in this case, since there is no need for high-resolution photolithography. Another
issue is the need to transfer the transparency patterns to chrome plates for regular use in the
fabrication process. The various consequences of making this decision will be discussed in later
sections of this report (see Sections 5.2 and 8).

       3.3 Device Description

       Resulting from these various considerations, the overall device design is shown in Figure
3.2. On the left is a schematic of the device mask layout, and on the right is a photo of an actual
completed device. The legend in the figure indicates the colors corresponding to different
materials. Note that the geometry resulting from the fabrication process is quite imprecise,
compared to the mask layout. This is discussed further in section 5.2.




[CAPTION: Figure 3.2. Device design and actual device. On the left is a FreeHand layout of
the device masks, and on the right a photo of a completed device (see section 3.4 for mask
design). Black outlines in the mask layout represent boundaries of PDMS channels and
“tunnels.” Note that the cross-channel was not molded into the PDMS used in the actual device.]

       The device itself consists of a pair of identically-sized EIS capacitors - the active areas in
contact with the solution are 25m × 25m square. They are designed to respond identically, as
a matched pair. They are made by implanting lightly-doped p-type regions (in Fig. 3.2 RED =
light boron implant: p) in an n-type silicon wafer. To maximize sensitivity, the active area
doping levels need to be kept low. Lighter doping allows a deeper depletion layer, more
capacitive variation with bias voltage, and hence greater sensitivity.
        In order to make contact with the electrolyte solution in the channel, an electrode is
required with a minimally reactive electrochemistry, and with a known half-cell potential. This
is accomplished by using a gold electrode (BLUE) in contact with the solution, and in close
proximity to the sensors. For ease of fabrication, the rest of the device metal contacts are also
made of gold. Electrical contact is made to the active areas and to the solution electrode by
means of highly p-doped (GREEN = boron implant: p+) traces that run under the silicon surface
and are contacted by gold traces outside the fluidic channel. Also, to properly control the
substrate voltage, the entire area surrounding the electronic structures is highly n-doped,
(ORANGE = phosphorus implant: n+) which enables good electrical contact with the silicon
substrate. Finally, the entire surface of the device is passivated with a thick layer of thermally
grown SiO2, in which holes are cut (PURPLE) only to expose the active regions and to make
electrical contact. It is the cuts in the oxide which define the 25m square size of the active
regions. The thermal oxide provides electrical isolation, chemical passivation, and a
biologically-compatible surface. The thermal oxidation step is also used to simultaneously
diffuse and anneal the ion implants (see next section for detailed doping and diffusion
parameters).
        Fluid is delivered to the active areas in microfluidic channels (BLACK OUTLINES),
fabricated in poly-dimethylsiloxane (PDMS), a silicone elastomer. In brief, the channels are
made by casting and curing the polymer on a relief-molded master. The PDMS is then bonded to
the SiO2 surface, making a leak-free seal for fluidics. In order to avoid the topography and
surface discontinuities associated with the gold traces on the oxide surface, “tunnels” were added
to the PDMS to surround the traces. Please refer to section 5 for complete fabrication details.

         3.4 Device geometry and Mask Design
         Keeping in mind the various goals of the project, the masks were designed to conform to
both the electrical and the mechanical constraints of the problem. The primary criteria that drove
the mask design process were transparency printing resolution limits, alignment tolerances,
lateral diffusion of the dopants, and the flow characteristics of the PDMS channel. The final
mask count for silicon device fabrication was six: (1) alignment & die marks, (2) p implant, (3)
p+ implant, (4) n+ implant, (5) oxide cuts, and (6) metallization (refer to appendix X for more
details).
         At the beginning of the design process, a number of different options were considered for
the size of the wafers to be used, as well as the photolithography method. Photolithography
using a stepper, with optical reduction of the mask features, would obviously be a great
improvement in the feature resolution achievable with transparency masks. However, for a
number of reasons, the process had to be implemented on 4” Si wafers, using contact
photolithography.
         Mask design was carried out using FreeHand graphical software, which is the file format
preferred by PageWorks. All six mask layers were drawn together, with a separate color and
layer for each photolithography step. It is important to note that while the tone of all features in
the graphical files is positive (clear field), transparencies of the inverse tone were ordered (clear
field) in order to properly fabricate the desired structures (e.g. if positive photoresist is used,
implanting an area with boron, requires that area to be an open window in a dark-field mask).
         As mentioned previously, the minimum feature size of transparency masks is 25m (the
actual resolution limit of the 5080 dpi laser printer is 5m; however, the minimal practically
printable feature is 25m). This meant that all mask features had to be drawn on a 5m-pitch
grid, and the smallest shape would be a 25m × 25m box. The sensing areas, defined by the
oxide cuts seen in Fig. 3.2, were therefore sized at this minimal feature size, and the rest of the
mask features were laid out accordingly. For a detailed discussion of mask layout, please refer to
Appendix A.


        3.5 TSUPREM4 Modeling
        Prior to designing the detailed fabrication process for the device, numerical simulation
proved extremely useful in determining the optimal process parameters to be used. TSUPREM4
is a package that performs finite-element numerical simulations of standard semiconductor
processing steps, such as doping, photolithography, and thermal diffusion, in order to predict the
resulting geometry, dopant concentrations, oxide thickness, etc.
        A number of considerations drove the design. As mentioned above, the active regions
needed to be lightly p-doped, enough to exceed the background doping of the wafer, but low
enough to maintain sensitivity. The p+ and n+ regions required heavy doping, to enable ohmic
contact, as well as low resistivity to ensure minimal resistive losses along their length. A thick
oxide (~1m) was required to ensure good passivation and minimize capacitive coupling
between the electrolyte above it and conductive traces below it. Obviously, the duration and
temperature of high-temperature dopant diffusion and oxidation steps would be a key parameter
to control in achieving the desired results. Finally, lateral diffusion was an issue of concern, to
verify that the selected geometry did not result in undesired electrical contact between different
doped regions.
        After a number of simulation cycles, using a reduced feature geometry to speed up
simulations, a number of design decisions were made. Processing is greatly simplified if we use
only one high-temperature furnace step, so we chose to carry out the dopant diffusion and
thermal oxidation simultaneously. The three separate ion-implantation steps were designed all
be done all in sequence, followed by a single dry/wet/dry (15/200/15 min) oxidation/anneal at
1050° C (this process recipe was chosen to conform to an available recipe at MTL). With these
constraints, the implantation parameters, and the expected resulting surface dopant concentration
were chosen as shown in the following table.

doping               species    energy        dose (cm-2)    projected     final surface
                                (keV)                        range         concentration
p (active)           boron      100           5 × 1013       0.3 m        1017 cm-3
p+ (traces)          boron      100           5 × 1015       0.3 m        8 × 1018 cm-3
n+ (subs. contact)   phosphorus 125           5 × 1015       0.3 m        6 × 1019 cm-3

        A simulation done with these parameters produces the results shown in the next two
figures. Figure 3.3 shows a cross-section through the surface of the device, with distance into the
wafer (depth) on the y-axis, and distance parallel to the wafer surface on the x-axis. For these
simulations, the p implant was placed from x=5 to x=10, the p+ implant from x=10 to x=15, and
the n+ implant from x=20 to x=25. The colors represent dopant concentration, starting with 1016
cm-3 in red, and moving through the color spectrum at increments of half an order of magnitude.
The y-axis is referenced to the original wafer surface location (y=0.0), and the 1m oxide layer
(in cyan) is clearly evident between y=-0.5 and y=0.5.
        Figure 3.4 is a section of this plot at y=0.6 (slightly below the resulting Si-SiO2
interface), and more clearly illustrates the surface doping concentrations. The spatial x-
coordinate of this plot is the same as in Fig. 3.3, but the y-axis now shows the dopant
concentration.
        Appendix B contains the full TSUPREM4 code used to run these simulations, as well as
an additional plot of dopant concentration profiles.
APPENDIX A: MASK DESIGN AND LAYOUT

       This Appendix discusses in detail the various decisions made during the mask layout
process. The descriptions in the following section all refer to the following figure. [CAPTION:
Figure A1: Mask close-up. Shown here is the electrically “interesting” area of the device. All
dimensions are specified in microns. Refer to Fig. 3.2 for color legend.]



                     150                                                 25
                             130

                    45                                            45
                                                                               55

              130                                           45                      25
                                                                                         20
                                                                    25        20
                                                                         20

                    35




Silicon features
        As mentioned in Section 3.4, the minimal feature size achievable with transparency
masks is 25m – this dictated the 25m square size of the device active areas. The adjacent
arrangement of the sensing areas was chosen based on the intended applications of the device.
With laminar fluid flow down the fluidic channel, two different solutions could flow side-by-side
down the channel, separated by a boundary layer. Thus, if the devices are likewise placed side-
by-side across the channel, they can independently sense two solutions flowing simultaneously.
Additionally, the devices are placed adjacent to each other to maximize their symmetry and
make them behavior as identically as possible. For instance, a possible experiment with the
device uses electro-osmotic flow to drive the solution down the channel. This flow-driving
method sets up a potential gradient in the solution, and places nonadjacent sensing areas at
different potentials, reducing their effectiveness as a differential pair the complexity of the
system.
        The transparency resolution limits imposed an additional set of layout constraints.
Ordinarily, overlap tolerances between features need to be only as large as the mask aligner
tolerances. The contact mask aligners in MTL normally have tolerances of ~1mm. However,
the low expected precision of the printed mask features increased the required tolerance to a
minimum of 5m. To be completely certain of proper alignment, all overlap and separation
tolerances are drawn to be 10m on these masks. Therefore, the p-regions that form the sensing
areas were designed with a 10m border around the oxide cuts that would expose them.
        For the pair of devices to operate properly, it is essential that the p-regions are separated
from each other and from the reference electrode region. For this reason, there is a 20m
separation between all of these.
        Under this constraint, the reference electrode was placed in the center of the channel, as
close as possible to the active areas, and equidistant from both. This electrode placement puts it
within the secondary PDMS cross-channel, intended for use in cleaning and flushing of the
sensing surfaces.
        Finally, to electrically isolate the sensing areas and reference electrode from the rest of
the die, the outlying substrate must be positively biased. A front-side substrate contact was
chosen over a backside contact to simplify the final packaging process. This contact is made by
means of a highly-doped n+ region, which completely surrounds the active device components,
leaving a ~20m gap around them.
        Gold traces connect to the device and reference electrode n+ contacts through cuts made
in the oxide during the same step as the active area cuts. The traces run to the each of four
corners of the square die, where they terminated with large 1mm x 1mm bond pads. The die size
of 20mm × 20mm was determined by the requirement that it be large enough to easily handle
when attaching the PDMS molded fluidic channels, attaching tubes to those channels, and to
allow room for wirebonding. (Experience now shows that the die can likely be made somewhat
smaller – perhaps as small as 10mm × 10mm).


Alignment Marks
         Alignment marks for photolithography are crucial for the first few steps of our silicon
process, since implants are invisible on a silicon surface. Therefore, in order to be able to align
the implants to each other, alignment trenches were necessary as the first step in the process. In
addition, a set of die-boundary marks was added to the alignment layer, which become etched
into silicon, and allow easy identification of dies. These also serve as ideal die-saw guides
during die separation.
         The entire alignment structure (shown Figure A2 (b) on next page). was designed to
allow any mask to be aligned to marks from any of the other masks. It is a matrix of light-field
and dark-field crosses which line up in subsequent rows and columns for each succeeding mask
(in the figure, these are again color-coded as before, each mask layer having a separate color. In
retrospect, the marks are too large to fit the entire alignment grid in the mask-aligner microscope,
and the placement of overlapping features between layers could be somewhat improved. This is
a consideration to be implemented in the next device generation.


PDMS-related features
        A number of considerations influenced the design of the PDMS microfluidic channels.
The channel width resulted from the device geometry, as well as the expected accuracy of PDMS
alignment to the device (optimistically assumed to be 20m, but later proven to be even more
accurate due to the alignment scheme discussed in Section 6.1). Allowing the 20m tolerance on
both sides of the active areas resulted in a width of 130m for the primary channel.
        The PDMS molding process allows variable channel depths, down to about 50mm with
the SU-8 polymer used to make the master. However, the ability to properly drive laminar plug
flow down the channel with electro-osmosis is dependent upon the channel dimensions. If the
width of the channel is too much greater than its depth, laminar flow becomes problematic – an
aspect ratio close to 1 is needed. Therefore, the channel height is designed to be between 100m
and 150m.
        In order to avoid problems with PDMS adhesion to the oxide-covered die surface, due to
the topography associated with the gold traces, “tunnels” are molded in the PDMS, which fit
around the electrodes. Because of this, the length of the n+ traces running out to connect with
the gold traces on the silicon surface was primarily driven by a PDMS-related constraint.
Obviously, these traces need to be as short as possible, to form a low-resistance connection.
However, the wall of PDMS separating the electrode tunnels from the microchannel must be
thick enough to properly bond to the surface and seal the channel. The minimum required wall
thickness of the PDMS between the flow channel and a trace path is estimated to be on the order
of 100m. To allow a nominal margin of error, the traces were placed to create a 150m thick
PDMS wall. Finally, in order to make PDMS alignment more tolerant to errors in alignment
angle (-error), the tunnels widen out toward the bond pads, as shown in Fig. A2 (a).




The following two pages will be full-page figures. First, a page with three figures, which will
have fulldiemask.gif, aligngrid.gif, and aligncross.gif. These collectively make up Figure A2,
and have sub-labels (a) (b) and (c) respectively. You can probably lay them out with (a) at the
top center, and (b) and (c) below that. let me know if that works.

The caption at the bottom of the first page is [Figure A2: Mask Details. (a) A full-die view of
the mask layout. The die size is 20mm × 20mm. Note thick black lines around the edge – these
are the die-marks used for diesawing. Note also location of alignment features on the die, as
well as the relative sizes of the “area of interest” to the die, and length of gold traces. (b) Detail
of the alignment grid showing all alignment features. Shown here in opposite (positive) tone to
that of the actual masks – the mask tone for these features was dark field (see Section 3.4 for
explanation). (c) Detail of one alignment feature, showing dimensions and alignment
tolerances.]


The following page will be a full-wafer level figure of one mask layer, which is the figure
layer0full.gif. The caption reads
[Figure A3: Full 5” mask plate layout. Shown here actual size is a full, wafer-level “layer 0”
mask – the alignment trenches and die marks. Note that there are 12 dies to a wafer, and two
such 5” plates can be tiled on one 8.5” × 11” transparency, effectively doubling the yield].
APPENDIX B: TSUPREM4 CODE AND SIMULATION RESULTS

$ 6.151 Spring 2002
$ TSUPREM4 simulation of implants and oxidation

$ setup grid (mesh size finest at junctions of dopants

LINE   X   LOC=0.0 SPAC=1
LINE   X   LOC=9.0 SPAC=0.5
LINE   X   LOC=10.0 SPAC=0.1
LINE   X   LOC=11.0 SPAC=0.5
LINE   X   LOC=14.0 SPAC=0.5
LINE   X   LOC=15.0 SPAC=0.1
LINE   X   LOC=16.0 SPAC=0.5
LINE   X   LOC=19.0 SPAC=0.5
LINE   X   LOC=20.0 SPAC=0.1
LINE   X   LOC=21.0 SPAC=0.5
LINE   X   LOC=30.0 SPAC=1

LINE Y LOC=0.0 SPAC=0.2
LINE Y LOC=3.0 SPAC=0.2

$ start with <100> n=doped (As) wafer
INIT <100> ARSENIC=5E15

$ thin oxide diffusion as protective layer for implants
DIFFUSION TEMP=950 TIME=15 DRYO2
DIFFUSION TEMP=950 TIME=7 WETO2
DIFFUSION TEMP=950 TIME=15 DRYO2

$ pattern resist for p implant (window from x=5 to x=10)
DEPOSITION PHOTORES THICKNESS=1.1
ETCH PHOTORES START X=5 Y=-0.035
ETCH CONTINUE X=10 Y=-0.035
ETCH CONTINUE X=10 Y=-1.13
ETCH DONE X=5 Y=-1.13
IMPLANT BORON DOSE=5E13 ENERGY=100
ETCH PHOTORES ALL

$ pattern resist for p+ implant (window from x=10 to x=15)
DEPOSITION PHOTORES THICKNESS=1.1
ETCH PHOTORES START X=10 Y=-0.03
ETCH CONTINUE X=15 Y=-0.03
ETCH CONTINUE X=15 Y=-1.13
ETCH DONE X=10 Y=-1.13
IMPLANT BORON DOSE=5E15 ENERGY=100
ETCH PHOTORES ALL

$ pattern resist for n+ implant (window from x=20 to x=25)
DEPOSITION PHOTORES THICKNESS=1.1
ETCH PHOTORES START X=20 Y=-0.03
ETCH CONTINUE X=25 Y=-0.03
ETCH CONTINUE X=25 Y=-1.13
ETCH DONE X=20 Y=-1.13
IMPLANT PHOSPHORUS DOSE=5E15 ENERGY=125
ETCH PHOTORES ALL
$ diffusion to grow       thick oxide and drive in dopants
ETCH OXIDE ALL
DIFFUSION TEMP=1050       TIME=15 DRYO2
DIFFUSION TEMP=1050       TIME=200 WETO2
DIFFUSION TEMP=1050       TIME=15 DRYO2

$ output resulting design file to "device.dat" for easy reference
SAVEFILE OUT.FILE=device.dat

$ FOLLOWING THIS ARE VARIOUS FILE PLOTS: SOME REPRESENTATIVE PLOTS ARE
INCLUDED BELOW


OPTION device=ps-c file.sav=testout.ps
SELECT Z=LOG10(DOPING) TITLE="oxidation and dopant diffusion"
PLOT.2D X.MIN=0 X.MAX=30 Y.MAX=3.0 line.typ=2 boundary
COLOR MATERIAL=SILICON COLOR=1
COLOR MATERIAL=OXIDE COLOR=5
FOREACH X ( 16 to 20 STEP 0.5)
COLOR MIN.VALU=X MAX.VALU=( X + 1 ) COLOR=( 2 * (X - 16) + 8 )
END

OPTION device=ps-c file.sav=ysect.ps
SELECT z=log10(phosphorus) title="surface doping profile"
PLOT.1D Y.VALUE=0.6 BOTTOM=13 TOP=21 RIGHT=30 LINE.TYP=5 COLOR=2
SELECT z=log10(boron)
PLOT.1D Y.VALUE=0.6 ^AXES ^CLEAR LINE.TYP=2 COLOR=4
SELECT z=log10(arsenic)
PLOT.1D Y.VALUE=0.6 ^AXES ^CLEAR LINE.TYP=3 COLOR=3

OPTION device=ps-c file.sav=xsectplus.ps
SELECT z=log10(phosphorus) title="p++ doping profile"
PLOT.1D X.VALUE=12 BOTTOM=13 TOP=21 RIGHT=3 LINE.TYP=5 COLOR=2
SELECT z=log10(boron)
PLOT.1D X.VALUE=12 ^AXES ^CLEAR LINE.TYP=2 COLOR=4
SELECT z=log10(arsenic)
PLOT.1D X.VALUE=12 ^AXES ^CLEAR LINE.TYP=3 COLOR=3



The next page is basically a full-page figure, figure_B1.jpg, which’ll be some dopant profiles.
The caption is [Figure B1: Dopant Profiles. This figure shows dopant concentration as a
function of distance into the wafer (x-axis in this figure is y-axis on the 2D color plot in Figure
3.3). The oxide-silicon interface is at x=0.5. The three curves show profiles at different cross
section locations, according to the legend.]