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International Journal of Emerging Trends & Technology in Computer Science (IJETTCS) Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com Volume 1, Issue 2, July – August 2012 ISSN 2278-6856 Field Programmable Gate Array Implementation of 14 bit Sigma-Delta Analog to Digital Converter Sukhmeet Kaur1, Parminder Singh Jassal2 1 M.Tech Student , Department of Electronics and Communication Engineering, Yadavindra College of Engineering, Punjabi University Guru kashi Campus , Talwandi Sabo – 151 302 , Punjab (India) 2 Assistant Prof., Department of Electronics and Communication Engineering, Yadavindra College of Engineering, Punjabi University Guru kashi Campus , Talwandi Sabo – 151 302 , Punjab (India) Abstract: This paper the design and FPGA implementation The work on electronic ADC was started with the of a delta sigma A/D convertor. The proposed converter has invention of Pulse code modulation (PCM) in 1921[1]. A been designed using Xilinx system generator tool, which significant development in ADC technology during the reduces the design cycle by directly generating efficient period was the electron beam coding tube described by R. VHDL code. The VHDL code has been implemented on a W. Sears in [4]. The basic algorithm used in the Spartan 3E xc3s100e-4vq100 FPGA using ISE 12.4 tool. successive approximation ADC conversion is based on Keywords: Analog to Digital Convertor, Field the determination of an unknown weight by a minimal Programmable Gate Array, Sigma–Delta, System sequence of weighing operations [5]. Later CMOS was Generator, Xilinx. the ideal process for the sigma-delta (Σ-∆) architecture, which became the topology of choice for ADCs used in 1. INTRODUCTION voice band and audio applications, as well as in higher The most important advantages of digital processing over resolution, low frequency measurement converters. The analog processing are a perfect storage of digitized Σ-∆ architecture began to replace the parallel ADCs in signals, unlimited signal-to-noise ratio, the option to audio applications. Σ-∆ offered much higher carry out complex calculations, and the possibility to oversampling ratios, thereby relaxing output filter adapt the algorithm of the calculation to changing requirements, as well as provided higher dynamic range circumstances[10]. If an application wants to use these with lower distortion. In this paper Σ-∆ ADC has been advantages, analog signals have to be converted with high implemented on FPGA using system generator tool by quality into a digital format in an early stage of the Xilinx. The performance of the Σ-∆ ADC has also processing chain. And at the end of the digital processing evaluated by converting its digital output again into the conversion has to be carried out in the reverse analog domain. direction. The digital-to-analog translates the outcome of the signal processing into signals that can be rendered as 2. PRELIMINARIES OF A/D CONVERSION a picture or sound. This makes analog-to-digital (A/D) Signals, in general, can be divided into two categories an conversion a crucial element in the chain between our analog signal, x(t), which can be defined in a continuous- world of physical quantities and the rapidly increasing time domain and a digital signal, x(n), which can be power of digital signal processing. Fig 1 shows the represented as a sequence of numbers in a discrete-time (ADC) as the crucial element in a system. domain as shown in Fig 2. The time index n of a discrete- time signal x(n) is an integer number defined by sampling interval T[8]. Thus, a discrete- time signal, x*(t), can be represented by a sampled continuous-time signal x(t) as: x * (t ) x(t ) (t nT ) n (1) Where, (t ) 1 , t 0 0, elsewhere Most ADCs can be classified into two groups according to the sampling rate criteria. Nyquist rate converters, such as a successive approximation register (SAR), double A Figure 1: The A/D and D/A converters [10] practical A/D converter transforms x(t) into a discrete- time digital signal, x*(t), where each sample is expressed Volume 1, Issue 2 July-August 2012 Page 229 International Journal of Emerging Trends & Technology in Computer Science (IJETTCS) Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com Volume 1, Issue 2, July – August 2012 ISSN 2278-6856 with finite precision. Each sample is approximated by a band, which were not present in the original signal. This digital code, i.e., x(t) is transformed into a sequence of non-linear phenomenon is a signal distortion frequently finite precision or quantized samples x(n). Integration, referred to as aliasing [6]. The distortion can only be and oversampling converters, sample analog signals prevented by properly lowpass filtering called the anti- which have maximum frequencies slightly less than the aliasing filter. In addition to an anti-aliasing filter, a Nyquist frequency, fN = fs/ 2, where fs is the sampling sample and hold circuit is required. Although the analog frequency [2]. Meanwhile, oversampling converters signal is continuously changing, the output of the sample perform the sampling process at a much higher rate, fN and hold circuitry must be constant between samples so << Fs, where Fs denotes the input sampling rate. the signal can be quantized properly. This allows the converter enough time to compare the sampled analog signal to a set of reference levels that are usually generated internally [7]. If the output of the sample-and- hold circuit varies during T, it can limit the performance of the A/D converter subsystem.Each of these reference levels is assigned a digital code. The process of converting an analog signal into a finite range number system introduces an error signal that depends on how the signal is being approximated. This quantization error is Figure 2: Generalized ADC process [8] on the order of one least-significant-bit in amplitude, and it is quite small compared to full-amplitude signals. Fig. 3 illustrates the conventional A/D conversion process However, as the input signal gets smaller, the that transforms an analog input signal x(t) into a quantization error becomes a larger portion of the total sequence of digital codes x(n) at a sampling rate of fs = signal. When the input signal is sampled to obtain the 1/T, where T denotes the sampling interval. sequence x (n), each value is encoded using finite word lengths of B-bits including the sign bit. Assuming the sequence is scaled such that x (n) 1 for fractional number representation, the pertinent dynamic range is 2. Since the encoder employs B-bits, the number of levels B available for quantizing x (n) is 2 . The interval between successive levels, q, is therefore given by: 1 q B 1 2 (4) Figure 3: Conventional ADC process [8] which is called the quantization step size. Mean square 1 value of quantization error can be calculated as [5]: ( j 2 n t )/ T x (t ) (t nT ) T x (t ) e e2 E e 2 1 q/2 e 2 de q 2 2 2 B n n q ( q )/2 12 3 (2) also (5) where E denotes statistical expectation 1 1 x *(t ) x(t )e( j 2 n t )/T T n x(t )e j 2 fsnt T n 3. Σ-∆ A/D CONVERTER (3) Eqn. 2 states that the act of sampling (i.e., the sampling Fig. 4 shows the block diagram of a Σ-∆ A/D converter. function): The 1-bit digital output from the modulator is supplied to a digital decimation filter which yields a more accurate representation of the input signal at the output sampling n x (t ) (t nT ) rate of fs. In the figure is a first-order Σ-∆ modulator. It consists of an analog difference node, an integrator, a 1- is equivalent to modulating the input signal by carrier bit quantizer (A/D converter), and a 1-bit D/A converter signals having frequencies at 0, fs, 2fs,. . .. In other in a feed- back structure. The modulator output has only words, the sampled signal can be expressed in the 1-bit (two levels) of information, i.e., 1 or -1. The frequency domain as the summation of the original signal modulator output y(n) is converted to x(t) by a 1-bit D/A component and signals frequency modulated by integer multiples of the sampling frequency Thus, input signals converter. The input to the integrator in the modulator is above the Nyquist frequency, fn, cannot be properly the difference between the input signal x(t) and the converted and they also create new signals in the base- quantized output value y(n) converted back to the Volume 1, Issue 2 July-August 2012 Page 230 International Journal of Emerging Trends & Technology in Computer Science (IJETTCS) Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com Volume 1, Issue 2, July – August 2012 ISSN 2278-6856 predicted analog signal, x(t). Provided that the D/A Where is the most significant bit of the DAC input converter is perfect, and neglecting signal delays, this and is filter settle time constant.This approach difference between the input signal x(t) and the fed back makes the ADC unsuitable for applications requiring a signal x(t) at the integrator input is equal to the high sampling rate. The 'ADCOut Register' captures the quantization error. This error is summed up in the reference shifter output after a sample has been computed, integrator and then quantized by the 1-bit A/D converter. then produces the ADC output sample. The 'ADCOut Register' captures the reference shifter output after a sample has been computed, then produces the ADC output sample. The 'ADCOut Register' captures the reference shifter output after a sample has been computed, then produces the ADC output sample. The 'ADCOut Register' captures the reference shifter output after a sample has been computed, then produces the ADC output sample. 1 AgtR AgtR Figure 4: Block Diagram of Sigma delta A/D converter [8] shif t mask shif t ref _shif ter 1 DAC_dri ver Although the quantization error at every sampling mask d Mask Reference instance is large due to the coarse nature of the two level Shi fter Shifter z -1 q 2 en ADCout quantizer, the action of the Σ-∆ modulator loop is to ADCOut generate a±1 output which can be averaged over several Regi ster input sample periods to produce a very precise result. The [a:b] z-1 averaging is performed by the decimation filter which and 3 ADC_Sampl ed follows the modulator. [shi ft] l oad l1 -1 4 z sampl e 0 di n -- a 4. FPGA IMPLEMENTATION OF Σ-∆ ADC 'c1' en 0 b a=b z -1 [shi ft] and Σ-∆ ADC has been implemented using System Generator FSTM Counter l2 tool of Xilinx, which reduces the design cycle. The snapshot of the ADC has been shown in Fig 5. ++ a z-1 a=b -1 z DAC Sampl e 0 b Counter rel1 Figure 6: Block Diagram of ADC a 1 a a+b d DAC_In a+b b -1 z q [a:b] d b 0 rst Sigma Adder -1 q 1 z Delta DAC_Out r1 Adder hi 0 rst hi } } lo lo 0 Figure 7: Block Diagram of DAC Figure 5: Snapshot of the Set-Up Fig. 6 shows the block diagram of ADC. ADC employs a Fig. 7 shows block diagram of DAC. The Delta Adder sequential binary search to arrive at the appropriate computes the difference between the current DAC input output sample. The sample rate of the ADC is computed and the current DAC output. The two concatenators as create a 16-bit output with the DAC output copied in the f clk two MSB positions. This effectively creates a difference ADCsr from the Delta Adder when the DAC output is 1. The 2 MSBI 1 Fmst 1 MSBI 1 Sigma Adder accumulates the differences produced by the Delta Adder by using 'r1' to storing the adder output on Samples/sec (6) each successive cycle. The MSB of the 'r1' output is sliced off and provides the DAC output. The pulse string is Volume 1, Issue 2 July-August 2012 Page 231 International Journal of Emerging Trends & Technology in Computer Science (IJETTCS) Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com Volume 1, Issue 2, July – August 2012 ISSN 2278-6856 registered before it is driven on the DAC output port. The REFERENCES proposed ADC has been verified by converting its output [1] Paul M. Rainey, "Facimile Telegraph System," U.S. back to analog domain by using DAC. Table 1 shows the Patent 1,608,527, filed July 20, 1921, issued comparison of ADC input and output of DAC. The results November 30, 1926. show that the proposed design is quite accurate in [2] H. Nyquist, "Certain Factors Affecting Telegraph converting the analog data into digital data. The small Speed," Bell System Technical Journal, Vol. 3, error shown in Table 1 may be a due to inaccuracy of April 1924, pp. 324-346. DAC. [3] H. S. Black, "Pulse Code Modulation," Bell Labs Record, Vol. 25, July 1947, pp. 265-269. [4 R. W. Sears, "Electron Beam Deflection Tube for Pulse Code Modulation," Bell System Technical Journal, Vol. 27, pp. 44-57, Jan. 1948. [5] W. W. Rouse Ball and H. S. M. Coxeter, Mathematical Recreations and Essays, Thirteenth Edition, Dover Publications, 1987, pp. 50, 51. [6] H. Nyquist, “Certain topics in telegraph transmission theory,” AIEE Trans., pp. 617-644, 1928. [7] M. Armstrong, et al, “A COMS programmable self- calibrating 13b eight-channel analog interface processor,” ISSCC Dig. Tech. Paper, pp. 44-45, Feb. 1987. [8] Sangil Park, “Principles of Sigma-Delta Modulation for Analog-to- Digital Converters” Motorola Figure 8: Internal View of Top Level RTL Schematic of Digital Signal Processors. Proposed ADC [9] Ms.N.P.Pendharkar, Dr.K.B.Khanchandani Design, The summary of the resources utilized has been shown in Development & Performance Investigations of table 2. Sigma-Delta ADC using CMOS Technology, Table 2: Resource Utilization for Spartan 3E xc3s100e- International Journal of Advanced Engineering & 4vq 100Device Application, Jan 2011 Issue Device Utilization Summary (estimated values) [10] Marcel J.M. Pelgrom “Analog-to-Digital Conversion http://www.scribd.com/doc/60454030/ Logic Utilization Used Available Utilization Analog-to-Digital-Conversion. Number of Slices 38 960 3% Number of Slice Flip Flops 55 1920 2% Number of 4 input LUTs 45 1920 2% Number of bonded IOBs 3 66 4% Number of GCLKs 1 24 4% 5. CONCLUSION This paper presents the design and implementation of proposed Σ-∆ ADC. The proposed design has been implemented on Spartan 3E xc3s100e-4vq 100 FPGA Device and only consumes 38 number of slices, number of 55 Slice Flip Flops, 45 number of 4 input LUTs, 3 number of bonded IOBs and 1 number of GCLKs out of available 960, 1920, 1920, 66 and 24 respectively. The proposed design has also been verified for its accuracy. Volume 1, Issue 2 July-August 2012 Page 232

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International Journal of Emerging Trends & Technology in Computer Science (IJETTCS), Web Site: www.ijettcs.org, Email: editor@ijettcs.org, editorijettcs@gmail.com
Volume 1, Issue 2, July – August 2012, ISSN 2278-6856

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International Journal of Emerging Trends & Technology in Computer Science (IJETTCS) is an online Journal in English published bimonthly for scientists, Engineers and Research Scholars involved in computer science, Information Technology and its applications to publish high quality and refereed papers. Papers reporting original research and innovative applications from all parts of the world are welcome. Papers for publication in the IJETTCS are selected through rigid peer review to ensure originality, timeliness, relevance and readability. The aim of IJETTCS is to publish peer reviewed research and review articles in rapidly developing field of computer science engineering and technology. This journal is an online journal having full access to the research and review paper. The journal also seeks clearly written survey and review articles from experts in the field, to promote intuitive understanding of the state-of-the-art and application trends. The journal aims to cover the latest outstanding developments in the field of Computer Science and engineering Technology.

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