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					   International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)
       Web Site: Email:,
Volume 1, Issue 2, July – August 2012                                          ISSN 2278-6856

                                            Shikha Khurana1, Kanika Kaur2
                                             M.Tech Student, KIIT Gurgaon, India 1
                                            Research Scholar, JJTU, Rajasthan, India

                                                                 High level design methodology allows managing the
                                                                 design complexity in a better way and reduces the design
Abstract: This paper primarily deals with the construction       cycle. [10]. A high-level model makes the description and
of arithmetic Logic Unit (ALU) using Hardware Description        evaluation of the complex systems easier. RTL
Language (HDL) using Xilinx ISE 9.2i and implement them          description specifies all the registers in a design, and the
on Field Programmable Gate Arrays (FPGAs) to analyze the
                                                                 combinational logic between them. The registers are
design parameters.. ALU of digital computers is an aspect of
                                                                 described either       explicitly through component
logic design with the objective of developing appropriate
algorithms in order to achieve an efficient utilization of the   instantiation or implicitly through inference [3]. The
available hardware. The hardware can only perform a              combinational logic is described by logical equations,
relatively simple and primitive set of Boolean & arithmetic      sequential control statements subprograms, or through
operations and are based on a hierarchy of operations that       concurrent statements [3]. Designing at a higher level of
are built by using algorithms employing the hardware. Speed,     abstraction delivers the following benefits [10]:
power and utilization of ALU are the measures of the
efficiency of an algorithm. In this paper, we have simulated          • Manages complexity: Fewer lines of code improves
and synthesized the various parameters of ALUs by using                   productivity and reduces error.
VHDL on Xilinx ISE 9.2i and SPARTAN 3E FPGA board.                    • Increases design reuse: Implementation of
Keywords: FPGA, ALU, XILINX                                               independent designs as cell library & reuse in
                                                                          various models.
                                                                      • Improves verification: Helps to run process faster
The design and implementation of FPGA based
Arithmetic Logic Unit is of core significance in digital
technologies as it is an integral part of central processing
unit. ALU is capable of calculating the results of a wide
variety of basic arithmetical and logical computations.
The ALU takes, as input, the data to be operated on
(called operands) and a code, from the control unit,
indicating which operation to perform. The output is the
result of the computation. Designed ALU will perform the
following operations:
• Arithmetic operations
• Bitwise logic operations
All the modules described in the design are coded using
VHDL which is a very useful tool with its degree of                          Figure 1 Block Diagram of ALU [6]
concurrency to cope with the parallelism of digital
hardware. The top level                                          3. OPERATION OF ALU
module connects all the stages into a higher level at            There are two kinds of operation which an ALU can
Register Transfer Logic (RTL). RTL describes the                 perform first part deals with arithmetic computations and
requirements of data and control units in terms of digital       is referred to as Arithmetic Unit. It is capable of addition,
logic to execute the desired operations. Each instruction        subtraction, multiplication, division, increment and
from the architecture's instruction set is defined in detail     decrement. The second part deals with the Gated results
in the RTL Once identifying the individual approaches            in the shape of AND, OR, XOR, inverter, rotate, left shift
for input, output and other modules, the VHDL                    and right shift, which is referred to as Logic Unit. The
descriptions are run through a VHDL simulator and then           functions are controlled and executed by selecting
is downloaded the design on FPGA board for verification.         operation or control bits.
                                                                    3.1 Software Approach
2. DESIGN OF TOP LEVEL (RTL) VHDL ODULE                          The VHDL software interface used in this design reduces
OF 4- BIT ARITHMETIC LOGICAL UNIT (ALU)                          the complexity and also provides a graphic presentation
                                                                 of the system. The key advantage of VHDL when used for
                                                                 systems design is that it allows the behavior of the

Volume 1, Issue 2 July-August 2012                                                                                 Page 146
   International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)
       Web Site: Email:,
Volume 1, Issue 2, July – August 2012                                          ISSN 2278-6856

required system to be described (modeled) and verified         ALU Specifications:
(simulated) before synthesis tools translate the design into                      Table 1
real hardware (gates and wires). This software not only          OPCOD       OPERATION SPECIFICATIONS
compiles the given VHDL code but also produces                   E
waveform results.                                                0000                A             Y is assigned the
   3.2 Hardware Approach                                                                           value of a (input)
The VHDL code which implies the hardware part of ALU             0001            NOT a             Y is assigned the
is downloaded on FPGA processor using JTAG cable                                                   value of NOT a
interfacing PC and the hardware element. A final point is        0010                B             Y is assigned the
that when a VHDL model is translated into the "gates and                                           value of b (input)
wires" that are mapped onto a programmable logic device          0011            NOT b             Y is assigned the
i.eFPGA, and then it is the actual hardware being                                                  value of NOT b
configured, rather than the VHDL code being "executed"           0100           a AND b            Y is assigned the
as if on some form of a processor chip.                                                            value of a AND b
                                                                 0101            a OR b            Y is assigned the
 4. VHDL CODE OF 4- BIT ALU                                                                        value of a OR b
Following portion of the VHDL code uses Data Flow                0110          a NAND b            Y is assigned the
Style of Modeling for implementation Logical and                                                   value of a NAND b
Arithmetic functions:                                            0111           a NOR b            Y is assigned the
                                                                                                   value of a NOR b
  library IEEE;                                                  1000           a XOR b            Y is assigned the
  use IEEE.STD_LOGIC_1164.ALL;                                                                     value of a XOR b
  use IEEE.STD_LOGIC_ARITH.ALL;                                  1001                a+1           Y is assigned the
                                                                                                   value of increment a
  entity alu is
     Port ( a : in STD_LOGIC_VECTOR (03                          1010                b+1           Y is assigned the
           downto 0);                                                                              value of increment
           b : in STD_LOGIC_VECTOR (03                                                             b
           downto 0);                                            1011                a+b           Y is assigned the
          opcode : in STD_LOGIC_VECTOR                                                             value of a + b
          (03 downto 0);                                         1100                a-1           Y is assigned the
          y : out STD_LOGIC_VECTOR (03                                                             value of a -1
          downto 0));                                            1101                b-1           Y is assigned the
  end alu;
                                                                                                   value b-1
  Architecture Behavioral of alu is
  begin                                                          1110                a-b           Y is assigned the
  with opcode (3 downto 0) select                                                                  value of a -b
  y<= a when "0000",                                             1111          a XNOR b            Y is assigned the
      (not a) when "0001",                                                                         value a XNOR b
       b when "0010",
       (not b) when "0011",
        a and b when "0100",
        a or b when "0101",
                                                               5. SYNTHESIS RESULT
        a nand b when "0110",                                    5.1 RTL VIEW
        a nor b when "0111",
        a xor b when "1000",
        a+1 when"1001",
        b+1 when "1010",
        a+b when "1011",
        a-1 when "1100",
         b-1 when "1101",
         a-b when "1110",
         a xnor b when "1111",
          "0000" when others;
  end Behavioral;


Volume 1, Issue 2 July-August 2012                                                                              Page 147
   International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)
       Web Site: Email:,
Volume 1, Issue 2, July – August 2012                                          ISSN 2278-6856

                                                          7. IMPLEMENTATION OF ALU ON FPGA BOARD

                                                          The VHDL coding of this paper design is compiled and
                                                          simulated using Xilinx ISE 9.2 i and has been
                                                          downloaded in FPGA using SpartanXC3S100E kit as
                                                          shown in Figure 4 The data is updated in the kit using
                                                          two separate select inputs A and B each carrying 4 bits.
                                                          The function of FPGA is embedded on the kit along with
                                                          PROM, LCD, LEDs and DIP switches. A Joint Test
                                                          Action Group (JTAG) interface connects the FPGA chip
                                                          with PROM and leads to PC through a serial interface.
                                                          Since FPGA is a user programmable, therefore JTAG is
                                                          of core significance. PROM has several postulates in the
                                                          shape of data storage and debugging, permanent storage
                                                          of data, consistency of operation, low cost, high speed and
                                                          compactness. PROM used in this design of
                                                          ALUis“XC10S”, which is equipped with the inbuilt
                                                          circuitry to support and store complex functions.

                        Fig. 3
5.2 Technology View

                                                                                 Figure 6 [11]

                       Figure 4

By behavioral simulation for a-b where a = 10 & b = 8:-
Y = a-b =2, gives following results:

                                                                                 Figure 7[11]
                                                          In real time application, after the process of compilation
                                                          and simulation of the VHDL design, the hardware
                                                          realization is carried out and tested as shown in Fig. 5.
                                                          Here the 4-bit inputs are given by means of two sets of
                                                          DIP switches and the output can be displayed on a LCD
                       Figure 5                           panel and the result can be verified with the simulated
                                                          output. The status of the flag registers is indicated by a

Volume 1, Issue 2 July-August 2012                                                                        Page 148
   International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)
       Web Site: Email:,
Volume 1, Issue 2, July – August 2012                                          ISSN 2278-6856

series of 8-bit LEDs. The provision of a select switch used   published a book titled “Digital System Design” by
in this hardware enables the user to perform the required     SciTech Publication in 2009.Editor of 05 Technical
operation on the FPGA processor.                              Proceedings of National & International Seminars.
                                                              Convener of many National and International
8. CONCLUSION                                                 Symposium. Life member of IETE & ISTE. Awarded as
                                                              best academic personality& HOD in 2007 and 2008
This study helped to understand the complete flow of
                                                              NIEC, Delhi. Convener of Research Journal of KIIT
RTL design, starting from designing a top level RTL
                                                              College of Engineering
module for 4-bit ALU using hardware description
language, VHDL. Verification of the designed RTL code         Shikha Khurana (Lecturer , KIIT, Gurgaon) received
using simulation techniques, synthesis of RTL code to         B.E (ECE) from Sant Longowal Institute of Engineering
obtain gate level netlist using Xilinx ISE tool and           & Technology (Punjab)in 2004 and presently pursuing
Arithmetic Logic Unit was successfully designed and           M.Tech. from MDU , Rohtak. Member of Institution of
implemented using Very High Speed Hardware                    Engineers India (IEI).
Descriptive Language and Xilinx Spatan-3E Field
Programmable Gate Array.

  [1] B.Stephen Brown, V.Zvonko, “Fundamentals of
  digital logic with VHDL Design”2ndEdition,Mc Graw
  Hill International Edition, 2005.
  [2]Charles H.Roth, Jr., “Digital System Design using
  VHDL”, PWS Publishing Company, 2006.
  [3] Douglas L. Perry, VHDL, third edition, McGraw-
  Hill, pp. 60-63, 238, July 1999.
  [4].Mark Zwolinski, “Digital System Design with
  VHDL”, Prentice Hall, 2000.
  [5] Pedroni, “Digital Logic Design using VHDL”.
  [6] S.Kaliamurthy, R.Muralidharan, “VHDL Design of
  FPGA Arithmetic Processor” International Conference
  on Engineering and ICT, 2007.
  [7] Digilent, Inc.., Spartan 3E Starter Board, Date
  Accessed June 2000
  [8] Fraunhofer IIS, “From VHDL and Verilog to
  [9]Xilinx Technologies, Xilinx Data Sheet for
  [11]Prof. S. Kaliamurthy & Ms. U. Sowmmiya,
  “VHDL design of arithmetic processor” ,Global
  Journals Inc.(USA) , November 2011.

                 Kanika Kaur (Associate Professor,
                 KIIT,     Gurgaon)    received   B.Sc
                 (Electronics) Hons. Degree from Delhi
                 University in 1997 and M.Sc
                 (Electronics) Hons. Degree from Jamia
                 Millia Islamia University in 1999.She
                 received M.Tech degree from RTU in
2005 and presently pursuing Ph.D from the JJTU,
Rajasthan in the field of “Low power VLSI design-
subthreshold leakage reduction technique for CMOS”.
Published more than 20 research papers in national,
international journal & conferences. She has also

Volume 1, Issue 2 July-August 2012                                                                       Page 149

Description: International Journal of Emerging Trends & Technology in Computer Science (IJETTCS) is an online Journal in English published bimonthly for scientists, Engineers and Research Scholars involved in computer science, Information Technology and its applications to publish high quality and refereed papers. Papers reporting original research and innovative applications from all parts of the world are welcome. Papers for publication in the IJETTCS are selected through rigid peer review to ensure originality, timeliness, relevance and readability. The aim of IJETTCS is to publish peer reviewed research and review articles in rapidly developing field of computer science engineering and technology. This journal is an online journal having full access to the research and review paper. The journal also seeks clearly written survey and review articles from experts in the field, to promote intuitive understanding of the state-of-the-art and application trends. The journal aims to cover the latest outstanding developments in the field of Computer Science and engineering Technology.