project41 appendix by o9S16v4

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									                                 Appendix A – Code Samples:

Code sample 1: PIC code for driving the LCD with input on the A/D channels 1-4
          list       p=16f877A                ; list directive to define processor
          #include   <p16f877A.inc>           ; processor specific variable definitions

          __CONFIG _WDT_OFF & _BODEN_OFF & _XT_OSC      & _LVP_OFF & _PWRTE_ON


;***** VARIABLE DEFINITIONS
COUNTX         equ     0x20
DELAYX         equ     0x21
TEMP           equ     0x22
WTEMP          equ     0x23
STEMP          equ     0x24
TMLO           equ     0x25
TMMID          equ     0x26
TMHI           equ     0x27
VOLT0          equ     0x28
VOLT1          equ 0x29
VOLT2          equ 0x2A
VOLT3          equ 0x2B
TEMPVOLT       equ 0x2C
VOLT0ADD       equ     0x2D
VOLT1ADD       equ     0x2E
VOLT2ADD       equ 0x2F
VOLT3ADD       equ 0x30
RS                     equ         0
RW                     equ         1
E                      equ         2

;**********************************************************************
                       ORG     0x000       ; processor reset vector

                          goto     Main           ; go to beginning of program


                          ORG       0x004         ; interrupt vector location
                          movwf    WTEMP            ; save status
                          swapf    STATUS, w
                          movwf    STEMP

                          movf     VOLT0, w         ; move VOLT0 into work
                          movwf    TEMPVOLT         ; move work into TEMPVOLT
movwf PORTC
                          rrf             TEMPVOLT, f    ; divide TEMPVOLT by 2
                          rrf             TEMPVOLT, f    ; divide TEMPVOLT by 2
                          rrf             TEMPVOLT, f    ; divide TEMPVOLT by 2
                          rrf             TEMPVOLT, f    ; divide TEMPVOLT by 2
                          movf     TEMPVOLT, w   ; move TEMPVOLT to work
                          andlw    0x0F          ; clear the four upper bits of work

                          movwf    TEMPVOLT         ; move work to TEMPVOLT

                          movlw    0x01             ; return home and clear display
                          call     Wcommand

                          movf     TEMPVOLT, w      ; move TEMPVOLT into work
                          btfsc    STATUS, Z        ; if the zero flag is clear, this will be
true
                          goto     NextLine1        ; and this will be skipped

Display          movlw    0xFF             ; write block to the display
                          call     Wdata

                          decfsz TEMPVOLT, f        ; decrement TEMPVOLT, exit loop if zero
                          goto   Display




                                                  A.1
;-----------------------------------------
NextLine1      ;clrf TMR0             ; clear timer

                       movlw   0xC0           ; move the cursor to the next line
                       call    Wcommand

                       movf    VOLT1, w       ; move VOLT1 into work
                       movwf   TEMPVOLT       ; move work into TEMPVOLT

                       rrf            TEMPVOLT, f    ; divide TEMPVOLT by 2
                       rrf            TEMPVOLT, f    ; divide TEMPVOLT by 2
                       rrf            TEMPVOLT, f    ; divide TEMPVOLT by 2
                       rrf            TEMPVOLT, f    ; divide TEMPVOLT by 2
                       movf    TEMPVOLT, w   ; move TEMPVOLT to work
                       andlw   0x0F          ; clear the four upper bits of work

                       movwf   TEMPVOLT       ; move work to TEMPVOLT

                       movf    TEMPVOLT, w    ; move TEMPVOLT into work
                       btfsc   STATUS, Z      ; if the zero flag is clear, this will be
true
                       goto    NextLine2      ; and this will be skipped

Display1       movlw   0xFF            ; write block to the display
                       call    Wdata

                       decfsz TEMPVOLT, f    ; decrement TEMPVOLT, exit loop if zero
                       goto   Display1
;------------------------------------------
NextLine2      ;clrf TMR0             ; clear timer

                       movlw   0x90           ; move the cursor to the next line
                       call    Wcommand

                       movf    VOLT2, w       ; move VOLT2 into work
                       movwf   TEMPVOLT       ; move work into TEMPVOLT

                       rrf            TEMPVOLT, f    ; divide TEMPVOLT by 2
                       rrf            TEMPVOLT, f    ; divide TEMPVOLT by 2
                       rrf            TEMPVOLT, f    ; divide TEMPVOLT by 2
                       rrf            TEMPVOLT, f    ; divide TEMPVOLT by 2
                       movf    TEMPVOLT, w   ; move TEMPVOLT to work
                       andlw   0x0F          ; clear the four upper bits of work

                       movwf   TEMPVOLT       ; move work to TEMPVOLT

                       movf    TEMPVOLT, w    ; move TEMPVOLT into work
                       btfsc   STATUS, Z      ; if the zero flag is clear, this will be
true
                       goto    NextLine3      ; and this will be skipped

Display2       movlw   0xFF            ; write block to the display
                       call    Wdata

                       decfsz TEMPVOLT, f    ; decrement TEMPVOLT, exit loop if zero
                       goto   Display2
;------------------------------------------
NextLine3      ;clrf TMR0             ; clear timer

                       movlw   0xD0           ; move the cursor to the next line
                       call    Wcommand

                       movf    VOLT3, w       ; move VOLT3 into work
                       movwf   TEMPVOLT       ; move work into TEMPVOLT

                       rrf            TEMPVOLT, f    ; divide TEMPVOLT by 2
                       rrf            TEMPVOLT, f    ; divide TEMPVOLT by 2
                       rrf            TEMPVOLT, f    ; divide TEMPVOLT by 2
                       rrf            TEMPVOLT, f    ; divide TEMPVOLT by 2
                       movf    TEMPVOLT, w   ; move TEMPVOLT to work
                       andlw   0x0F          ; clear the four upper bits of work



                                             A.2
                      movwf    TEMPVOLT        ; move work to TEMPVOLT

                      movf     TEMPVOLT, w     ; move TEMPVOLT into work
                      btfsc    STATUS, Z       ; if the zero flag is clear, this will be
true
                      goto     EndISR          ; and this will be skipped

Display3      movlw   0xFF              ; write block to the display
                      call     Wdata

                       decfsz TEMPVOLT, f    ; decrement TEMPVOLT, exit loop if zero
                       goto   Display3
;------------------------------------------
EndISR         clrf    TMR0           ; clear timer

                      swapf    STEMP, w
                      movwf    STATUS
                      swapf    WTEMP, f
                      swapf    WTEMP, w
                      bcf             INTCON, T0IF
                      bcf             INTCON, 2
                      retfie                            ; return from interrupt


;************Delay routine********************
;
;      0.5 ms time delay called by Xdelayo
;      requires multiplier already in work register
;
;*********************************************
Delay500
                       movlw 0xA5
                       movwf COUNTX
Delay5loop     decfsz COUNTX, f
                       goto   Delay5loop
                       return

Xdelay        movwf   DELAYX
Xdelloop      call    Delay500
                      decfsz DELAYX, f
                      goto   Xdelloop
                      return

;**************Checks for busy flag************
Busyflag
                       bsf            STATUS, RP0    ;bank 1
                       movlw 0xFF            ;change PortD to all inputs
                       movwf TRISD
                       bcf            STATUS, RP0    ;bank 0

Busy          bcf              PORTB, E        ;clear   enable
                      bcf             PORTB,   RS        ;command
                      bsf             PORTB,   RW        ;read
                      bsf             PORTB,   E         ;enable
                      btfsc    PORTD, 7        ;check   for busy flag
                      goto     Busy            ;still   busy...

                      bcf               PORTB, E       ;clear enable
                      bsf               STATUS, RP0    ;bank 1
                      clrf     TRISD           ;back to all outputs
                      bcf               STATUS, RP0    ;bank 0

                      return

;**************Write command byte*************
Wcommand
                       movwf TEMP
                       call   Busyflag
                       movf   TEMP, w




                                             A.3
Command       bcf              PORTB, RS     ;command
                      bcf             PORTB, RW      ;write
                      bsf             PORTB, E       ;enable

                      movwf    PORTD            ;send command
                      bcf                PORTB, E       ;clear enable

                      return

;**************Write data byte*****************
Wdata
                       movwf TEMP
                       call   Busyflag
                       movf   TEMP, w

                      bsf                PORTB, RS          ;data
                      bcf                PORTB, RW          ;write
                      bsf                PORTB, E           ;enable

                      movwf    PORTD            ;send data byte
                      bcf                PORTB, E       ;clear enable

                      return



Main          ;Initialize Pic

                      bcf                STATUS, RP1        ;Select Bank0
                      bcf                STATUS, RP0

                      clrf     PORTA            ; Clear ports
                      clrf     PORTB
                      clrf     PORTC
                      clrf     PORTD

                      bsf                STATUS, RP0        ; Select Bank1

                      clrf     TRISB            ;    Make   portB   output
                      clrf     TRISC            ;    Make   portC   output
                      clrf     TRISD            ;    Make   portD   output
                      movlw    0xFF             ;    Make   portA   inputs
                      movwf    TRISA

                      movlw    0x08             ; portA analog, RA3 reference
                      movwf    ADCON1

                      clrf     INTCON           ; clear flags

                      clrf     TMR0             ; clear timer
                      movlw    0x04             ; internal clock, TMR0 assign, and
                      movwf    OPTION_REG       ; prescale 1:256
                                                               ; PortB weak pullups +
falling edge int

                      bcf                STATUS, RP0        ; Bank0

                      movlw    0x41             ; 8Tosc, channel 0, AD on
                      movwf    ADCON0

                      ; LCD initialization stuff-----------------------
                      movlw 0x28            ;40
                      call   Xdelay         ;time delay of 500us x 40 = 20ms

                      movlw    0x38             ;function set command
                      call     Command          ;send command

                      movlw    0x09             ;9
                      call     Xdelay           ;4.5 ms delay

                      movlw    0x38



                                              A.4
                      call    Command

                      movlw   0x01             ;1
                      call    Xdelay           ;500 us delay

                      movlw   0x38
                      call    Command

                      call    Wcommand         ;start checking for busy flag
                                                                      ;8 bit interface, 2
lines, 5x7 font

                      movlw   0x08             ;display off
                      call    Wcommand

                      movlw   0x01             ;clear display
                      call    Wcommand

                      movlw   0x06             ;Entry mode
                                                                ;increment right, display not
shifted
                      call    Wcommand

                      movlw   0x0C             ;display on, cursor off
                      call    Wcommand

                      movlw 0x01            ;Return home
                      call   Wcommand
                      ;------------------------------------------------

                      clrf    TMR0
                      movlw   0xA0             ; set interupts GIE,    TMR0IE
                      movwf   INTCON

Start         movlw   0x41              ; 8Tosc, channel 0, AD on
                      movwf   ADCON0

                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop               ;21 usecond delay for AD acq

                      bsf               ADCON0, 2      ;set GO bit
Wait0         btfss   PIR1, ADIF        ;poll for AD flag
                      goto   Wait0

                      bcf               PIR1, ADIF

                      movf    ADRESH, w
                      movwf   VOLT0



                                             A.5
;-------------------------------------------------------

                      movlw   0x49            ;8Tosc, channel 1, AD on
                      movwf   ADCON0

                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop              ;21 usecond delay for AD acq

                      bsf              ADCON0, 2      ;set GO bit
Wait1         btfss   PIR1, ADIF       ;poll for AD flag
                      goto   Wait1

                      bcf              PIR1, ADIF

                      movf    ADRESH, w
                      movwf   VOLT1

                      ;-----------

                      movlw   0x61            ;8Tosc, channel 4, AD on
                      movwf   ADCON0

                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop
                      nop              ;21 usecond delay for AD acq



                                            A.6
                bsf              ADCON0, 2      ;set GO bit
Wait2   btfss   PIR1, ADIF       ;poll for AD flag
                goto   Wait2

                bcf              PIR1, ADIF

                movf    ADRESH, w
                movwf   VOLT2

                ;-----------

                movlw   0x69            ;8Tosc, channel 5, AD on
                movwf   ADCON0

                nop
                nop
                nop
                nop
                nop
                nop
                nop
                nop
                nop
                nop
                nop
                nop
                nop
                nop
                nop
                nop
                nop
                nop
                nop
                nop
                nop
                nop
                nop
                nop
                nop              ;21 usecond delay for AD acq

                bsf              ADCON0, 2      ;set GO bit
Wait3   btfss   PIR1, ADIF       ;poll for AD flag
                goto   Wait3

                bcf              PIR1, ADIF

                movf    ADRESH, w
                movwf   VOLT3

                goto    Start



        END




                                      A.7
Code Sample 2: Selected assembly code from DSP – Equalizer function

_equalizer
       ENTER_ASM

  STM                  #_fft_data,AR3                             ; AR3 -> original FFT
  ;STM          #_eq_fft,AR3                        ; AR3 -> amplified FFT, use if
amplify() is called

  STM                  #slide1,AR2                          ; AR2 -> current scale factor
(one of the slide values)

   ;STM        #_eq_fft,AR7                         ; AR7 -> filtered FFT
   STM                 #_bit_rev_data,AR7                  ; AR7 -> filtered FFT,
originally from fft_data

  ;loop through 4 diff ranges of the FFT and scale each according to sliders
  ;Xmem and Ymem can only be AR2 thru AR5
;#N/4-1,BRC;

low:
        ST #5, BRC ; 3*2 samples
        RPTB mid1 - 1
        MPY *AR3+, *AR2, A
        STH A, *AR7+ ; *remember we are now storing in bit_rev_data
mid1:
        MAR *AR2+
        ST #21, BRC ; 11*2 samples
        RPTB mid2 - 1
        MPY *AR3+, *AR2, A
        STH A, *AR7+
mid2:
       MAR *AR2+
  ST #113, BRC ; 57*2 samples
       RPTB high - 1
       MPY *AR3+, *AR2, A
       STH A, *AR7+
high:
       MAR *AR2+
  ST #881, BRC ; 441*2 samples
       RPTB high_neg - 1
       MPY *AR3+, *AR2, A
       STH A, *AR7+
high_neg:

;now repeat this process for the negative frequencies



                                            A.8
  ST #883, BRC ; 442*2 samples
      RPTB mid2_neg - 1
      MPY *AR3+, *AR2, A
      STH A, *AR7+
mid2_neg:
      MAR *AR2-
  ST #113, BRC ; 57*2 samples
      RPTB mid1_neg - 1
      MPY *AR3+, *AR2, A
      STH A, *AR7+
mid1_neg:
      MAR *AR2-
  ST #21, BRC ; 11*2 samples
      RPTB low_neg - 1
      MPY *AR3+, *AR2, A
      STH A, *AR7+
low_neg:
      MAR *AR2-
  ST #3, BRC ; 2*2 samples
      RPTB done - 1
      MPY *AR3+, *AR2, A
      STH A, *AR7+
done:

; filtered FFT data is now in bit_rev_data

; now perform inverse fft to reconstruct the audio
; inversefft can be done by taking complex conjugate of fft, then performing fft and
normalizing by N
;the complex conjugation is performed below
;fft must be used on the resulting data later in main

       STM       #_bit_rev_data,AR5           ; (source &) destination of conjugation is
bit_rev_data

       ST #N-1, BRC
       RPTB conjugate - 1
       MAR          *AR5+                                    ; skip over the real parts
       MPY *AR5,#-32767,A               ; negate the imaginary parts
       STH      A, *AR5+            ; store neg im parts back into bit_rev_data
conjugate:
       NOP

       LEAVE_ASM

 RET



                                             A.9
Code Sample 3: Selected assembly code from DSP – Serial data acquisition

Based on code written by I-Ju Liao and Jung-Gyu Lee, available at
http://cnx.org/content/m12062/latest/

;-----------function for obtaining serial data of fader values-----------------------------
;never fully functional, but a start

;the slider values will be 4 8-bit words corresponding the the fraction of the
; reference voltage coming in from each of 4 potentiometers
; we will store these fractions as scale values for the 4 frequency bands
; the equalizer
; the Tx format will be startword-startword-startword-slide1-slide2-slide3-slide4
; from the PIC

_get_data
       ENTER_ASM

     pshm AR0            ; we save all registers that are used in
     pshm AR2            ; this function - note that accumulator
     pshm AR3            ; B IS OVERWRITTEN!
     pshm AR4
     pshm BK

     mvdm #srx_head, AR2 ; srx_head, defined in core.asm, points
               ; to one element past the last value
               ; recieved in the serial recieve buffer

     stm #ser_rxlen, BK ; set BK to length of receive buffer

     stm #testserial, AR4 ; address of current word holder for comparison to start word

     mar *+AR2(-15)% ; AR2 now points to the most recently
               ; received block of 14 words, should have a full set of 7

     stm #1, AR0          ; set increment
     LD #14, A           ; counter for total checks, just check the past 14 bytes

check:
    mvdd *AR2+0%, *AR4 ;load in first word
    CMPM *AR4, 00EEh ; check if this is a start word, if so...
    BC #found1,TC      ; go check if the next word is also start
    sub #1, A
    BC exitserial, AEQ     ; if we've check 14 words and no dice, just exit
    B #check




                                               A.10
found1:
    mvdd *AR2+0%, *AR4 ; load in next possible start word
    CMPM *AR4, 00EEh ; check if this is a start word, if so...
    BC #found2,TC      ; go check if the next word is also start
    sub #1, A
    BC exitserial, AEQ ; if we've check 14 words and no dice, just exit
    B #check

found2:
    mvdd *AR2+0%, *AR4 ;load in third possible start word
    CMPM *AR4, 00EEh ; check if this is a start word, if so...
    BC #found3,TC      ; get the next 4 words, they should be slider values
    sub #1, A
    BC exitserial, AEQ      ; if we've check 14 words and no dice, just exit
    B #check

found3:
    stm #slide1, AR3 ; get first slider
    ld *AR2+%, 7, B ; place 8 bits into MSBs of B
    stl B, *AR3+    ; save at slide1, AR3 points to slide2

    ld *AR2+%, 7, B ; place 8 bits into MSBs of B
    stl B, *AR3+   ; save at slide2, AR3 points to slide3

    ld *AR2+%, 7, B ; place 8 bits into MSBs of B
    stl B, *AR3+   ; save at slide3, AR3 points to slide4

    ld *AR2+%, 7, B ; place first 8 bits in high part of B
    stl B, *AR3    ; save at slide4

exitserial:
     popm BK
     popm AR4
     popm AR3
     popm AR2
     popm AR0

    LEAVE_ASM

    Ret




                                          A.11
Code sample 4: Matlab script for implementing FFT convolution equalizer

% fftconv.m
% Matlab script that performs the FFT convolution of an audio sample
for
% the purposes of equalization.
%
% music.mat must be in the current workspace and contain an array of
music
% samples corresponding to the sequence of music to be equalized.
%
% modify scale1, scale2, scale3, scale4 below to modify the boost and
cut
% ratios for the lows, lowmids, highmids, and highs, respectively.
%
% Created 2007 by Cristina Vasco
% University of Illinois at Urbana-Champaign

clear;load music;

%play the original sample
boomplay = audioplayer(music,44100);
playblocking(boomplay);

%try... each column is actually a 512-block...
for i=1:length(music)/512
    for j=1:512
        boom2D(j,i)=music((i-1)*512+j);
    end
end
%..zero-padded by 256 on each side (512 total)
boom2D = padarray(boom2D, 256);

%fft(boom2D) will operate on each column
boomfft = fft(boom2D);

%now we modify the fft, inverse it, and play it
%low numbered rows = low freqs, and so on

%just to initialize the array size:
boomfftEQ = boomfft;

%scaling   coefficents for the different bands
scale1 =   1.5;
scale2 =   0.3;
scale3 =   0.45;
scale4 =   1.4;

%modify the bass...
boomfftEQ(1,:) = boomfft(1,:)*scale1;
for i=[2:3]
    G1 = scale1; %+ (scale2-scale1)/3*(i-1); % use for linear
interpolation
    boomfftEQ(i,:) = boomfft(i,:)*G1 ;         %'neg' frequencies
    boomfftEQ(1024-i+2,:)= boomfft(1024-i+2,:)*G1;   % pos frequencies


                                     A.12
end

%modify the mids...
for i=[4:14]
    G2 = scale2; % + (scale3-scale2)/11*(i-4); % use for linear
interpolation
    boomfftEQ(i,:) = boomfft(i,:)*G2;         %'neg' frequencies
    boomfftEQ(1024-i+2,:)= boomfft(1024-i+2,:)*G2;   % pos frequencies
end

for i=[15:70]
    G3 = scale3; % + (scale4-scale3)/57*(i-15); % use for linear
interpolation
    boomfftEQ(i,:) = boomfft(i,:)*G3;         %'neg' frequencies
    boomfftEQ(1024-i+2,:)= boomfft(1024-i+2,:)*G3;   % pos frequencies
end

%modify the highs..
for i=[71:(1024-69)]
    boomfftEQ(i,:) = boomfft(i,:)*scale4;
end

%inverseFFT - equivalent to fft of complex conjugate
%this method is implemented in the DSP
reboomEQ2D = fft(conj(boomfftEQ))/1024;

%declare the array that will be the final prodct
reboomEQ = music;
%zero everthing out
for i=1:size(reboomEQ)
    reboomEQ(i) = 0;
end
%add 1024 extra samples for leadin and leadout
reboomEQ = padarray(reboomEQ, 512);

%reconstruct audio by overlapping samples
for i=1:size(boomfftEQ,2)
    reboomEQ((512*(i-1)+1):512*(i-1)+1024) = reboomEQ((512*(i-
1)+1):512*(i-1)+1024) + real(reboomEQ2D(:,i));
end

%play the equalized audio
playerEQ = audioplayer(reboomEQ,44100);
play(playerEQ);


% the following code will play a video of the fft response of the
equalized
% audio
% for i=1:size(boomfft,2)
%     plot(abs(boomfft(:,i)));
%     fftvid(i)=getframe;
% end

fftdiff = abs(boomfftEQ)./abs(boomfft);


                                  A.13
% Generate figures showing FFT before, FFT after, and difference for
one
% frame of samples
frequencies = 0:511;
frequencies = (frequencies*44100/1024)+1;
figure;semilogx(abs(boomfft(1:512,1)));
xlabel('Frequency (Hz)');
ylabel('abs(originalFFT)');
title('Magnitude of FFT for original audio');
figure;semilogx(frequencies,abs(boomfftEQ(1:512,1)));
xlabel('Frequency (Hz)');
ylabel('abs(equalizedFFT)');
title('Magnitude of FFT after equalization');
figure;semilogx(frequencies,fftdiff(1:512,1));
xlabel('Frequency (Hz)');
ylabel('abs(equalizedFFT)/abs(originalFFT)');
title('Magnitude of frequency response for EQ filtering');




                                  A.14
                     Appendix B: Figures and Schematics:
Figure 1: Updated block diagram




Figure 2: PIC used in the project




Figure 3: LCD used in the project




                                    A.15
Figure 4: Serial data on the oscilloscope coming from the PIC




Figure 5: Schematics of the circuits used in the LCD display unit
                            DSP                                                                                                             +5V


                                                                                                                                                  10K POT
Sound IN                                                       Channel
                                                               Channel
                                                                         1
                                                                         2                        PIC AND LCD CIRCUIT
                                                               Channel   3                                                                                    HD44780
                                                               Channel   4

                                  DSP
                                                                                    Channel   1     2                                  15
                                                                                    Channel   2     3    RA0         RC0/T1OSI/T1CLK   16
                                                                                    Vref+           4    RA1              RC1/T1OSO    17
                                                                                                         RA2               RC2/CCP1
                                                                                    Vref-           5
                                                                                                         RA3            RC3/SCK/SCL
                                                                                                                                       18                   VSS
                                                                                    Channel   3     6
                                                                                                         RA4/T0CLK      RC4/SDI/SDA
                                                                                                                                       23                   VDD
                                                                                    Channel   4     7                                  24
                                                                                                         RA5/SS             RC5/SDO
                                                                                                                                 RC6
                                                                                                                                       25                   D/I
                                                                                                    33
                                                                                                         RB0/INT                 RC7
                                                                                                                                       26                   R/W
                                                                                                    34
                                                                                                         RB1                                                E
                                                                                                    35
                                                                                                         RB2               RD0/PSP0
                                                                                                                                       19                   DB0
                                                                                                    36
                                                                                                         RB3               RD1/PSP1
                                                                                                                                       20                   DB1     LCD
                                                                                                    37
                                                                                                         RB4               RD2/PSP2
                                                                                                                                       21                   DB2
                                                                                                    38
                                                                                                         RB5               RD3/PSP3
                                                                                                                                       22                   DB3
                                                                                                    39
                                                                                                         RB6               RD4/PSP4
                                                                                                                                       27                   DB4
                                                                                                    40
                                                                                                         RB7               RD5/PSP5
                                                                                                                                       28                   DB5
                                                                                                                           RD6/PSP6
                                                                                                                                       29                   DB6
                                                                                                    13
                                                                                                         OSC1/CLK          RD7/PSP7
                                                                                                                                       30                   DB7
                                                                                                    14
                                                                                                         OSC2/CLKOUT                   8
                                                                                                                            RE0/RD
                                                                                                    1
                                                                                                         MCLR/VPP           RE1/WR
                                                                                                                                       9                    RESET
       REFERENCE VOLTAGE CIRCUIT                                                                    11                      RE2/CS
                                                                                                                                       10                   VEE
                                                                             4MHz                   32   VDD
       +5V                                                                                               VDD

                                                                                                         PIC16F877

  4k             R10

                       U4
                       +
                                                                   Vref+
  1k             R11        OUT
                                                                                              0
                       -                               R12
                            OPAMP
                                             R13

                                        3k              1k
                                                             OPAMP
                                                   -

             0                                               OUT     Vref-
                                                   +
                                                   U5

                                             0



                                                                              A.16
Figure 6: DSP Flowchart for FFT Convolution




                                       A.17
Figure 7: Spectrogram of logarithmic chirp




Figure 8: Filter responses to logarithmic chirp




                                           A.18
Figure 9: Original FFT




Figure 10: Equalized FFT




Figure 11: Ratio of FFTs, corresponds to EQ filter response




                                          A.19

								
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