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The Off-Detector Opto-electronics for the Optical Links
of the ATLAS SemiConductor Tracker and Pixel
Detector
M.L. Chu, S.-C. Lee, D.S. Su, P.K. Teng
Institute of Physics, Academia Sinica, Taiwan
M. Goodrick
Cavendish Laboratory, Cambridge University, UK
N. Kundu, A.R. Weidbergi
Physics Department, Oxford University, UK
M. French, C.P. Macwaters, J. Matheson
Rutherford Appleton Laboratory, UK
Abstract
The off-detector part of the optical links for the ATLAS SCT and Pixel detectors is
described. The VCSELs and p-i-n diodes used and the associated ASICs are Formatted: Font: Italic
described. A novel array packaging technique is explained and an analysis of the
performance of the arrays and the overall system performance is given.
PACS: 42.88, 04.40N, 85.40, 85.60.
Keywords: LHC; Optoelectronics; Data transmission; ASICs.
1. Introduction
Optical links will be used in the ATLAS SemiConductor Tracker (SCT) and Pixel
detectcor[1,2] to transmit data from the detector modules to the off-detector
electronics and to distribute the Timing, Trigger and Control (TTC) data from the
counting room to the front-end electronics[3]. The on-detector components are
described in references [4,5,6,7]. The overall system architecture of the SCT optical
links is reviewed briefly in Section 2. The specifications for the VCSELs and PINs
and the array packaging are given in Section 3. The associated ASICs are briefly
reviewed in Section 4. The performance of the arrays and the combined performance
of the arrays and ASICs were studied and the results are discussed in Section 5.
Finally some conclusions are given in Section 6.
2. System Architecture
The overall architecture of the SCT optical links is described in [1] and [332] and is
briefly reviewed here for convenience. The system is illustrated schematically in
Figure 1 below.
i
Corresponding author. Email: t.weiderg1@physics.ox.ac.uk
1
Figure 1 The ATLAS SCT optical links system architecture.
The links are based on GaAs VCSELsi emitting light around 850 nm and epitaxial
silicon p-i-n diodes. There are 12 ABCD ASICs[1] on each SCT module and each
ABCD reads out the signals from 128 channels of silicon strips. The ABCD ASIC
consists of 128 channels of preamplifiers and discriminators. The binary data from
each channel is stored in a pipeline memory and the binary data corresponding to a
first level trigger (L1) signal is read out. Two data links operating at 40 Mbits/s
transfer the data from the ABCD ASICs on each SCT modules to the off-detector
opto-electronics. The ABCD ASICs[1] send the data to the VDC ASIC[665] which
drives two VCSEL channels[443]. The data is sent in NRZii format via radiation hard
optical fibre[776] to the p-i-n diode arrays in the BOC card in the counting room. The Formatted: Font: Italic
electrical signals from the p-i-n diode arrays are discriminated by the DRX-12 ASIC Formatted: Font: Italic
which provides LVDS data used in the SCT RODs. Optical links are also used to send
the timing, trigger and control (TTC) data from the RODS to the SCT modules. The
BPM-12 ASIC uses biphase mark (BPM) encoding to send a 40 Mbits/s control
stream in the same channel as the 40 MHz bunch crossing clock. The outputs of the
BPM-12 ASIC drive an array of 12 channels of VCSELs which transmit the optical
signal into 12 radiation hard fibres. The signals are converted from optical to electrical
by the on-detector p-i-n diodes[554]. The electrical signals from the p-i-n diodes are Formatted: Font: Italic
received by the DORIC4A ASIC[665] which discriminates the signal and decodes the
i
Vertical Cavity Surface Emitting Lasers.
ii
Non Return to Zero.
2
BPM data into a 40 MHz Bunch Crossing (BC) clock and a 40 Mbit/s control data
stream.
The architecture of the optical links for the Pixel system is described in Ref.[2]. The
Pixel system uses essentially the same components for the off-detector end of the
optical links as the SCT. The one minor difference is that the Pixel system will use 8
way arrays, whereas the SCT uses 12 way arrays. The data links for the innermost
layer (“B layer”) of the Pixel system will be operated at 80 Mbits/s while the other
layers will be operated at the same speed as those for the SCT. The studies described
in this paper focussed on the SCT operation at 40 Mbits/s, although given the
measured speed of the links, the operation at 80 Mbits/s is not expected to pose any
problems.
Formatted: Font: Italic
3. VCSEL and p-i-n arrays
3.1 VCSELs
VCSELs [8] are used to transmit the TTC data to the front end modules optically. The
main advantage of VCSELs are that they provide large optical signals at very low
currents and have fast rise and fall times. In order to lower the laser threshold current
VCSELs use ion implants to selectively produce a buried current blocking layer to
funnel current through a small area of the active layer[9]. In older VCSELs this
current confinement was achieved with proton implants. These VCSELsi used in this
study havean an oxide implant to achieve the current confinement, implant which is
becoming the standard VCSEL technology as they produce lower thresholds and
higher bandwidth. than the older proton implant VCSELs. The one disadvantage for
this application found with the oxide confinedimplant VCSELs was the relatively
large opening angle (the FWHM of the optical output of these VCSELsii was 150).
This results in a very low coupling efficiency into the 50 m core step index multi-
mode (SIMM) fibre if no lens is used. In order to achieve a higher coupled power into
the SIMM fibre without the complication of the use of a lens, a special production run
was made with a lower reflectivity of the emitting surface which results in a slightly
higher threshold but a much larger slope efficiency. . The threshold increase was
rather small (~ 1mA) but there was a big increase in slope efficiency which results in a
much higher optical power at a nominal drive current of 10 mA Therefore it was
possible to obtain a typical fibre coupled power of greater than 1 mW at a drive
current of 10 mA.
The specifications for the VCSEL arrays are given in Table 1 below.
Table 1 Specifications for the VCSEL arrays.
Characteristics Min. Typical Max. Units
Wavelength 820 ~840 860 nm
i
TSA-8B12-00 Truelight, Taiwan.
ii
This was measured at a drive current of 6 mA.
3
Output power coupled into 0.7 1.2 - mW
50m core SIMM fibre @
BPM DAC setting of 165
(equivalent to 10 mA).
Threshold current 3 6 mA
Forward voltage @ 10mA 2 2.5 V
Reverse voltage 2 V
20%-80% Rise/Fall time 1 2 ns
Temperature range 10 20 50 °C (condition for package not
chip)
3.2 PINs
Arrays of silicon p-i-n diodes are used to receive the readout data from the front end Formatted: Font: Italic
modules. Epitaxial silicon p-i-n diodesi are used because the i I layer provides a thin Formatted: Font: Italic
active layer allowing for fast operation at low p-i-n bias voltage. The specifications for Formatted: Font: Italic
the p-i-n array are given in Table 2 below. Formatted: Font: Italic
Formatted: Font: Italic
Table 2 Specifications for the p-i-n arrays.
Characteristics Min. Typical Max. Units
Operating wavelength 820 840 860 nm
Input power 1 3 mW
Responsivity @ 820 –860 nm 0.4 0.5 A/W
and 5V bias
Dark current <1 2 nA
Reverse voltage 5 10 V
Breakdown voltage 15 20 V
20%-80% Rise/Fall time at 5V 1 2 ns
bias
Temperature range 10 20 50 °C (condition for package not
chip)
The active area of each individual p-i-n diode is circular with a diameter of 130 m Formatted: Font: Italic
and the depth of the i I region is 35 m.
3.3 Array Packaging
The parts for the opto array sub-assembly are shown in Figure 2 below. An identical
design is used for VCSEL and p-i-n array sub-assemblies, except for the opto array Formatted: Font: Italic
chip. The location of two precisely machined guide pins, define the location of fibres
in an MT connector when the connector is inserted. The array chip is placed precisely
on the base PCB with respect to the guide pins on the base PCB. The precise location
i
Designed by Truelight, Taiwan, manufactured by Episil ,Taiwan.
4
between guide pins and opto array chip guarantees the alignment of the active
elements of the array-opto chip to the optical fiberes. The opto-array chips are wire
bonded to the base PCB and the connection from the base PCB to the TX or RX PCBs
is done via the lead frames. The upper lead frame is used for the connections from the
12 individual anodes and the lower lead frame is used for the common cathode
connections.
Figure 2 Schematic view of opto-array-package assembly
4. ASICs
4.1 DRX-12
The DRX-12 ASIC contains 12 channels, each of which consists of a comparator with
an LVDSi output driver. The input comparators were designed to accept the electrical
signals from the p-i-n diode arrays. The DRX-12 was fabricated in the AMS 0.8 m Formatted: Font: Italic
BiCMOS process using npn bipolar transistors[6]. The basic units for the design were
copied from the DORIC4A ASIC. The input comparators are DC coupled unlike the
DORIC4A to allow for the NRZ data stream. Each channel of the DRX-12 hasd an
individually adjustable threshold which canould be set by an external voltage to
correspond to an input signal amplitude in the range 0 to 255 A. The other change to
the comparators, compared to the DORIC4A iswas that there iswas no hysteriesis. sis.
i
LVDS: Low Voltage Differential Signals for Scalable Coherent Interface (SCI) Draft 1.3 IEEE
P1596.3-1995.
5
4.2 BPM-12
The BPM-12 ASIC consisted of 12 channels of biphase mark encoding and VCSEL
drive circuitry. Each channel has an input 40 Mbits/s data stream and there was also a
common input 40 MHz system clock for all channels. The bBiphase mark encoding
scheme is a DC balanced code which creates extra transitions to encode data “1”s as
illustrated in Figure 3 below. The BPM-12 ASIC was also fabricateddesigned in the
AMS 0.8 m BiCMOS process but used only CMOS transistors.
6
25 nS
Clock input
25 nS
Data input
25 nS
BPM Output
Figure 3 Illustration of the biphaseBiPhase mMark Encoding Scheme. The top
trace shows the input clock signal and the middle trace shows the input data. The
bottom trace shows the resulting bBipPhase mark encoded data. The data “1” is
encoded as an extra transition in the output.
4.2.1 VCSEL Driver circuits
A very simple CMOS circuit iswas used to drive each channel of VCSELs. A
schematic diagram of one channel of the VCSEL driver circuit is shown in Figure 4
below. An external voltage (bias) is converted to a current by a 2k resistor and the
current is amplified by two current mirrors, each with a current gain of 4. The current
to the VCSEL is switched on or off by a logical level which corresponds to the
biphase mark encoded data for that channel. A small “bleed” current of around 1 mA
is sent to the VCSEL during the off period in order to ensure a fast turn on of the
VCSEL. The current to the VCSEL for each channel is was adjustable in the range 10
to 18 mA by means of an external voltage.
7
Figure 4 Schematic diagram of the VCSEL drive circuit.
4.2.2 BPM-12 Adjustments
It is essential in the SCT pipelined system that then order to ensure that the correct
data for the event corresponding to a given L1 trigger is read out from the ABCD
pipeline. This means that level 1 (L1) trigger signal corresponds to the correct time
slot, the L1 trigger must arrive at the ABCDs at the right time. This is achieved the
control data for each channel could b e individually adjusted by setting the coarse
delay register, which delays ed the L1 signal by an integral number of clock cycles.
This iswas performed by sending the data through flip flops clocked by the 40 MHz
BC clock. It is also necessary to adjust the delay of the 40 MHz BC clock so that the
phase is correct with respect to the signals generated by particles crossing the detector
module. A delay canould be set for each channel by means of a 7 bit fine delay
register which changesd the delay in the range 0 to 35 ns (i.e. it coveresd the entire 25
ns period). This delay iswas generated by passing the signal through a variable number
of pairs of inverters. In order to obtain an equal mark to space ratio (MSR) for the
optical output (this is necessary for the on-detector system to create a low jitter BC
clock as discussed in Section 5.3.4) a mark to space ratio adjustment was
implemented which allowed for the adjustment of the mark to space ratio of the BPM
encoded data. The schematic diagram of the mark to space ratio adjustment is shown
in Figure 5 below. The mark to space ratio of the signal is first reduced by connecting
it to one input of a NAND gate where the other input is a delayed version of the same
signal. This signal is then fed to one input of an NOR gate where the other input is a
delayed version of the same signal. The delay for the second signal is adjustable by
means of a register which controls how many pairs of inverters the signal is passed
through. The effect of the NOR gate is to stretch the width of the pulse so that the
MSR mark to space ratio (MS) is controlled by the length of this adjustable delay.
8
Figure 5 Schematic diagram of the mark to space ratio adjustment circuit in
BPM-12.
4.3 RX and TX Plug-in PCBs
The RX PCBs contained the 12 channel p-i-n array with the precision mounted MT
guide pins and the DRX-12 ASIC. The PCB also contained a multi-DACi for setting
the thresholds to each channel. The RX PCB had a 40 pin connector to allow it to be
connected to the Back of Crate (BOC) card. Similarly the TX PCBs contained the 12
channel VCSEL array and the BPM-12 ASIC. The TX PCB also contained a multi-
DACi for setting the voltages which control the VCSEL drive current.
5. Array Performance
5.1 p-i-n Measurements
5.1.1 Analogue measurements
The rise and fall times of the bare p-i-n arrays was measured as a function of p-i-n
bias voltage on a sample of arrays and the results for one channel of one array are
shown in Figure 6 below.
i
DAC LTC1665.
9
PIN Rise and Fall Times
8
7
6
5
Time (ns)
Rise Time
4
Fall Time
3
2
1
0
0 2 4 6 8 10 12
PIN Bias (V)
Formatted: Font: Italic
Figure 6 p-i-n 20%-80% rise and fall times as a function of p-i-n bias.
Formatted: Font: Italic
This shows as expected that a fast response could be obtained for a p-i-n bias voltage Formatted: Font: Italic
of 5V. The p-i-n responsivity was measured at a p-i-n bias of 5V and the resulting Formatted: Font: Italic
distribution of responsivities is shown in Figure 7 below. The distribution of the
responsivities measured on the bare die array is very uniform, so the measured spread
is probably due to the MT optical connector.
PIN Responsivity
30
25
20
Frequency
15
10
5
0
0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 0.62 0.64 0.66 More
Responsivity (A/W)
Formatted: Font: Italic
Figure 7 Distribution of p-i-n responsivities at a p-i-n bias voltage of 5V.
Formatted: Font: Italic
10
5.1.2 Digital p-i-n Measurements
In order to measure the performance of the combined p-i-n diode/DRX-12 system a Formatted: Font: Italic
series of Bit Error Rate (BER) measurements were performed using a prototype SCT
opto-harness as the 12 data sources. The opto-harness consists ed of opto-flex cables
connected to 6 low mass aluminium power tapes. An opto-package containing two
VCSELs and one p-i-n diode[10,11] as well as the DORIC4A and VDC ASICs
arewere mounted on the opto-flex cable[12]. Scans of BER versus RX DAC (this sets
the threshold) value were made at different p-i-n bias voltages. Scans of the number of
errors as a function of the timing were also done. The results of the BER scans versus
RX DAC value for p-i-n bias voltages in the range 0 to 4V are shown in Figure 8 to
Figure 10 below. The results of scans with higher p-i-n bias voltages looked very
similar to the results obtained at 4V.
BER Scan PIN Bias 0V
6.00E-01
5.00E-01
Series1
Series2
4.00E-01 Series3
Series4
Series5
BER
Series6
3.00E-01 Series7
Series8
Series9
2.00E-01 Series10
Series11
Series12
1.00E-01
0.00E+00
0 50 100 150 200 250 300
RX DAC
Figure 8 BER versus RX DAC value for p-i-n Bbias of 0V.
11
BER Scan PIN Bias 2V
6.00E-01
5.00E-01
Series1
4.00E-01
Series2
Series3
Series4
BER
3.00E-01 Series5
Series6
Series7
Series8
2.00E-01
Series9
1.00E-01
0.00E+00
0 50 100 150 200 250 300
RX DAC
Figure 9 BER versus RX DAC value for p-i-n bBias of 2V.
BER Scan PIN Bias 4V
8.00E-01
7.00E-01
6.00E-01
Series1
5.00E-01 Series2
Series3
Series4
BER
4.00E-01 Series5
Series6
Series7
3.00E-01
Series8
Series9
2.00E-01
1.00E-01
0.00E+00
0 50 100 150 200 250 300
RX DAC
Figure 10 BER versus RX DAC value for p-i-n bBias of 4V.
Not surprisingly, there is a clear improvement in going from a p-i-n bias of 0V to 2V.
There is a slight improvement in going from 2V to 4V but after that there is no clear
evidence of any further improvement. In order to summarise the data in one figure the
results of the BER scans versus RX DAC value for one channel are shown in Figure
11 below.
12
BER Scans vs PIN Bias
0.6
0.5
0V
0.4 2V
4V
BER
6V
0.3
8V
10V
0.2 12V
14V
0.1
0.0
0.00 50.00 100.00 150.00 200.00 250.00
RX DAC
Figure 11 BER scans versus RX DAC value for channel 0, at different p-i-n bias
voltages.
From the timing scans, the width of the region with no bit errors was determined and
this width is plotted as a function of p-i-n bias voltage in Figure 12 below.
Width of 0 Errors vs PIN Bias Voltage
25
20
Width (ns)
15
DAC=255
DAC=104
10
5
0
0 2 4 6 8 10 12 14 16
PIN Bias (V)
Figure 12 Width of the region of 0 bit errors as a function of p-i-n bias voltage
for two different settings of the RX DAC value.
5.2 2D Scans
In order to further understand the system performance the BER scans were made as a
function of RX DAC value and the relative delay between the reconstructed and
reference data. These 2D scans can then be used to create the digital equivalent of an
“eye” diagram. The results of a 2D scan of BER versus RX DAC value and timing
setting is shown in Figure 13 below.
13
PIN Bias 2V
0
250
1.000
4500
6750
200 9000
1.125E4
1.35E4
RX DAC Value
150 1.575E4
1.8E4
100
50
5 10 15 20 25 30
Timing (ns)
Figure 13 Number of bit errors versus RX DAC value and timing setting for
array C000 channel 0 at a p-i-n bias of 2V.
This shows that the width of the timing scan with 0 errors, is greatly reduced at low
DAC value, compared to higher DAC values. This corresponds to the slow tail in the
analogue signal at low p-i-n bias voltage. The equivalent plot for a p-i-n bias of 4V is
shown in Figure 14 below and shows a much better performance. There was no clear
improvement in the plot as the p-i-n bias voltage was increased above 4V.
PIN Bias 4V
0
250
1.000
4500
6750
200 9000
1.125E4
1.35E4
RX DAC Value
150 1.575E4
1.8E4
100
50
5 10 15 20 25 30
Timing (ns)
Figure 14 Number of bit errors versus RX DAC value and timing setting for
array C000 channel 0 at a p-i-n bias of 4V.
In order to compare the performance more quantitatively, the range of the timing scan
in which there were no bit errors was calculated as a function of RX DAC value. The
14
results for one channel are shown for different p-i-n bias voltages in Figure 15 below.
to Figure 18 below.
C004 channel 0
25
20
Range of 0 Errors (ns)
15
2V
4V
6V
10
5
0
0 50 100 150 200 250 300
RX DAC
C004 channel 0 2V
25
20
Range of 0 Errors (ns)
15
10
5
0
0 50 100 150 200 250 300
RX DAC
Figure 15 Range of timing scan with no bit errors as a function of RX DAC value
for array C000, channel 0 at different a p-i-n bias voltages (see legend) of 2V.
15
C004 channel 0 4V
25
20
Range of 0 Errors (ns)
15
10
5
0
0 50 100 150 200 250 300
RX DAC
Figure 16 Range of timing scan with no bit errors as a function of RX DAC value
for array C000, channel 0 at a p-i-nbias voltage of 4V. Formatted: Font: Italic
C004 channel 0 6V
25
20
Range of 0 Errors (ns)
15
10
5
0
0 50 100 150 200 250 300
RX DAC
Figure 17 Range of timing scan with no bit errors as a function of RX DAC value
for array C000, channel 0 at a p-i-nbias voltage of 6V. Formatted: Font: Italic
16
C004 channel 0 8V
25
20
Range of 0 Errors (ns)
15
10
5
0
0 50 100 150 200 250 300
RX DAC
Figure 18 Range of timing scan with no bit errors as a function of RX DAC value
for array C000, channel 0 at a p-i-nbias voltage of 8V. Formatted: Font: Italic
These results show a clear improvement in performance when increasing the p-i-n Formatted: Font: Italic
bias voltage from 2V to 4V but there is no evidence for any further improvement at
higher p-i-n bias voltages. In order to summarise the performance for a given array at Formatted: Font: Italic
a particular p-i-n bias voltage, the number of bins in the 2D scan with no bit errors Formatted: Font: Italic
was counted. The results are shown for the sample of 10 p-i-n arrays used in Figure Formatted: Font: Italic
16Figure 19 below.
Number Zero Error Bins
4500
4000
C001-c0
3500 C001-c6
C002-c0
3000
Number bins
C003-c0
2500 C004-c0
C005-c0
2000 C006-c0
C007-c0
1500
C008-c0
1000 B000-c0
B001-c0
500
0
0 2 4 6 8 10 12 14 16
PIN Bias (V)
Formatted: Left
Figure 16 Number of bins in the 2D scan of BER versus RX DAC and timing
setting with no bit errors as a function of p-i-n bias voltage, for selected channels
of the 10 p-i-n arrays used.
17
Figure 19 Number of bins in the 2D scan of BER versus RX DAC and timing
Formatted: Font: Italic
setting with no bit errors as a function of p-i-nbias voltage, for the 10 p-i-narrays
Formatted: Font: Italic
used.
For all the p-i-n arrays the performance improves with p-i-n bias voltage but no Formatted: Font: Italic
further improvement is observed for a p-i-n bias above 6V. Formatted: Font: Italic
Formatted: Font: Italic
5.3 VCSEL measurements
5.3.1 Analogue Measurements
The distribution of the amplitudes with the lasers coupled to 50 m core SIMM fibre Formatted: Font: Symbol
and with the drive currents set at 10 mA, is shown in Figure 17Figure 20 below.
VCSEL Power
8
7
6
Frequency
5
4
3
2
1
0
e
0
0
00
00
00
00
00
00
00
00
00
00
70
90
or
11
13
15
17
19
21
23
25
27
29
M
Coupled Power (W)
Figure 17 Distribution of coupled optical power for all channels of a sample of 7
VCSEL arrays with a drive current of 10 mA.
Figure 20 Distribution of coupled optical power for all channels of a sample of 7
VCSEL arrays with a drive current of 10 mA.
There is a very broad distribution of optical power but all channels gave an optical
power above 700 W at 10 mA.
The measurement of the rise and fall times, were all done using a fast optical probei
(with an optical attenuator to ensure that the signal was well below the saturation level
for the probe). The measurements were not corrected for the bandwidth of the probe
(700 MHz) nor of the oscilloscope (300 MHz). The distributions of the rise and fall
i
Tektronix O/E converter P6701B.
18
times are shown in Figure 18 and Figure 19 Figure 21 and Figure 22 below. The
distributions show that the rise and fall times are peaked around 1 ns, and are well
below 2 ns.
Rise Time
30
25
Frequency
20
15
10
5
0
0
0
0
0
0
00
00
00
00
00
00
20
40
60
80
10
12
14
16
18
Time (ps) 20
Formatted: Left
Figure 18 Distribution of 20%-80% rise times for all VCSEL channels driven at
10 mA.
Figure 21 Distribution of 20%-80% rise times for all VCSEL channels driven at
10 mA.
19
Fall Time
45
40
35
Frequency
30
25
20
15
10
5
0
0
0
0
0
00
00
00
00
00
00
0
20
40
60
80
10
12
14
16
18
20
Time (ps)
Figure 19 Distribution of 20%-80% fall times for all VCSEL channels driven at
10 mA.
Formatted: Left
Figure 22 Distribution of 20%-80% fall times for all VCSEL channels driven at
10 mA.
Some channels had an apparently slower rise time but the significance of this is not so
obvious as the signals always had a fast component and then a slow tail as illustrated
in some of the oscilloscope pictures in Figure 20Figure 23 (rise and fall times below
1ns) and Figure 21Figure 24 (rise time above 1ns) below.
20
TD007 Fibre 4
7.00E+02
6.00E+02
5.00E+02
Time (ns)
4.00E+02
Probe
3.00E+02
2.00E+02
1.00E+02
0.00E+00
0 20 40 60 80 100 120
Output (a.u.)
Figure 20 Oscilloscope picture of optical signal for fibre 4 of TD007 (rise time =
0.64 ns, fall time = 0.86 ns).
Formatted: Left
TD001 Fibre 4
900
800
700
600
Output (a.u.)
500
400
300
200
100
0
0 10 20 30 40 50 60 70 80 90 100
Time (ns)
Figure 21 Oscilloscope picture of optical signal for fibre 4 of TD001 (rise time =
1.60 ns, fall time= 0.86 ns).
Figure 23 Oscilloscope picture of optical signal for fibre 4 of TD007 (rise time =
0.64 ns, fall time = 0.86 ns).
21
TD001 Fibre 4
900
800
700
600
Output (a.u.)
500
400
300
200
100
0
0 10 20 30 40 50 60 70 80 90 100
Time (ns)
Figure 24 Oscilloscope picture of optical signal for fibre 4 of TD001 (rise time =
1.60 ns, fall time= 0.86 ns).
From the Oscilloscope pictures it can be seen that all channels have a very fast
component to the rise and fall time and the apparently slower rise times of some
channels is due to the shape of the top of the waveform. Since the DORIC4A is ac
coupled with a threshold close to 0 we might well expect that the digital performance
will still be very good, even for the apparently slower channels.
5.3.2 BER Scans
The central 6 channels of all 9 arrays were used to perform BER scans using the
samea prototype re-series opto-harness as used for the BER scans for the RX PCBs
(see section 5.1.2). All channels worked very well on all arrays. The width of the
region in the timing scan which gave no errors was typically 20 or 21 ns and was
never less than 19 ns. The results of the BER scans for the TTC links for one of the
arrays are shown in Figure 25 Figure 22 and the other 8 arrays showed very similar
performance.
22
BER Scan TD000
0.6
0.5
0.4
VCSEL 4
VCSEL 5
BER
VCSEL 6
0.3
VCSEL 7
VCSEL 8
VCSEL9
0.2
0.1
0.0
0 50 100 150 200 250 300
TX DAC
Formatted: Left
Figure 22 TTC BER scan versus TX DAC value for TX TD000.
Figure 25 TTC BER scan versus TX DAC value for TX TD000.
From these BER scans it can be seen that all the 6 channels tested work very well. The
turn on of the system at around a TX DAC setting of 100 corresponds to a VCSEL
drive current of about 5 mA. This is above laser threshold for these arrays but
corresponds to the minimum value for which the BPM-12 driver circuit gives a
reasonable output signal. The channels which have non- zero BER at high TX DAC
values, correspond to channels with a coupled power above 2 mW. The power
reaching the p-i-n diode during ATLAS operation will be lower by about 2 dB Formatted: Font: Italic
because of the attenuation in the fibre and the extra MT connector. Therefore the
errors occurring at very high DAC value would not be seen in free region during
ATLAS operation operation. will be wider than seen in these scans.
5.3.3 Mark to Space Ratio
The mark to space ratio of the VCSEL optical signal needs to be close to 50:50 in
order to maintain a low clock jitter. With biphase mark encoded data, the DORIC4A
creates clock pulses from both edges of the 20 MHz clock. Therefore if the mark to
space ratio is not equal to 50:50 there will be two “families” of recovered 40 MHz
clock, one with a period shorter than 25 ns period and one with a longer period, which
effectively creates jitter in the clock. This is illustrated schematically in Figure 23
Figure 26 where the effect of an extremely low mark to space ratio creates a short
clock period followed by a long clock period.
23
Figure 23 The effect of unequal mark to space ratio of the TTC signal on the
recovered 40 MHz BC clock. (A) shows a BPM signal with a low mark to space
ratio and (B) shows the resultant clock that would be recovered by DORIC4A.
Figure 26 The effect of unequal mark to space ratio of the TTC signal on the
recovered 40 MHz BC clock. (A) shows a BPM signal with a low mark to space
ratio and (B) shows the resultant clock that would be recovered by DORIC4A.
The optimal register mark to space ratio register value to get a 50:50 mark to space
ratio for the electrical output of the BPM-12 was measured for every channel for a
sample of BPM-12s as a function of fine delay. Increasing the fine delay increases the
number of pairs of inverter gates the BPM signal passes through and since each
inverter can slightly distort the signal this can affect the mark to space ratio. The
results for one channel are shown in Figure 24Figure 27 below.
24
Figure 24 Optimal value of the BPM-12 mark to space register versus fine delay.
Figure 27 Optimal value of the BPM-12 mark to space register versus fine delay.
Formatted: Left
A linear fit was made to determine the intercept (ie the optimal value of the mark
to space register at a fine delay of 0) and the slope (ie the change in the optimal
value of the mark to space register with fine delay). The distributions of these
intercepts and slopes for all channels for a batch of ~ 100 BPM-12s is shown in
Figure 25 Distribution of intercepts of the linear fit of optimal mark to space
register versus fine delay.
Figure 28 and Figure 26Figure 29 below.
25
Optimal MSR Setting
350
300
Frequency
250
200
150
100
50
0
e
12
14
.4
.8
.2
.6
.4
.8
or
12
12
13
13
14
14
M
Fitted MSR Value
Formatted: Left
Figure 25 Distribution of intercepts of the linear fit of optimal mark to space
register versus fine delay.
Figure 28 Distribution of intercepts of the linear fit of optimal mark to space
register versus fine delay.
26
400
350
300
250
Frequency
200
150
100
50
0
07
08
e
2
4
6
8
2
4
6
07
07
07
07
08
08
08
or
0.
0.
M
0.
0.
0.
0.
0.
0.
0.
Slope MS fit
Figure 2629 Distribution of slopes of the linear fit of optimal mark to space
register versus fine delay.
The mean and standard deviations of the distributions of fitted intercepts and slopes
are given in Table 3 below.
Table 3 Summary of fits of optimal MSR setting versus fine delay scans.
Fitted Parameter Mean Standard Deviation
Intercept 13.292 0.294
Slope 0.0761 0.0030
The mark to space ratio of the electrical output will in general be distorted by the
VCSELs, therefore it is also necessary to study the mark to space ratio of the optical
signal out of the TX PCBs. The positive duty cycles of the optical output of the central
6 channels for one of the TXs were measured as a function of the mark to space
register (MSR) setting and the results shown in Figure 27Figure 30 below. All
channels show similar behaviour and the optimal value of the MSR is 17. With the
27
MSR set to a value of 17, the positive duty cycle was measured on all channels from 7
TXs and the resulting histogram is shown in Figure 28Figure 31 below.
Mark to Space Ratio
56
54
52
Positive duty cycle %
50 Fibre 4
Fibre 5
Fibre 6
48 Fibre 7
Fibre 8
46 Fibre 9
44
42
40
0 5 10 15 20 25 30
M:S register
Figure 2730 Adjustment of duty cycle with the mark to space register setting.
35
30
25
Frequency
20
15
10
5
0
49 49.2 49.4 49.6 49.8 50 50.2 50.4 50.6 More
Positive Duty Cycle (%)
28
Figure 2831 Distribution of positive duty cycle for the output of all channels
from 7 TXs with the MSR set to 17.
The distribution of positive duty cycles is very well peaked close to 50% showing that
there is very little variation within TXs or between TXs. However it should be noted
that the optimal MSR (17) for obtaining an equal mark to space ratio for the optical
signal is different for that for obtaining the optimal mark to space ratio for the
electrical signal (13).
5.3.4 BC Clock Jitter
The final check that the MSR is optimal is to look at the jitter of the 40 MHz BC
clock. This was studied for the 6 central channels of a TX by sending the optical
signals to a pre-series opto-harness and looking at the 40 MHz clocks recovered by the
PIN/DORIC4A. Pseudo-rRandom data wereas sent to each channel so that the phase
of the BPM signal was changing. The clock jitter was estimated as a function of the
MSR setting and shown in Figure 29Figure 32 below.
Clock Jitter vs MSR
5
4.5
4
3.5
Clock Jitter (ns)
Fibre 4
3
Fibre 5
Fibre 6
2.5 Fibre 7
Fibre 8
2 Fibre 9
1.5
1
0.5
0
0 5 10 15 20 25 30 35
MSR
29
Clock Jitter vs MSR
5
4.5
4
3.5
Clock Jitter (ns)
Fibre 4
3
Fibre 5
Fibre 6
2.5 Fibre 7
Fibre 9
2 Series6
1.5
1
0.5
0
0 5 10 15 20 25 30 35
MSR
Figure 2932 Jitter (full width) in the recovered 40 MHz clock as a function of
MSR setting for the central 6 channels of TD007. The fine delay registers were
set to a value of 0.
The optimal value of the MSR is 14 for 5 channels but 15 for one. This optimal value
differs slightly from the value of 17 which gave the closest to 50% duty cycle for the
optical signal. This could be due to the difference in the response of the DORIC4A/p- Formatted: Font: Italic
i-n diode compared to the Tektronix optical probe or to the details of the algorithm
used in the oscilloscope to determine duty cycle. In any case it is the jitter
measurement of the recovered clock which defines the final system performance. The
jitter was measured for the 6 central channels of another 5 TXs. The optimal value
varied from TX to TX and within a TX in the range 13 to 16. If one were to chose a
single value for the MSR it would be 15. The distribution of jitter for an MSR setting
of 15 is shown in Figure 30Figure 33 below. If one uses the optimal MSR value for
each channel then the jitter would be significantly improved as shown in Figure
34
30
Optimised Jitter
14
12
10
Frequency
8
6
4
2
0
0.3 0.4 0.5 0.6 0.7 0.8 0.9 More
Full Width Jitter (ns)
Figure 34 below. The improvement in the jitter in using the optimised MSR setting for
each channel compared to the value of 15 for all channels is summarised in Table 4
below.
Table 4 Summary of jitter measurements for the recovered 40 MHz clock.
Full width jitter (ns) MSR=15 Optimised MSR
Mean value 0.614 0.431 Formatted: Font: (Default) Times New
Roman, 12 pt
Standard deviation 0.203 0.124
Maximum value 1.08 0.68
From the results shown in Table 4 using an optimal MSR setting does give a
significant improvement in the jitter. However even using a common value of the
MSR settings for all channels gives reasonably good performance as the RMS is still
typically well below 0.5 ns.
31
Jitter MSR=15
8
7
6
Frequency
5
4
3
2
1
0
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 More
Full width Jitter (ns)
Figure 3033 Distribution of the full width of the jitter of the recovered clock for a
MSR setting of 15.
32
Optimised Jitter
14
12
10
Frequency
8
6
4
2
0
0.3 0.4 0.5 0.6 0.7 0.8 0.9 More
Full Width Jitter (ns)
Figure 3134 Distribution of the full width of the jitter of the recovered clock for
an optimised MSR setting for each channel.
In order to understand if the variation between TX channels was affected by which p- Formatted: Font: Italic
i-n diode/DORIC4A was used, the results for TD007 were repeated with the MT
connector reversed. The results were significantly different which suggests that even if
a full calibration was done for each TX channel, a final calibration would have to be
done for each channel in ATLAS. This in--situ calibration could be performed using
the clock/2 mode in which the ABCD[13, 14] chips return a 20 MHz clock to the data
links. A scan of the width of the on period of this signal should show a width of 25ns
for the optimal MSR setting. The measurement would then be repeated after a single
“1” had been sent in order to flip the phase of the biphase mark signal. The difference
between the results of the width of the scans between the two phases would then be a
measure of the unequal mark to space ratio of the VCSEL signal. Therefore by
adjusting the MSR until this difference was minimised the optimal MSR setting could
be determined.
Finally the value of the fine delay was changed from 0 to 85 (corresponding to the
maximum useful fine delay of 25 ns) and the clock jitter was measured as a function
of the MSR setting and the results shown in Figure 32Figure 35 below. This shows
that the optimal MSR setting for a fine delay setting of 85 is changed by 6 to 7 counts
compared to that for a fine delay setting of 0 (see Figure 29Figure 32). This is in good
agreement with the measured slopes (see Figure 26Figure 29) which would predict a
change of 85*0.076=6.5 counts.
33
Jitter vs MSR for Fine Delay=85
1.4
1.2
1
Jitter (ns)
Fibre 4
0.8 Fibre 5
Fibre 6
Fibre 7
0.6 Fibre 8
Fibre 9
0.4
0.2
0
18 19 20 21 22 23 24
MSR
Figure 3235 Jitter (full width) in the recovered 40 MHz clock as a function of
MSR setting for the central 6 channels of TD007. The fine delay register was set
to a value of 85.
6. Conclusions
The design of the off-detector opto-electronics for the SCT and Pixel optical links has
been presented. Detailed analogue and digital studies have been performed of the data
and TTC links. The data links work well for a p-i-n bias voltage of greater than about Formatted: Font: Italic
2V but require a p-i-n bias of greater than about 6V to produce the optimal Formatted: Font: Italic
performance. The TTC links work well over a large range of VCSEL drive currents. A
very low jitter can be obtained on the recovered 40 MHz BC clock, provided the
BPM-12 mark to space adjustment system is used.
Formatted: Heading 1
7. Acknowledgements Formatted: Bullets and Numbering
This work was supported by the National Science Council of Taiwan, ROC. Financial Formatted: Normal, Justified
support from the UK Particle Physics and Astronomy Research Council is gratefully
acknowledged.
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35
