Design and Implementation of FPGA Based PID Controller

Document Sample
Design and Implementation of FPGA Based PID Controller Powered By Docstoc
					Design and Implementation of FPGA Based PID Controller



Abstract — This paper explains a               Digital Signal Processors (DSPs), and
method for the design of tunable PID           general purpose computers are tools for
controller based on Field Programmable         software implementation. The second
Gate Array (FPGA) device. It is more           method is based on hardware. Here we
compact, power efficient and provides          are using Field Programmable Gate
high speed capabilities as compared to         Arrays (FPGA).FPGAs are configurable
software based PID controllers. In one         ICs and used to implement logic
FPGA we can implement many PID                 functions. They ensure ease of design,
controllers thus it is cost effective. Here    lower development costs, more product
in this paper we tried to cover up basics      revenue, and the opportunity to speed
of    PID    controller     as    well   as    products to market. At the same time
implementation of PID controller on            they are superior to softwarebased
FPGA.                                          controllers as they are more compact,
                                               power-efficient, while adding high speed
I. INTRODUCTION                                capabilities [1]. FPGAs are high-density
There are basically two methods for            Programmable Logic Devices (PLDs)
implementing control system based on           with, usually; more than a million gates
digital technology. The first method is        and 100s of I/O ports. Most of the
using software which implies a memory-         manufacturers of the FPGAs provide
processor interaction. The memory holds        software to program these devices.
the   application   program      while   the   Hardware Description Languages such
processor fetches, decodes, and executes       as VHDL and Verilog,
the program instructions. Programmable         which were initially used to describe and
Logic         Controllers          (PLCs),     simulate digital logic circuitry, are
microcontrollers, microprocessors,             currently being used to implement
                                               complex algorithmic logic and then
                                               loaded into the FPGA.
                                               II. PID CONTROLLER
                                               One of the most powerful but complex
                                               controller mode operations combines the
proportional, integral, and derivative          1e(k -1) + 2e(k - 2)….........(2)
modes with a control loop feedback          Where the coefficients 0, 1, and 2
mechanism widely used in industrial         are evaluated by the expressions:
control system. A PID controller corrects
the error between a measured process
variable and a desired set point. It
                                            The Kc, Ti and Td, are PID parameters
calculates the difference between the two
                                            for tuning, and Ts is the sampling period
and then outputs a corrective action
                                            in seconds. There are several methods
thorough the feedback.
                                            for evaluating the PID parameters,
                                            generally called PID tuning methods [2].
The analytical equation is:
                                            When       controlling      time-invariant
P = Kpep + KpKI _epdt + KpKD(dep/dt)
                                            processes, the PID parameters can be
+PI(0) (1)
                                            constants and evaluated off-line, so, the
Where,
                                            PID architecture may use fixed values
Kp = proportional gain
                                            for the 0, 1, and 2       coefficients.
KD = derivative gain
                                            Otherwise, for time-variant processes
ep = error in % of full scale range
                                            there is   a need to       update those
KI = integral gain
                                            parameters;   in   this   case   the   PID
PI(0) = value of integral term at t=0
                                            architecture has Kc, Ti and Td as
There are various tuning algorithm
                                            parameters that can be automatically
available in the literature.
                                            updated during runtime by auto-tuning
                                            algorithms. A complete implementation
III. PID CONTROLLER TUNING
                                            of the PID controller with auto-tuning
A typical closed loop system using a PID
                                            requires a component responsible for the
controller is shown in Fig.2 (a). The
                                            auto tuning algorithm, whose complexity
control system usually requires units to
                                            largely depends on the auto-tuning
interface it to the environment. For
                                            algorithm used. The auto-tuning feature
instance, a converter
                                            is required in most control systems for
to PWM (Pulse-Width Modulation) may
                                            mobile robotics due to the changes that
be needed when controlling DC motors.
                                            may occur in the environment and/or
The digital PID controller can be
                                            system. Those modifications usually
described by the following difference
                                            need the retuning of parameters to still
equation:
                                            have a stable control system with
u(k) = u(k -1) + 0e(k) +
                                            acceptable performance criteria's. In
general, it could be useful that a           are incorporated as              fixed assigned
controller                implementation     values. The algorithm proposed will tune
accommodates both type of numerical          to various changes in parameters and
representation: fixed- and floating-point.   then automatically control the set point.
In FPGA implementations architecture         The implementation part demonstrated in
might   be   preferred.   However,    the    the paper is for a given set of values of
evaluation of the number of bits for         Kc, Ti and Td.. The auto tuning
integer and fractional parts of each         algorithm may be developed as per
operand in the system is a very time         actual   real   time       example.     System
consuming procedure. In this paper we        Generator implements the design by
propose a methodology for design and         considering     the        correct    hardware
implementation of PID controllers in         platform and also takes care of the
FPGA with                                    synchronization            and       interfacing
exploitation of the number of bits for       problems. [3]
fixed-point representations [7].             A separate test bench application for
                                             hardware (FPGA) verification is also not
                                             required. The co-simulation block can be
                                             used with the same Simulink test bench
                                             apparatuses
                                             that were used to test the original System
                                             Generator model. Along - disadvantages
                                             also, that are associated with the
                                             presented             co             simulation
                                             methodology/tools using automatic bit
                                             stream generation. With every release of
                                             System Generator, the top level output
                                             files change.




IV. FPGA IMPLEMENTATION
The various implementation schemes
available in the literature are mainly
focused on hardware efficient PID
algorithms. The values of Kc, Ti and Td
The algorithm shown in Fig 4 will be the             allow representing those values as
basis     of     a       SoPC     model        for   223.1484, -441.4688 and 218.3281.
implementation       of    Digital       adaptive
controllers.
                                                     18 bits are used for integer part and 7
                                                     bits are used for fractional part for the
                                                     uniform fixed point representation all
                                                     operands (0, 1, and 2 included) and
                                                     operators. This implementation achieves
                                                     none errors when compared to the
                                                     floating-point implementation using the
                                                     same values for 0, 1, and 2 for the
                                                     reference    signal    presented.    When
                                                     compared to the original floating-point
                                                     values,     although       stable,       the
                                                     representation has a mean relative error
                                                     of 7.9%. Note that reduction of bit-
                                                     widths more than 20.9% makes the
                                                     system unstable. Based on this, we can
                                                     conclude that in this kind of digital
V. DESIGN EXAMPLE
                                                     systems error metrics (relative, absolute,
Here we have implemented multiplier
                                                     etc.) may play a secondary role since
based PID controller as suggested by
                                                     they may not have the
Joao Lima, Ricardo Menott et all [4] by
using Xilinx SysGen tool box. As seen
in the Fig.5
                                                     importance as in digital filter design.
(b).the floating-point values of the 0,             Here, we are firstly concerned with
1, and 2 coefficients are: 223.1538,-              stability and then with precision [4].
441.4616and 218.3344, respectively &
transfer function is G(s) = 1/(s+1)3. In
the      examples         with         fixed-point
representations we use for 0, 1, and
2      {9,    7},{10,    6}     and     {9,   6},
respectively [4]. Those representations
                                             V|| HARDWARE SETUP

                                                          Real time physical setup of the
                                             FPGA kit, ADC, DAC circuits, V/I
                                             converter with FPGA kit and host
                                             computer and physical setup of the three
                                             tank system which is configured for
                                             single tank process are shown in Fig7.1
                                             to Fig 7.2

VI. RESULTS
Here in fig.6 are included the simulation
results of FPGA based tunable PID
controller with multiplier. As depicted in
results it provides better settling time.




                                             Figure 7.1: Spartan II FPGA kit
                                              In a future we plan to implement fuzzy
                                              logic controllers on FPGAs.



                                              REFERENCES



                                                     1. Wei Zhao, Byung Hwa Kim,
                                                        Amy C. Larson, and Richard
Figure 7.2: FPGA kit with interfacing
                                                        M.        Voyles.,          ‘FPGA
circuits and host computer
                                                        Implementation        of     Closed
                                                        loop     control     System        for
                                                        Small     Scale      Robot’,        In
                                                        Proceedings.,                     12th
                                                        International conference on
                                                        advanced      robotics-ICAR05,
                                                        2005, pp.70-77.

                                                     2. Daijin          Kim.              “An
                                                        implementation         of    Fuzzy
                                                        Logic     Controller        on     the
Figure 7.3: Synthesized circuit of Real                 Reconfigurable               FPGA
to Floating point converter                             system”, IEEE transactions
                                                        on     Industrial    Electronics,
VII!. CONCLUSION                                        Vol.47, No.3, 2000.

Today’s high-speed and high-density                  3. M.K.Gupta, “Implementation
FPGAs          provide    viable     design             of Digital PID Controller on a
alternatives        to     ASIC        and              single    FPGA       chip        using
microprocessor-based implementations.                   VHDL”, IEEE transactions
Several        building    modules      for             on Industrial Electronics,
implementing PID controllers on these                4. Y.F.Chang, M.Moallm and
FPGAs are constructed in this work.                     W.Way,        “Efficient          PID
Implementing PID controllers on                         Controller     Using        FPGA”,
FPGAs features speed, accuracy, power,                  IEEE         transactions          on
compactness, and cost improvement over                  Industrial           Electronics,
other digital implementation techniques.                Vol.35, pp. 119-125.
5. L.Samet,           N.Masmoudi,       10. Stephen Brown, ‘Digital logic
   M.W.Kharrat and L.Kamoun,               design’, Tata Mechgraw Hill
   “A Digital PID Controller for           publications, India, 2002.
   Real time and Multi Loop
   Control:     a      comparative      11. Design     tips   for    HDL

   study”, in proceedings of               implementation of Arithmetic

   1998       IEEE    international        functions      from      Xilinx

   Conference on Electronics               tutorials www.xilinx.com

   Circuits and Systems,Vol.1,
   1998, pp. 291-296.
6. Akihiro      Ozeki,        Hideji
   Fujikawa, “A Design Method
   of Self tuning controller for
   unknown time delay system”,
   IEEE        transactions       on
   Industrial Electronics, 1992,
   pp.1218-1223.
7. Paul    Leisher,    Christopher
   Meyers.Dr.T.Stewart           and
   Dr.G.Dempsey,              “FPGA
   Implementation of a PID
   controller with DC Motor
   Application”,            Bradley
   University, a project report,
   2002.
8. IEEE-754, a binary floating
   point arithmetic standard and
   IEEE 1076, a standard of
   VHDL                        from
   www.ieeexplore.ieee.org,
   2002.
9. J.Bhasker, ‘A VHDL primer’,
   Pearson     Education,      India,
   2005.

				
DOCUMENT INFO
Shared By:
Stats:
views:152
posted:9/24/2012
language:English
pages:7
Description: Seminar papers