CAD PRELIM SYLLABUS Revised October 2004 1. Circuit Simulation: A. Sangiovanni-Vincentelli, "Circuit Simulation" Design systems for VLSI synthesis, Martinus Nijhoff Publishers, 1987 2. .Layout: J. Kleinhaus, G. Sigl, F. Johannes, K. J. Antreich, “GORDIAN: VLSI Placement by Quadratic Programming in Slicing Optimization”. IEEE Transactions on Computer-Aided Design, March 1991. 3 Compaction: Thomas Lengauer, "Combinatorial Algorithms for Integrated Circuit Layout", Chapter 10, "Compaction", pages 579-649, Wiley and Teubner, 1990 4. Partitioning: B.W. Kernighan, S. Lin, "An Efficient Heuristic Procedure for Partitioning Graphs", Bell Syst. tech Journal, vol 49, 1970 C.M. Fiduccia, R.M. Mattheyses, "A Linear Time Heuristic for Improving Network Partitions", Proc 19th DAC, 1982 5. Routing: R. L. Rivest and C. M. Fiduccia, “A „Greedy‟ Channel Router”. Proceedings of the 19th Design Automation Conference. June 1982. pg. 418-424. C. Y. Lee. "An Algorithm for Path Connections and its Applications". IRE Transactions on Electronic Computers, EC-10. September 1961. pg. 346-365. 6. Two Level Logic Synthesis: R. Rudell, A. Sangiovanni, "ESPRESSO-MV: Algorithms for Multi-Valued Logic Minimization", CICC, May 1985 7. Multilevel logic synthesis: K. Keutzer, ``DAGON: Technology Binding and Local Optimization by DAG Matching‟‟, Proceedings of the 24th Design Automation Conference. June 1987. pp. 341-347. R.K. Brayton, G. Hachtel, A. Sangiovanni-Vincentelli, "Multi-Level Logic Synthesis", Proc of IEEE vol. 78, Feb. 1990 8. BDD's: R. Bryant, "Symbolic-Boolean Manipulation with OBDD's", ACM Computing Surveys, Sept. 1992 9. Testing: Prabgajar Goel, "An implicit enumeration algorithm to generate tests for combinational logic circuits", IEEE Trans. on Computers, C-30(3):215-222, March 1981 T. Larrabee. “Test Pattern Generation Using Boolean Satisfiability.” IEEE Transactions on ComputerAided Design, vol. 11, no. 1, January 1992. 10. Timing Analysis: Devadas, Keutzer, Malik, - Computation of Floating Mode Delay: Theory and Algorithms, IEEE TCAD, Vol 12, No. 12, December 1993. pp. 1913-1923
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11. Sequential Optimizations: finite-state machine optimizations and retimng L. Lavagno, T. Villa, A. Sangiovanni-Vincentelli, " Advances in encoding for logic synthesis", Digital Logic Analysis and Design, 1994 N. Shenoy. “Retiming: Theory and Practice”. Integration: The VLSI Journal. Vol. 21, 1997. pg. 1-21. 12. Formal Design Verification: Clarke, Grumberg, Long - "Verification Tools for finite-State Concurrent Systems", in A Decade of Concurrency - Reflections and Perspectives, Springer LNCS, vol. 803, 1994. R. Alur. Timed Automata. Tutorial, 11th International Conference on Computer-Aided Verification, LNCS 1633, pp. 8-22, Springer-Verlag, 1999. R. Alur and T.A. Henzinger. Reactive modules. Formal Methods in System Design 15:7-48, 1999. 13. Formal models of computation E. A. Lee and A. Sangiovanni-Vincentelli, “A Framework for Comparing Models of Computation”. IEEE Transactions on CAD, vol. 17. no. 12, December 1998. NOTE: The following courses may not be used to fulfill the prelim breadth requirement if you take the CAD prelim: EE 219ABC, 244, 290A, 290H, 290LS, or CS 170, 172 or 250.
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