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Digital Logic

Objective: Main Objective is to know about properties of Logic gates, positive and
negative logic, basic gates and universal gates, HDL
1.    Define Binary operator.                                                         02
2.    List out different postulate used for algebric structure.                       02
3.    Explain the commutative & Associative law                                       02
4.    Discuss the following theorems with example                                     02
      i) x+x=x ii) x.x=0 iii) x+1=1 iv) x.0=0 v) x+xy=x vi) x(x+y) =x
5.    Explain Duality principle with an example.                                      02
6.    Explain complement of function with an example                                  02
7.    Define truth table                                                              02
8.    Why NAND & NOR gates are called universal gates                                 02
9.    Discuss canonical & standard forms of Boolean functions with an example         04
10.   Convert the following Boolean function to Sum of Minterms for F=A+B1C           04
11.   Convert the following Boolean function F=xy+x1z to product of Maxterm           04
12.   Bring out the difference between Canonical & Standard forms                     04
13.   What are logical gates,mention different types of Logic gates                   04
14.   Explain the operation of different Logic gates with neat diagram                04
15.   Demonstrate by means of Truth table the validity of following theorem of        06
      Boolean algebra
      i)Associative law ii) Demorgans law for Validity iii) Distributive law
16.   Simplify the following Boolean function to minimum no. of literals              06
      i) xy+xy1 ii) (x+y) (x+y1) iii) xyz+x1y+xyz1 iv) y(wz1+wz)+xy v) (A+B)1
      ((A1+B1)1
17.   Reduce the Boolean Expression to required number of literal                     06
      i) BC+AC1+AB+BCD ii) [(CD1) + A ]1+A+CD+AB iii) [(A+C+D) (A+C+D1)
      (A+C1+D) (A+B1)
18.   Obtain Truth table for function F=xy+xy1+y1z                                    06
19.   Convert the following to other canonical form
      i) F(x,y,z) =(1,3,7) ii) F(A,B,C,D)= (0,2,6,11,13,14) iii) F(x,y,z)           06
      =(0,1,2,3,4,6,12)
20.   Show that dual of Exclusive-OR is equal to its complement                        06
21.   Implement the following function F=(CD+E) (A+B’) using Nand gates only.         *05
22.   Simplify the Boolean function F using don’t care conditions d, in SOP and POS   *10
      form
      F=A’B’C + A’CD + A’BC
      D=A’BC’D + ACD + AB’D’
23.   Implement the following function with no more than 2 NOR gates. Assume both     *10
      normal and complement inputs are available
      F=A’B’C’+ AB’D + A’B’CD’
      D=ABC+AB’D’
24.   Simplify the following and then complement using logic gates                    *08
       AB+ A(B+C)+B(B+C)
       [ AB’ ( C+BD) + A’B’] C
25. Realize using NAND and NOR gates only                                             *08
    AB’C + A’BC’ + AB
    XYZ + XY’Z + X’Y’
26. Prove the following using Boolean identities                                      *05
     A+A’B = A+B
    ( A + B ) ( A + B’ ) ( A’ + C ) =AC
27. Simplify the following Boolean expression using NAND gates only.                  *10
    A’B’C’ + A’B’C’ + B’C’
    ( A + B’ + C ) ( A’ + B’ + C’ ) ( A’ + B )
28. What are Universal gates ? Realize NOT, OR, AND functions using Universal         *06
    Gates.
29. Mention two categories of Boolean expressions based on their structure. Write     *08
    these forms for any three variable expression T ( x,y,z ).
30. Using algebraic procedure realize the Boolean expression                          *06
    F(w,x,y,z) = w z + w z ( x + y )
31. Determine the Minterm canonical formula of the following:                         *04
      T ( x,y,z ) = x y + z + x y z
32. Prove the Demorgan’s law x+y = x . y using Boolean postulates and theorems.       *06
                                                                  1
33. Implement the given Boolean function using NAND gate (A+B )(CD+E).                 08
34. Implement the given Boolean function using NOR gate A(B+CD)+BC1                    08
35. Obtain the minimal sum for the following Boolean function
                                                                                      *08
    F(w,x,y,z) =m(0,1,3,5,7,9,11,14) + d(2, 8 , 10, 12)
36. Simplify the Boolean function F using the don’t care conditions d, in 1. SOP 2.
    POS
                                                                                      *10
    F= A’B’C’ + A’CD + A’BC
    D = ABC + AB’D’
37. Implement the following function with no more than two NOR gates. Assume
    that both normal and complement inputs are available.
                                                                                      *10
    F= A’B’C’+AB’D+A’B’CD’
    D=ABC + AB’D’
38. Using graphical procedure , obtain a nor-gate realization of the Boolean
    expression                                                                        *06
    F(w,x,y,z) = w’z + wz’( x + y’)
39. Prove that if w’x+yz’=0 then
                                                                                      *06
    Wx+y’(w’+z’)= wx +xz +w’z’+w’y’z
40. Prove the following laws using Boolean expression
    Xy+yz+x’z=xy+x’z
    (x+y)(y+z)x’+z) = (x+y)(x’+z)
41. Implement the following function with no more than two nor gates. Assume that
    both normal and complement inputs are available.
                                                                                      10
    F=A’B’C’+AB’D+A’B’CD’
     d=ABC+AB’D’
42. Implement a full subtractor with two half subtractors and an OR gate              10
43. Prove the following consensus laws using Boolean postulates
                  i)     xy+yz+x’z = xy+x’z                                            4
                  ii)    (x+y)(y+z)(x’+z) = (x+y)(x’+z)
44. Prove that if w’x+yz’ = 0 then
                                                                                       6
    Wx+y’(w’+z’) = wx+xz+x’z’+w’y’z
45. Mention the different methods available for manipulating Boolean formulas.
                                                                                      10
    Explain any three in detail
46. Using graphical procedure, obtain a nor-gate realization of the Boolean
                                                                                      6
    expression f(w,x,y,z) = w’z+wz’(x+y’)
47. Show that A B C D =∑m(0,3,5,6,9,10,12,15)                                         4
48. Write short notes on: Implies and subsumes                                        5
49. State and explain with examples shannon’s expansion and reduction theorems in
                                                                                      4
    Boolean algebra
50. Simplify the following using Boolean theorems:
                  i)     f(x,y,z)=(x+y)[(x’(y’+z’)]’ + (xy)’ +(xz)’                   8
                  ii)    f(A,B,C) = (A+B+C)(A’+B+C)(A’+B+C’)
51. Transform each of the following canonical expressions into other canonical form
    in decimal notation and express in simplified form in decimal notation
                                                                                      8
                  i)     f(x,y,z)= =m(0,1,3,4,6,7)
                  ii)    F(w,x,y,z) = ΠM(0,1,2,3,4,6,12)
52. What is don’t care condition? What are its advantages?                            4
53. Obtain a NOR-gate realization of the Boolean function
                  i)     f(w,x,y,z) =m(0,3,5,6,9,10,12,15)                           8

54. Obtain a NAND-gate realization of the Boolean function
                                                                                      8
    f(A,B,C) = (A+B’+C)(A’+B’+C’)(A’+B)
55. Explain the importance of enable input signal                                      6
56. Design and implement full subtractor using NAND gates only                        10
57. What is high speed adder? Design and explain 2 bit carry lookahead adder           8
COMBINATIONAL LOGIC CIRCUITS

Objective: In this chapter we learn about different methods of simplifying Boolean
functions, Postulates of theorems & Boolean algebra. The laws such as
commutative,Associative law,Identity,Inverse & Distributive Laws will be known.
Canonical & standard forms of Boolean functions will be known. Advantage Of using
K-map method for 2,3 & 4 variables, Quine McCluskey method by Determining
Prime implicants (Tabulation method) . Simplification of Product of sums,
Simplification of Boolean function which includes don’t care conditions .

 1. Given the function T (w,x,y,z) = m(1,3,4,5,7,8,9,11,14,15). Use K-Map to             *0
    determine the set of the prime implicants. Indicate the essential prime implicants.    8
    Find three distinct minimal expressions for T.
 2. Determine the set of prime implicants for the given function:-                        *1
    F(v,w,x,y,z) =m(13,15,17,18,19,20,21,23,25,27,29,31)+ Ф (1,2,12,24) and              6
    obtain the minimal expression.
 3. Mention one advantage and one disadvantage of the Quine-McCluskey method              *1
    for obtaining the prime implicants of a given Boolean function. Obtain all the         2
    prime implicants of the function.
    F(v,w,x,y,z) = m(4,5,9,11,12,14,15,27,30) + dc(1,7,25,26,31)
    Use Quine McCluskey method. Do you have any Essential Prime Implicants.
 4. Mention different methods of simplifying Boolean functions                            02
 5. Discuss K-map & Quine McCluskey methods for simplification of Boolean                 02
    expressions
 6. Discuss K-map & Quine McCluskey methods                                               02
 7. Write advantages of K-map over Quine McCluskey method                                 02
 8. Define term Don’t care condition                                                      02
 9. Explain K-map representation in detail & discuss the merits & demerits                *0
                                                                                           6
 10. Explain the tabulation procedure in detail & discuss merits & demerits               *0
                                                                                           6
 11. Compare K-map & Quine-Mcclusky methods for simplification of Boolean                 *0
     Expression                                                                            6
 12. Obtain the simplified expression in sum of products for the following:               06
     i)     F(A,B,C,D,E) = (0,1,4,5,16,17,21,25,29)
     ii)    BDE+B1C1D+CDE+A1B1CE+A1B1C+B1C1D1E1
     iii)   F(x,y,z)= x1z + w1xy1+w(x1y+xy1)
 13. Obtain simplified expression in SOP & POS form                                       06
     i)
            x1z1+y1z1+yz1+xyz ii) w1yz1+vw1z1+vw1x+v1wz+v1w1y1z1
            and draw gate implementation using AND & OR gates
 14. Using K-map simplify following Boolean expression & give implementation of           10
     same using
     i) NAND gates only
     ii) AND,OR & Invert gates for F(A,B,C,D) =(2,4,8,16,31)+ D(0,3,9,12,15,18)
 15. Using K-map obtain Simplified expression in SOP & POS form of function               10
     F(A,B,C,D)=(A1+B1+C1+D1)                (A1+B1+C+D1)               (A+B1+C+D1)
                 1
     (A+B+C+D )(A+B+C+D)
 16. Simplify Boolean function using don’t care condition for SOP & POS                   10
    i)     F=w1(x1y+x1y1+xyz)+x1z1(Y+w), d=w1x(y1z+yz1)+wyz
    ii)    F=ACE+A1CD1E1+A1C1DE, d= DE1+A1D1E+AD1E1
17. Simplify the following Boolean function using K-map method                        14
    i)      xy+x1y1z1+x1yz1
    ii)     x1yz+xy1z+xyz+xyz1
    iii)    F=A1C+A1B+AB1C+BC
    iv)    f (w,x,y,z)= (0,1,2,4,5,6,8,9,12,13,14)
18. Simplify Boolean function by Tabulation method                                    14
    i)     F(A,B,C,D,E,F,G)= (20,28,52,60)
    ii)    F(A,B,C,D,E,F,G)= (20,28,38,39,52,60,102,103,127)
19. Give two simplified irredundant expression for F(w,x,y,z)= (0,4,5,7,8,9,13,15)   *1
                                                                                       4
20. Determine      set   of   Prime     implicants     for   function   F(w,x,y,z)=   *1
    (0,1,2,5,7,8,9,10,13,15)                                                          4
21. Implement following function with NAND & NOR gates.use only four gates            14
    F=w1xz+w1yz+x1yz1+wxy1z, d=wxy+wyz
22. Minimize the following function with don’t care terms using Q.M. method           14
    i)     f(A,B,C,D)= m(5,7,11,12,27,29)+d(14,20,21,22,23)
    ii)    f(A,B,C,D)= m(1,4,6,9,14,17,22,27,28,)+d(12,15,20,30,31)
23. Implement the following function using NAND gates f(X,Y,Z)= (0,6)                14
24. Implement the following function using NOR gates F(x+y1) (x1+y)z1                 14
25. Explain the Tabulation procedure in detail & discuss the merits & demerits        *1
                                                                                       4
26. Determine the set of Prime implicants for function F(w,x,y,z)=                    *1
    (0,1,2,5,7,8,9,10,13,15)                                                          4
27. Find the minimal two level NOR realization for each following function            14
    i)       f(A,B,C)= m(1,4,6,8)
    ii)      f(A,B,C,D,E)= m(3,5,7,12,23,27,28,30)
28. Find the minimal two level NAND realization for each following function           14
    iii)     f(A,B,C)= m(0,2,3,7)
    iv)      f(A,B,C,D,E)= m(4,5,6,7,25,27,29,31)
29. Expand the following function into canonical SOP form f( x1,x2,x3 ) = x1 x3 +     06
    x2 x3 + x1 x2 x3
30. Expand the following function into canonical POS form F( W, X, Q) = ( Q+W’ )      06
     ( X+Q’)
31. With K-map obtain simplified expression in SOP                                    *0
     F (A,B,C,D) = Σ(7,99,10,11,12,13,14,15)                                           8
32. Simplify the following Boolean function using the tabulation method               *1
    F(A,B,C,D)= Σ( 0,1,2,8,10,11,14,15)                                                2
33. Determine the minimal SOP using the tabulation method using only one decimal      *1
    notation                                                                           0
    F(A,B,C,D,E) = Σm(13,15,17,18,19,20,21,23,25,27,29,31)+ Σd(1,2,12,24)
34. Implement using K-map                                                             *1
    F(A,B,C,D) = Σm(0,2,4,6,8,16,18,20,22,24,26,28,30+ΣØ(3,7,11,15,19,23,27,31)        0
35. Using K-map obtain the minimal SOP and the minimal POS form of the function       *0
    f(a, b, c, d) = Σm(1,2,3,5,6,7,8,13)                                               8
36. What code is used to label the row headings and the column headings of a K-map    *0
    and why?                                                                           4
37. Mention one advantage and one disadvantage of the Quine-McClusky method for        *1
    obtaining the prime implicants of a given Boolean function. Obtain all the prime    2
    implicants of the function.
    F(v,w,x,y,z) = Σm(4,5,9,11,12,14,15,27,30)+dc(1,17,25,26,31)
    Use Quine Mc Clusky method. Do you have any essential prime implicants.
38. Using K-map simplify the following Boolean expression and give                     *1
    implementation of the same using the Nand gates only(SOP form) and Nor gates        0
    only(POS form).
    F(A,B,C,D) = Σ (0,1,2,4,5,12,14)+ d(8,10)
39. Explain the procedure for loading a K map using MEV technique. Write the           *1
    MEV K Map for the Boolean function                                                  0
    F(w,x,y,z) = Σm(2,9,10,11,13,14,15)
40. Using K-Maps, determine the minimal sums and the minimal products for              *0
    F(w,x,y,z) = пM(1,4,5,6,11,12,13,14,15)                                             8
    Is the answer unique?
41. Explain the grouping and simplification process in K map using 3-variable and 4    *0
    variable map                                                                        6

42. Using K-map method simplify following Boolean expression and give
    implementation of the same by using NAND and NOR gates only.                       *1
                                                                                        0
       (i)     The SOP form -

               F(a,b,c,d)= Σ (0,1,4,5,6,8,14,12)

       (ii)    The POS expression is given by

              F(a,b,c,d)= π(2,3,6, 7,9,11,15)
43. Minimize the following using K-maps:-                                              *1
       (iii)  The SOP expression is given by: -                                         4

               F(a,b,c,d)= Σ m(0,1,2,3,5,9,14,15)+ΣΦ (4,8,11,12)
       (iv)    The POS expression is given by

                F(a,b,c,d)= πM(0,1,5,8,9,10)
                Implement the minimal expressions thus obtained using basic
                gates(both normal and inverted inputs can be used)
44. List the differences between combinational and sequential logic circuits.          *0
                                                                                        4
45. Determine the set of prime implicates for the given function                       *1
    F(v,w,x,y,z)= Σ m(13,15,17,18,19,20,21,23,25,27,29,31) + ΣΦ (1,2,12,4) and          6
    obtain minimal expression
46. Simplify the given function by tabulation method and list the prime implicants.    *1
    Use decimal notation                                                                0
    F(A,B,C,D)= Σm(0,1,4,5,8,10,11,12,14) + d(2,6)

47. Obtain the minimal sum for the following Boolean function using Tabulation         *1
    method                                                                              4
    F(a,b,c,d,e)= Σm(0,1,3,4,7,9,10,12,15,16,17,20,23,25,28,29,30,31)
48. Using K-map, obtain simplified expression in sum of products                     *0
    F(A, B, C, D)= Σ(7,9,10,11,12,13,14,15)                                           8
49. Simplify the following Boolean function by tabulation method                     *!2
    F(A, B, C, D)= Σ(0,1,2,8,10,11,14,15)
50. Using K-map obtain the minimal sum and the minimal Product for the function      *1
    f(a, b, c, d) = Σm(0,1,3,7,8,12) + dc(5,10,13,14) is your answer unique?          0
51. Using quine Mccluskey method and prime implicant table reductions, determine 10
    the minimal sums for the incomplete Boolean function
    f(v,w,x,y,z)= Σm(4,5,9,11,12,14,15,27,30) + dc(1,17,25,26,31)
52. Explain the procedure for loading a k-map using map entered variable technique. 10
    Write the map entered variable K-map for the Boolean function f(w,x,y,z)=
    Σm(2,9,10,13,14,15)
53. Determine minimal SOP expression for              f(w,x,y,z)= Σm(0,2,4,9,12,15)+ 8
    Σd(1,5,7,10)
54. Using quine Mccluskey method and prime implicant table reductions, determine 8
    the minimal POS expression for the following using decimal notation
    f(v,w,x,y,z)= Σm(1,2,3,5,9,12,14,15) + dc(4,8,11)
55. Reduce the given switching function using variable map technique                  4
    F(A, B, C, D)= Σm(0,1,4,7,10,14)
56. Obtain minimal sum for the following boolean function using tabulation method    14
    f(a,b,c,d,e)=m(0,1,3,4,7,9,10,12,15,16,17,20,23,25,28,29,30,31)
Arithmetic circuits

Objective: To learn about full adder, half adder, half and full subtractor , binary
addition , subtraction, multiplication and division. Also HDL implementation of the
above circuits
1 Discuss the full adder with an example.                                               04
2 Discuss the Half adder with an example.                                               04
3 Explain the code conversion procedure.                                                04
4 Define full adder & half adder, explain the working of it with an example.            06
5 Mention the difference between full and half adder.                                   06
6 Implement the full subtractor with two half adder and OR gate                         08
7 Design a combinational circuit that converts 4-bit reflected code number to a         10
     four bit binary number,implement the circuit with EX-OR gates.
8 Design 2-bit adder circuit using two level NAND gate circuit for each output. the     10
     inputs are 2- bit binary number’s a1a0 & b1b0,the output’s are the 2-bit binary
     sum s1s0 & carry output c1 only.
9 Using only half adder , draw a circuit that will add 3-bits xi, yi and zi together,   10
     producing carry & sum bits Si, Ci as shown in following table:
             xi           yi           zi           Ci           Si

            0            0            0             0              0
            0            0            1             0              1
            0            1            0             0              1
            0            1            1             1              0
            1            0            0             0              1
            1            0            1             1              0
            1            1            0             1              0
            1            1            1             1              1
10 Give the truth table for half adder and full adder, develop the simplified *10
   expression for sum & carry of a full adder & realize the full adder using only
   half adder
11 Design a full adder & full subtractor ,give their truth table,simplified expression *20
   and circuit diagrams
12 Explain the 4-bit parallel adder with the carry look ahead scheme. Clearly *10
   indicate how this scheme improves the performance of the operation.
13 Write short notes on Binary Full Subtractor.                                         *05
14 Implement a full adder circuit with a decoder and two OR gates                       *05
15 Implement a Full subtractor with two half subtractor and an OR gate.                 *10
16 Implement a full adder circuit with a decoder and two OR gates.                      *05
17 Explain a 4-bit parallel adder with carry lookahead scheme.                          10
18 Implement a full adder circuit with a 3-to-8 line decoder and two OR gates           6
19 With a block diagram explain the principle of operation of a carry look ahead        6
   adder
20 Explain a 4-bit parallel adder with carry lookahead scheme                           10
CLOCKS AND TIMING CIRCUITS
Objective: To study clock waveforms, TTL clock, Schmitt trigger, pulse forming
circuits.

FLIPS FL0PS
Objective: The main objective of this chapter is to design sequential circuits( i.e.
circuits which include memory elements). Study of different flip-flops, Master slave
JK flip-flops. Study of different state diagrams & state equations. Also HDL
implementation of flip flop.
 1. Mention the difference between combinational & sequential circuits with block 04
      diagram
 2. Mention the difference between asynchronous & synchronous circuits with 04
      example.
 3. Difference between Latch & Flip flop give example                                   04
 4. Define clocked sequential circuit.                                                  04
 5. Difference between Characteristic & Excitation table.                               04
 6. Clearly distinguish between synchronous & asynchronous circuits, 10*
      Combinational & sequential ckts, Latch & flip-flop
 7. Design mod-3 counter using Jk flip-flops sketch waveforms for outputs when 20*
      clock is      Applied & verify it’s operations.
 8. Show that clocked D flip-flop can be reduced by one gate                            05
 9. Design BCD counter with JK flip flops                                               10
 10. Discuss why condition S=R=1 leads to unstable condition for SR latch construct 10
      state diagram for following table, what is the logic equation for output variable
      Z.

                                0        1

                         A       D/1     B/0
                         B      D/1      C/0
                         C      D/1      A/0
                         D       B/1     C/0
 11. Examine 7476 Jk flip flop, discuss why PRE1 & CLR1 inputs are refereed to as     05
     asynchronous inputs. While JK are called synchronous inputs.

 12. Discuss how unstable condition S=R=1 is avoided in storage latch of the          05
     following
               a) D latch b) JK flip flop c) T flip flop

 13. Give a block diagram of sequential circuit employing register as a part of 08
     sequential circuit.
 14. Design synchronous BCD counter using JK flip flops.                         08
 15. Construct Mod 12 counter using MSI chip.                                    10
 16. Design a serial adder using sequential logic procedure                      10
 17. Explain bi-directional shift register with parallel load                    10
 18. Discuss asynchronous up/down counter & explain presettable counter          10
 19. Explain Schmitt trigger                                                     10
 20. Explain the operation of one shot (Monostable multivibrator)                08
 21. Write short notes on                                                       *12
     a. Schmitt trigger, b. Race around condition c. Johnson counter
 22. Distinguish between level triggering and edge triggering explaining the *05
     advantages.
 23. Write short notes on                                                               *08
     a. Triggering of Flip-Flops, b. Sequence detector
 24. Give the details of a master slave S-R flip flop . Draw the logic diagram. Explain *10

      the flip-flop action during the control signal. Also give the function table.

 25. Design the mod-6 synchronous binary counter having the following repeated              *10

      binary sequence using clocked JK flip flops.

      0,4,2,1,6,0,4,………….

 26. Explain the different types of flip flops along with their truth table. Also explain   *08

      the Race-around condition in a flip-flop.

 27. Using the logic circuit, truth table and the timing diagram explain the operation      *10

      of a J-K flip flop . Show the excitation table and the Characteristic equation.

 28. Design a MOD-12 asynchronous (ripple) up-counter using J-K flip flops.                 *10

      Explain the operation briefly using the timing-diagrams.

  29. Explain the 4-bit binary ripple counter with the state diagram, timing diagram        *10
      and logic diagram using J-K, flip flop that triggers on negative edge.
  30. Using T flip flops design Mod-10 synchronous up counter.                              *12
  31. Explain the operation of clocked JK Flip-Flop with AND and NOR gates with             *10
      relevant characteristics table and equation                                            `
49. Explain the different types of flip flops along with their truth table. Also explain     8
      the race around condition in a flip flop.
 51 With a neat logic diagram and timing waveforms describe the operation of a               6
      master-slave JK flip flop
 52 Using T flip flops design mod-10 synchronous up counter                                 12

				
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posted:9/20/2012
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