Introduction to OFDM and MIMO with emphasis on 802.16

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Introduction to OFDM and MIMO with emphasis on 802.16 Powered By Docstoc
					           WIRELESS COMMUNICATIONS
            From Systems to Silicon


Raghu Rao
Wireless Systems Group,
Xilinx Inc.
                               Agenda
• Introduction to Wireless communications
      – Systems design and considerations
          • The wireless environment
          • Link budget
          • MIMO and OFDM Systems
      – High level view of wireless communication systems
          • Mobile WiMax, an example of wireless comm system,
          • Hardware/software partitioning
          • PHY/MAC etc.
• The Platform FPGA
• Overview of FPGAs and FPGA tools
      – Building DSP sub-systems on FPGAs
      – Digital baseband
• FPGA tools and design methodology

  2
                                                                R. M. Rao, 2008
Communications Roadmap


              • Key markets
              • Core DSP technologies
                 – OFDM
                 – MIMO
              • IP Network is key
              • Enables new
                approaches to
                 – QoS management
                 – Robustness
                 – Capacity
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                            R. M. Rao, 2008
      Wireless Environment
• Multipaths caused by reflections from various
  objects.




 4
                                              R. M. Rao, 2008
       Modeling the Channel
• As the mobile moves through the environment, the
  field strength varies due to :
  – Free space path loss
  – Long term (slow) fading
  – Short term (fast) fading
                                                       short term fading
       Signal Level (dB)




                           path loss
                                                           long term fading

                                       log(distance)
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                                                                              R. M. Rao, 2008
                        Doppler
• Changes in the received carrier frequency due to the
  relative motion of the mobile to the base station


                                         q
                                   D=v. t




• f= fd = (v/l) cos(q)
     – for f=900 MHz, v = 70 MPH (112 km/h)
     – fD-max = v/l = 93.3 Hz

 6
                                                    R. M. Rao, 2008
                        Delay Spread
• Measure of the time distribution of power in the channel
  impulse response
   – Typical office 25 ns to 60 ns
   – Large Lobbies and atria: 100 ns
   – Warehouse and factory floors: 100 ns to 200 ns
   – Delay spreads are up to 10 microseconds in cellular environments
        • Greater than 3 msec in urban areas
        • 0.5 ms in suburban and open areas




    7
                                                              R. M. Rao, 2008
      Exponential Power Delay Profile




• If the delay spread of the channel is larger than the symbol interval
  we will see multiple paths in our channel.
• Leads to inter-symbol interference (ISI).
• Leads to a frequency selective channel.
• Average energy of the channel impulse response follows an
  exponential power-delay profile.
  8
                                                                R. M. Rao, 2008
       Coherence Bandwidth
• Maximum frequency bandwidth for which the signals
  are still considered to be correlated.
• Bc in Hz = 1/(2ptrms) when considering amplitude
  correlation (correlation coefficient = 0.5)
• trms is the rms-delay-spread of the channel




   9
                                              R. M. Rao, 2008
              Coherence Time
• Maximum time period for which the signals are still
  considered to be correlated.
• It is used to characterize the time varying nature of
  the channel.
• Rule of Thumb 9/(16pfm)<Tc<0.423/(fm)
   – fm is the maximum Doppler frequency
   – Correlation coefficient = 0.5


   10
                                                   R. M. Rao, 2008
                  Link Budget
• A link budget is used to compute the range, transmit
  power, receiver sensitivity and other requirements of the
  communication system.
• In free space the path loss is given by the Friis equation :
                         PGt Gr l 2
                     Pr  t 2 2
                          (4p ) d
• Gt , Gr represent transmit and receive antenna gains. Pt ,
  Pr represent the transmit power and receive power.
                                                       l
  is the wavelength, d is the distance.

  11
                                                        R. M. Rao, 2008
                     Link Budget
• Expressing path loss in dB :
                                                        l
      Pr (dB)  Pt (dB)  Gt (dB)  Gr (dB)  20log(      )  ( ).10log(d )
                                                       4p

• Note:  is the path loss exponent depending on the
  environment (2 in free space).
• To compute the SNR at the baseband we need to
  include thermal noise in the signal bandwidth B, and
  noise figure of the system NF.
          Pr (dB)  174dBm / Hz  NF  10 log( B)  SNR

 12
                                                                       R. M. Rao, 2008
                   Link Budget
• Margin for desired outage taking into account receiver
  structure and antenna diversity.
   – Standards specify outage probabilities
   – WiMax – 90% in the cell, 75% at the boundary of the cell.
• Compensation factors for other impairments
   – Interference from neighbouring cell
   – Shadow fading, etc.

• Diversity helps achieve the outage probability (or reduces
  the margin for outage) without increase in transmit power.

  13
                                                             R. M. Rao, 2008
                                               Diversity
• Diversity provides the receiver with multiple looks at the transmitted
  signal.
• Prob(all channels in a fade) << Prob(any 1 channel in a fade)
• Diversity improves link reliability.
                                                                                                    Combined
                                                                                                    channel
                           10
                                                                            Channel 1

                            5
                                                                                                Channel 2
       Signal Level (dB)




                            0




                            -5




                           -10




                           -15




                           -20
                                 0   20   40   60   80    100   120   140    160    180   200


                                                         Time
  14
                                                                                                R. M. Rao, 2008
              Diversity Techniques
• Spatial Diversity
       – Antennas “sufficiently spaced” apart (> ½ wavelength).
       – Will result in an independent channel response and provide another look at the
         transmitted signal.
• Frequency Diversity
       – Transmit over multiple carrier frequencies.
       – If the frequencies are “sufficiently far” (coherence bandwidth) apart the channel
         response will be different on the different frequencies.
• Time Diversity
       – Channel is continuously changing.
       – Transmit signals “sufficiently spaced” (coherence time) apart in time so the 2nd
         transmission “sees” a different channel compared to the first one.
• Polarization Diversity
       – Signals transmitted on two orthogonal polarizations exhibit uncorrelated fading
         statistics.




  15
                                                                                      R. M. Rao, 2008
                     MIMO Systems
•   MIMO systems:
     • Multiple Antennas at the transmitter and
         receiver.                                     Tx Antenna 1                    Rx Antenna 1


•   3 types of MIMO Systems:
     • STBC MIMO systems
          • Diversity gain.
                                                       Tx Antenna 2                    Rx Antenna 2

                                                                      H
     • Spatial Multiplexing MIMO systems
          • Capacity/throughput gain.
     • Feedback MIMO systems
          • Higher performance thru interference
                                                       Tx Antenna M                    Rx Antenna N



              reduction.
•   MISO (multiple input single output) Systems:
     • STBC can be used with just 1 receive antenna.
          • Provides diversity gain.
          • To achieve array gain, need knowledge of
              channel at the transmitter (feedback).
     16
                                                                          R. M. Rao, 2008
                Spatial Multiplexing
• A spatial multiplexing MIMO system transmits different data symbols from each
  transmitter.
• The signals from each transmitter combine over the air and are received by multiple
  receive antennas.
• SM systems have a rate=M (num transmit antennas). The diversity order depends on
  the type of encoding and receiver (uncoded SM with ML decoding has diversity
  order=N (num receive antennas)).


                                                          r1(t) = a11x(t)+a12y(t)+a13z(t)
      x(n)   MODULATOR
                         x(t)
                                                                                    x(n)
                                                                    MIMO
                                                                    MIMO            y(n)
      y(n)   MODULATOR                                             Receiver
                                                                   Receiver
                         y(t)                                                       z(n)


      z(n)   MODULATOR                                 r3(t) = a31x(t)+a32y(t)+a33z(t)
                         z(t)


     17
                                                                                         R. M. Rao, 2008
      Spatial Multiplexing Receivers
  Zero Forcing receiver:                     y1  h11 x1  h12 x2  n1
                                             y2  h21 x1  h22 x2  n2
                  h11
                                              y1   h11     h12   x1   n1 
                                              y   h             x   n 
   Tx Antenna 1               Rx Antenna 1

                    h12
                                              2   21       h22   2   2 
                        h21                    ˆ
                                              x1           y1 
                                             x    W     y 
   Tx Antenna 2
                  h22         Rx Antenna 2
                                              ˆ2          2
                                                                   1
                                               ˆ
                                              x1   h11 h12   y1 
                                              x   h
                                               ˆ2   21 h22   y2 
For ZF receivers W  H 1                                      

Significant increase in noise when the channel is in a deep fade.
       18
                                                                         R. M. Rao, 2008
  Spatial Multiplexing Receivers

• MMSE MIMO Decoders:
  – Cancels interference and minimizes noise.
  – Minimizes the over all error (mean squared error).

                           ˆ  x) 2 ]
                       E[( x

                                           1
                       M     H     M    
             WMMSE          H H    IM  H H
                       Es         SNR 


  19
                                                         R. M. Rao, 2008
    Spatial Multiplexing Receivers
•    Zero-Forcing
•    MMSE
•    Successive Interference cancellation receivers
•    Sphere detectors (sub-optimal Maximum
     Likelihood)




    20
                                                 R. M. Rao, 2008
                      Transmit Diversity
• Space Time Block Code (STBC)
  – 2 Antenna STBC also known as “Alamouti Code”.
  – Improves BER/SER performance.

                                                    h1
                 Constellation
  Information      Mapper         Alamouti ST
    Source                        block code
                                                    h2                   Soft decision for
                                                                                c1
                                                                                             ML Decision




                                                r1  h1c1  h2c2
                                                                    STBC
                r2  h1(c2 )  h2 (c1 )
                          *          *                             Decoder
                                                                                             ML Decision


                       Symbol                     Symbol
                       Period 2                   Period 1
                                                                        Soft decision for
                                                                               c2



  21
                                                                                                R. M. Rao, 2008
                 STBC Decoder
In matrix form the received signal is:
                 r1   h1       h2   c1   n1 
                 r *    h*      *        n* 
                                 h1  c2   2 
                2  2

                         r  Hc  n
                                                         Low complexity decoder.
Decoder:
            c  H H r  H H ( Hc  n)
            ˆ                                            Just 2 complex mults
                                                         per symbol for a 2
                            c1 0   n1                antenna system (and
            c  ( h1  h2 )          n* 
                     2       2
            ˆ                                            grows linearly with block
                             0 c2   2                length/num antennas).

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                                                                      R. M. Rao, 2008
      Other MIMO schemes
• Achieving high rate high diversity MIMO systems
  is an area of active research.
• There are many suboptimal STBC schemes that
  improve the rate but reduce the diversity order.
• There are also combinations of spatial
  multiplexing and STBC schemes.
• One such scheme is 2 (or more) Alamouti’s in
  parallel.

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                                              R. M. Rao, 2008
                  Stacked Alamouti
•   Interference Cancelling STBC
                                                               Constellation
                                                                 Mapper                Alamouti ST
                                                                                       block code


•   2 Alamouti’s in parallel            Information                            Data Stream 1


•   Rate 2 system
                                          Source

                                                               Constellation
                                                                 Mapper                Alamouti ST

•   Diversity order =                                                                  block code




     N*(M-K+1)                                                                  Data Stream 2

                                                           Transmitter for Interference Cancelling STBC
    – K : co-channel users
    – N : transmit antennas per user.                         Interference Cancellation and ML

    – M : receive antennas                            r1
                                                                          Decision                   Data Stream 1




• Requires N*(K-1)+1 antennas
                                                                        C1

                                                      r2


  at the receiver to suppress K-1
                                                                        C2                             Data Stream 2




  interferers.                                             Receiver for Interference Cancelling STBC




    24
                                                                                                       R. M. Rao, 2008
 Orthogonal Frequency Division
      Multiplexing (OFDM)

             Magnitude




                         Frequency




OFDM divides a frequency selective channel into a number
                 of flat fading channels

  25
                                                 R. M. Rao, 2008
           OFDM Modulation
 • A QAM symbol is modulated onto each subcarrier

 • IFFT/FFT are used for efficient modulation and demodulation



         Frequency Domain                             Time Domain
                                                                   D/A
          QAM                               Cyclic
                       S/P     IFFT                        P/S     and
         Mapping                            Prefix
                                                                   RF

                                      (a)
                   Time Domain               Frequency Domain
         RF        Strip
                                                                      QAM
         and       cyclic    S/P      FFT            FEQ     P/S
                                                                    decoding
         A/D       prefix
                                      (b)




26
                                                                               R. M. Rao, 2008
         Combating Multipath
                             OFDM Symbol
             CP

                                           Constructing the cyclic prefix (CP)




      tmax                                      Multipath components
                       Sampling Instant
                  Ts
• Sampling at instant Ts all channels experience
  the same channel and there is no ICI
 27
                                                                  R. M. Rao, 2008
           MIMO and OFDM
• MIMO – Multiple Input Multiple Output
  Communication System. Employs multiple
  antennas at both transmitter and receiver.
• OFDM – Orthogonal Frequency Division
  Multiplexing. Breaks up a broadband channel into
  many parallel narrowband channels (subcarriers).
• MIMO-OFDM – A Combination of MIMO and
  OFDM. Appears like many parallel MIMO systems
  on orthogonal subcarriers.

 28
                                             R. M. Rao, 2008
          MIMO-OFDM System




                                RICH SCATTERING
              OFDM                                    OFDM
          TRANSMITTER 1                           DEMODULATOR 1




                                  ENVIRONMENT




                                                                  MIMO DECODER
              OFDM                                    OFDM
          TRANSMITTER N                           DEMODULATOR N




     Each transmitter is an independent OFDM modulator.

     The source symbols could be space-time block coded or just QAM modulated
     for spatial multiplexing.

     Each receiver is an OFDM demodulator combined with a MIMO decoder to
     invert the channel on each subcarrier and extract the source symbols.


29
                                                                                 R. M. Rao, 2008
                                Agenda
• Introduction to Wireless communications
       – Systems design and considerations
           • The wireless environment
           • Link budget
           • MIMO and OFDM Systems
       – High level view of wireless communication systems
           • Mobile WiMax, an example of wireless comm system,
           • Hardware/software partitioning
           • PHY/MAC etc.
• The Platform FPGA
• Overview of FPGAs and FPGA tools
       – Building DSP sub-systems on FPGAs
       – Digital baseband
• FPGA tools and design methodology

  30
                                                                 R. M. Rao, 2008
                  802.16/802.16e
• The 802.16 WirelessMAN standard includes
  requirements for operation in :
      – Line Of Sight (LOS), 10-66 GHz for fixed wireless systems.
      – Non Line Of Sight (NLOS), <11 GHz for fixed wireless
        systems.


• 802.16e (Mobile WiWax) adds enhancements for mobility
  in the <11 GHz licensed and unlicensed bands.
      – Operation in mobile mode is limited to licensed bands between
        2 GHz and 6 GHz.

 31
                                                               R. M. Rao, 2008
Scalable OFDMA parameters
           Parameters                          Values
     System bandwidth (MHz)     1.25      5               10              20
        FFT size (NFFT)         128      512             1024          2048
Sampling Frequency (Fs, MHz)    1.4      5.6             11.2           22.4
      Sample Time (1/Fs ns)    714.28   178.57           89.28         44.64
       Subcarrier spacing                  10.94 KHz
       Useful Symbol time                      91.4 us
         Guard interval                        11.4 us
      OFDMA symbol time                       102.9 us


32
                                                                 R. M. Rao, 2008
                               Link Budget
                                                   Downlink           Uplink
Transmit Power                                     10 Watts = 40dBm   200 mW = 23dBm
                                                   (max=20 Watts)     (max=200 mW)
Antenna Height                                     32 meters          1.5 meters
Antenna Gain                                       15 dBi (BS)        -1 dBi (mobile)
EIRP                                               55 dBm (approx)    22 dBm
# occupied subcarriers                             840 out of 1024    840 out of 1024
Power/subcarrier                                   28 dBm             3.44 dBm
Noise Figure                                       9 dB (at mobile)   4 dB (at BS)
Total margin for interference, shadow fading, ..   20 dB              20 dB
(75% coverage at cell edge, 90% overall)
BS to BS distance                                  2.8 kms            2.8 kms
SNR Required (Modulation – QPSK 1/8,               -3.31 dB           -2.5 dB
(repetition code = 4)) (BER=10^-6 after FEC)
Rx sensitivity                                     -100.7 dB          -111.1 dB
Max allowable path loss                            136.4 dB           133 dB
   33
                                                                                        R. M. Rao, 2008
         Time Division Duplexing
•        802.16e can be deployed in TDD and FDD environments.
•        Initial certification profiles are only for TDD.
•        The DL subframe and UL subframe lengths are adjustable.
•        TDD assures channel reciprocity.

                   Downlink subframe          Uplink subframe




                                       Adaptive                              RTG : Receive-
                                                                          Transmit transition gap

                                                                  TTG : Transmit-
                                                                Receive transition gap

     Frame (j-2)   Frame (j-1)    Frame (j)       Frame (j+1)    Frame (j+2)

    34
                                                                                   R. M. Rao, 2008
       OFDMA Frame Structure
                                                                                                OFDMA Symbol Number

                                             FC                                                                                                               FC
                                             H                                                                                                                H
                                                                                                                        UL Burst SS1
                                                                                             DL Burst
                                                                   DL Burst SS1
                                                                                              SS4


                                                      UL-MAP
      Subchannel logical number




                                                                                                                        UL Burst SS2
                                                                              DL Burst SS2
                                  Preamble




                                                                                                                                                   Preamble

                                                                                                                                                              DL-MAP
                                             DL-MAP




                                                                                          DL Burst
                                                                                             SS1
                                                                  DL Burst
                                                                                         (From BS2)                      UL Burst SS3
                                                                  Broadcast




                                                                                         DL Burst
                                                                  DL Burst
                                                                                          SS3                            UL Burst SS4
                                                                  Multicast


                                                                                                                       Ranging subchannel


                                                               Downlink (DL) Subframe                                 Uplink (UL) Subframe
                                                                                                        TTG                                  RTG

DL-MAP – Downlink MAP : downlink allocations
UL-MAP – Uplink MAP       : uplink allocations
FCH – Frame control header : contains information about the DL-MAP
 35
                                                                                                                                                              R. M. Rao, 2008
     Data rates for SIMO/MIMO
           configurations
                      64 QAM with 5/6 CTC




Source: WiMax Forum
36
                                            R. M. Rao, 2008
Baseband Transmission Model
                        OFDM             s(t)              r(t)         r(n)    Inner             Outer
      ai,k                                       Channel          ADC
                      Transmitter                                              Receiver          Receiver




                                                               Timing Delay
                               hn,i(t)                            W0(t)     Noise
                                                                             n(t)
                                                                                    T'
                            Resulting
                                                Timing Delay
               s(t)         Channel                                                       r(n)
                                                   d(t-eT')
                              hi(t)


 • OFDM receiver provides estimates of
      –      Channel hn,i(t)
      –      Frequency offset W0
      –      Sample timing T'
      –      OFDM symbol timing
 37
                                                                                                            R. M. Rao, 2008
      Generic OFDM Transmitter

                                         Insert   Append
                                  IFFT                     CFR   DUC DPD DAC   RF          PA
                                         Pilots    CP
           Source
                     Space-Time
           Coding
MAC                   Encoder
            e.g.
                    Beamforming
           LDPC                          Insert   Append
                                  IFFT                     CFR   DUC DPD DAC   RF          PA
                                         Pilots    CP




  • Figure shows a generic MIMO OFDM Tx
           – MIMO not an element of 802.11a, but it is in 802.11n,
             3GPP-LTE and 802.16e


      38
                                                                               R. M. Rao, 2008
      OFDM Receiver Architecture
                                                                                                                          Extract
                                            Symbol Timing                                                                 Pilots


                           Course Freq.                                                          Fine
                                                         CP          Sample                                Fine Freq.    Freq. Domain
      ADC            DDC     Offset                                                   FFT       Sample
                                                       Removal      Clock Adj.                             Offset Adj.     Equalizer
                            Correction                                                         Clock Adj
DAC




                                                        Channel
                                    Extract Preamble   Estimation
             Power
              Est.                                                                                                                           To/From
                                                                       Channel               Medium                                          Network
                                                                     Decoding, e.g.          Access
                                                                        LDPC                Controller




 • Figure illustrates architecture for generic OFDM Rx
 • Details will vary as a function of
           – Packet-based versus broadcast transmission
           – Existance of a preamble (or not) in the waveform
      39
                                                                                                                           R. M. Rao, 2008
                                Agenda
• Introduction to Wireless communications
       – Systems design and considerations
           • The wireless environment
           • Link budget
           • MIMO and OFDM Systems
       – High level view of wireless communication systems
           • Mobile WiMax, an example of wireless comm system,
           • Hardware/software partitioning
           • PHY/MAC etc.
• The Platform FPGA
       – Overview of FPGAs and FPGA tools
       – Building DSP sub-systems on FPGAs
       – Digital baseband
• FPGA tools and design methodology


  40
                                                                 R. M. Rao, 2008
Digital Receiver Architecture:
   Abstracted Architecture
• Common model of abstraction for digital receiver is inner/outer receiver
       Receiver Abstraction

       Digital IF Processing           Inner Receiver                                                Outer Receiver
                                       Ø     Frequency Offset Estimation/Correction
                                       Ø     Sample Clock Offset Correction
        Ø    Up-Conversion             Ø     Channel Estimation/Equalization                         Ø   Channel Coding
        Ø    Down-Conversion           Ø     Frame detection                                             q LDPC
        Ø    Channelizer               Ø     AGC                                                         q TPC
        Ø    Fast AGC                  Ø     Successive Interference Cancellation                        q CTC
                                       Ø     Space-Time-Coding                                           q Viterbi
                                       Ø     IFFT/FFT                                                    q (De-) Interleave
                                       Ø     Per sub-carrier processing
                                               q Beamforming
                                               q QRD-RLS



            Control, Protocol and Link Layer processing
         Ø     Medium Access Control (MAC)       Ø   System Initialization, Control and Monitoring
         Ø     Link Layer Processing             Ø   Application



        Ø     CPRI                                                              Ø   PCI Express
                                             Ø   Ethernet
        Ø     OBSAI                                                             Ø   SRIO


  41
                                                                                                                          R. M. Rao, 2008
   Receiver Abstraction and
Projection on to Platform FPGA
Receiver       Characteristics                   FPGA       Comments                 Receiver Abstraction

Function                                         Platform
Digital IF     Ø MAC Intensive                   SX         Ø DSP48 main
Processing                                                   requirement                   SX                                       LX
                                                                                                            SX/LX
Inner Receiver Ø MAC intensive                   SX/LX      Ø DSP48 leveraged
               Ø Some functions LUT                               FFT
                   intensive                                Ø FPGA fabric for
                      CORDIC in QRD-RLS                          CORDIC
               Ø FFT processing for OFDM                         FFT
               Ø Correlation processing for                                                                  FX
                   timing
               Ø Per-carrier complexity
                   processing (MIMO-OFDM)
                NTX  N RX  Num. Sub-carriers

Outer            Ø Symbol rate tasks             LX         Ø ACS/ACSO dominated      FPGA product portfolio
                                                                                      Tailored for various
Receiver         Ø Channel coding                             by low bit precision
                                                              add/multiplexors

                                                                                      processing Tasks in
                                                                 Good match for
                                                                  fabric
                                                                 Lots of memory

Control/         Ø   Gigabit connectivity        FX
                                                                  required
                                                            Ø Embedded PPC used
                                                                                      communications
Protocol         Ø
                 Ø
                     Linux
                     OS “heavy” tasks
                                                            Ø Rocket IO for
                                                                 PCI Express
                                                                                      receiver
                 Ø   TCP/IP                                      SRIO




      42
                                                                                                                  R. M. Rao, 2008
                 Digital Frontend




Digital upconversion (downconversion)
Crest factor reduction
Digital pre-distortion
  43
                                        R. M. Rao, 2008
 Embedded Software                                          High Performance
                                                               Processing
 MAC (Media Access)
  Decision oriented                                       High MIPs tasks
                                                          Radio PHY
tasks                       DUC,DDC                      Supported by embedded
   CORBA                    CFR,DPD                    DSP tiles, distributed
  RTOS                        RACH                     memory, block memory and
  NBAP




                                        Connectivity
                             Searcher                  logic fabric
  SCA (JTRS radios)         OFDM PHY                     DAC
                                                         DAC
                               TCC                      ADC
                                                        ADC
     Serial Gigabit           MIMO                       EMIF
  OBSAI/CPRI
  Proprietary serial                                      SRIO
backplane
  Inter-chip connectivity
                                                 Logic & IO
                                               OBSAI/CPRI
                                               SRIO
The Platform                                   AD/DA interface
                                               EMIF
          44
                                                                      R. M. Rao, 2008
     Virtex-4/5 FPGA Arhitecture
                                 High-Level View
• FPGA family with 3 members
  tailored for specific classes of
  processing
   – SX: DSP
   – LX: Logic centric
   – FX: Full featured
           • Embedded PowerPC hard IP
           • Giga-bit serial connectivity
           • DSP processing tiles “DSP48”



      45
                                                   R. M. Rao, 2008
               Virtex-5 FPGA Platform


                                                      Can be configured as a
                                                      shift register




• 2 slices per CLB, 4 LUTs per CLB
• Can be configured as a shift
register
• Can be configured as distributed
memory

                                     Can be configured as RAM
        46
                                                                R. M. Rao, 2008
                Virtex-4 DSP48 Slice
                        Scalable 500MHz Performance Not Possible Using
                      Standard Cell Libraries and Standard Cell Design Flow
Pipeline Registers
 Enable 500Mhz
  Performance




                                                          Integrated Cascade
                                                            Routing Enables
                                                         Scalable Performance



 Arithmatica Parallel Counter
                                  Arithmatica A+Adder
 20% Faster Performance and
       Uses Less Area               20% Faster Than
                                 Other Implementations

     47
                                                                  R. M. Rao, 2008
                               Pipelined Multiplier
                                   C                             To Adjacent DSP48 Tile
                                           48
                                                             BCOUT
                                                                                          3 delay latency                                    PCOUT
                                                             18                                                                                         48



                                                                     18                                                       48

                                                                                            18
                                                                                                      36         X
                     MS Word           A                                                    18                       48
                                                18                                                         36                 CIN
                      LS Word          B
                                                                                            72
                                                18                                                         36    Y                                               P
                                                                                                    48               48                                      48



                                                                                                 ZERO 48                      SUB
A                                                                                                                Z   48
     18             z-3        P (PCOUT)
B                         48
     18
                                                                                                                                        48
    36b product sign extended to 48b
                                                             Register
                                                                                                            Wire Shift Right By 17b
                                                     18                                                                                      48
                                                          BCIN                                                                                    PCIN


           48
                                                                                                                                      R. M. Rao, 2008
Pipelined Complex 18x18 MPY
                 S4
            Ai
                      18                                 Pr
            Bi                          48-         48
                      18
                 S3
            Ar
                      18
            Br                          48
                      18
                                              ‘0’
                 S2
            Ar
                      18                                 Pi
            Bi                          48          48
                      18
                 S1
            Ar
                      18
            Bi                    36    48
                      18
                                             ‘0’
      sn = Slice n     Register    Sign Extension


 49
                                                              R. M. Rao, 2008
          Wide Filters At Full Speed
     Within the Virtex-4 DSP Slice Column
 • Systolic N-tap FIR
     – Scalable N-levels deep implementation
     – N-levels deep at 500MHz performance
 • Uses Integrated Pipeline Registers to
   Synchronize Filter Inputs
 • Utilizes Input and Output Cascade Routing

           Build Massively Parallel 512-TAP FIR Filter
                  In a Single Device Achieving
                   256 GMACCs/s Performance

Equivalent Implementation Would Consume
 444 Embedded Multipliers and 77,008 LCs
And Would Only Achieve ½ The Performance

     50
                                                         R. M. Rao, 2008
                               Xilinx FFT IP (4)
     • FFT fully utilizes FPGA arithmetic hardware resources
     • FFT viewed as a recursion using a butterfly kernel

                                                           (  b)
                                     CADD1
                                     CADD2
                           b                           (  b) e-j2pk/N
                                                    CMPY
                                  Phase factors: e-j2pk/N
•   CADD{1|2}: complex adder
•   CMPY: complex multiplier

        51
                                                                          R. M. Rao, 2008
                Virtex-4 DSP Slice
• DSP slice key for
  implementing high-
  performance arithmetic
• Embedded 18x18 MPY
  and 48b adder
   – Butterfly phase rotator
   – Cross-addition




     52
                                     R. M. Rao, 2008
                  Butterfly CMPLX MPY
                                              Pr + jPi = (Ar+jAi) x (Br + jBi)
• Complex MPY used in FFT
                                                                                           Pr
  butterfly
• Optimized to employ Virtex-4           DSP Slice 2
  DSP Slice                         Ar                                  DSP Slice 1
      – 4 and 3 MPY option
                                 Br
•    Complex MPY available as IP Bi
     module†
                                    Ai                                  DSP Slice 4

                                         DSP Slice 3
                                                                                           Pi

    † Available: 6.2i IP Update 2
          53
                                                                         R. M. Rao, 2008
    Performance/Parallelism/Area
• FPGA: highly parallel computing machine
• Achieve performance using functional unit parallelism

• Butterfly array to produce high-
  performance FFT processor
• High computation rate using (possibly)
  hundreds of DSP slices
    – Allocate resources as appropriate to meet
      system requirements
• Large memory bandwidth using multi-
  port memory constructed from BRAMs
 Mem read BW: 320 x 36 x 500e6 = 5.76 Tera-bps

• Area/throughput tradeoff delivered via Xilinx IP library
    54
                                                             R. M. Rao, 2008
                   FFT Architecture
• For small number of carriers and modest data rates single
  butterfly (I)FFT is probably suitable - Small FPGA footprint
                                                    Phase
                      Iteration Engine            Factor ROM
      Input Data
                           Data
                          Ram 0




                                                                   switch
                                         switch
                           Data
                          Ram 1



                                                     Output Data

      55
                                                                            R. M. Rao, 2008
    Block boundary detection/Fine
          timing acquisition
                        1 OFDM block of
                         repeated data                        Half an OFDM block


                               SAMPLES          Z-1   Z-1   Z-1   Z-1       Z-1    Z-1   Z-1   Z-1


                                          ||2
                                                                     KNOWN
                                                                    SEQUENCE
                                      ave
                  Timing Est


                                          ()*   Z-1   Z-1   Z-1   Z-1       Z-1    Z-1   Z-1   Z-1


                    Freq Est
                               arg




F. Tufvesson, O. Edfors, M. Faulkner, “Time and Frequency Synchronization for OFDM
    using PN-Sequence Preambles”, VTC-1999/Fall, vol 4, pp.2203-7, New Jersey, 1999.


    56
                                                                                                     R. M. Rao, 2008
          Fine-timing acquisition using a
                 clipped correlator
      10 time multiplexed
           correlators
                                                                                                                                                                                                                 in0
                                                                                                                                                                                                         out0



                                                                                                                                                                                                                                                                        Full precision correlators :
                                                                                                                                                                                                                 in1

                                                                                                                                                                                                        Register1
                                                                                                    2
                                                                                                   xnz

           1
           xn
           2
                               d

                               addr q
                                sysgen                         a
                                                                                                                                                            1
                                                                                                                                                            a
                                                                                                                                                            2                      sysgen
                                                                                                                                                                                     cast
                                                                                                                                                                                                        a
                                                                                                                                                                                                        bsysgenb
                                                                                                                                                                                                        sub
                                                                                                                                                                                                            a                           d

                                                                                                                                                                                                                                            -1
                                                                                                                                                                                                                                           z q
                                                                                                                                                                                                                                         sysgen                 1
                                                                                                                                                                                                                                                                        32 embedded multipliers
                                                                                                                                                                                                                                                                        896 flipflops
          DAddr                                                                                                                                            coeff                    bc2                 AddSub
                               en                                                                                                                                                                                                                              yn
                                                               coef f                 yn            1                                                       3                        cast
                                                                                                                                                                                   sysgen                                                en
                                    R
                                                                                                   yn                                                       ld                      bc3
           3                   addr-1
                                sysgen
                                  z                            ld




                                                                                                                                                                           1-bit correlator
          CAddr
                                ROM1                                     MAC
           4                                    -1
                                             sysgen
                                               z
           LD                                Delay2




                  Data Addr                              -1
                                                      sysgen                                                                                                                            -1
                                                                                                                                                                                     sysgen
                                                        z                                                                                                                              z
                                                      Delay2                                                                                                                         Delay4
  2               Coef Addr
            BaudClk                         -2
                                         sysgen
                                           z
BaudClk                                  Delay
                        load


                  FSM




  1
  x
                                        xn

                                        DAddr
                                                         yn
                                                                    xn

                                                                    DAddr
                                                                                      yn
                                                                                                    xn

                                                                                                    DAddr
                                                                                                                      yn
                                                                                                                                       xn

                                                                                                                                       DAddr
                                                                                                                                                     yn
                                                                                                                                                                     xn

                                                                                                                                                                     DAddr
                                                                                                                                                                                          yn
                                                                                                                                                                                                            xn

                                                                                                                                                                                                            DAddr
                                                                                                                                                                                                                                 yn
                                                                                                                                                                                                                                              xn

                                                                                                                                                                                                                                              DAddr
                                                                                                                                                                                                                                                              yn
                                                                                                                                                                                                                                                                        Each 1-bit correlator :
                                                                                                                                                                                                                                                                                   10 slices
                                        CAddr                       CAddr                           CAddr                              CAddr                         CAddr                                  CAddr                             CAddr
                                                         xnz                          xnz                             xnz                            xnz                               xnz                                       xnz                          xnz
                                        LD                          LD                              LD                                 LD                            LD                                     LD                                LD

                                                 C1                           C2                                 C3                             C4                             C5                                        C6                             C7


                                                                                        -8
                                                                                     sysgen
                                                                                       zen
                                                                                     Delay1
                                                                                                                                                                                                                                 -1
                                                                                                                                                                                                                              sysgen
                                                                                                                                                                                                                                zen

                                                                                                                                                                                                                                                                        Total for clipped correlator :
                                                                                                                                       a
                                                                                                                                            a+b b
                                                                                                                                               en




                                                                                                                                                                                                                              Delay5
                                                                                                                            AddSub12       -1
                                                                                                                                       sysgen
                                                                                                                                                                                                                 a
                                                                                                                                                                                                                     a+b b
                                                                                                                                                                                                                        en




                                                                                                                                         z
                                                                                                                                                                                                                    -1
                                                                                                                                                                                                                 sysgen




                                                                                                                                                                                                                                                                                   589 slices
                                                                                                                                                                                                 AddSub1
                                                                         a
                                                                             a+b b
                                                                                en




                                                                                                                                                                                                                     z
                                                               AddSub       -1
                                                                         sysgen
                                                                           z
                                                                                                                                 -8
                                                                                                                              sysgen
                                                                                                                                zen
                                                                                                                                                                                                                                             -1
                                                                                                                                                                                                                                         sysgen
                                                                                                                                                                                                                                           z
                                                                                                                                                                                                                                          en
                                                                                                                              Delay3
                                                                                                                                                                                                                                         Delay7
                                                                                                                                                                                                                                                  a
                                                                                                                                                                                                                                                      a+b b
                                                                                                                                                                                                                                                         en
                                                                                                         a
                                                                                                             a+b b
                                                                                                                en




                                                                                                                                                                                                                                                  -1
                                                                                                                                                                                                                                       AddSub2 sysgen
                                                                                              AddSub13      -1
                                                                                                         sysgen                                                                                                                                  z
                                                                                                             z

                                                                                                                                                                                                  -7
                                                                                                                                                                                               sysgen
                                                                                                                                                                                                 zen
                                                                                                                                                                                               Delay6




Bank of correlators
                                                                                                                                                                           a
                                                                                                                                                                               a+b b
                                                                                                                                                                                  en




                                                                                                                                                                 AddSub4        -1
                                                                                                                                                                             sysgen
                                                                                                                                                                               z


                                                                                                                                                                                                                                                                    1
                                                                                                                                                                                                                                                                    y




           57
                                                                                                                                                                                                                                                                                        R. M. Rao, 2008
                       QRD
• One of the popular methods of matrix inversion is
  based on QRD.
      H  QR
      H 1  R 1Q H

• Q is Unitary and R is upper triangular
• A Unitary matrix has a trival inverse, Q  Q
                                        1   H



• An upper triangular matrix can be inverted by
  back-substitution
 58
                                                 R. M. Rao, 2008
               Givens Rotations
• For a 2x1 vector of real numbers
                      c s  a   a 2  b2 
                     s c  b           
                                 0     
                                             
                                  a                       b
                     c                      ,s 
                               a b
                                 2       2
                                                      a 2  b2

• For a NxM matrix, repeat the process 2 cells at a time.
         a11 a12   a13   a11 a12     a13   a11 a12   a13   a11 a12   a13 
                                                                           
        a          a23    a21 a22   a23    0 a22   a23    0 a22   a23 
         21 a22                                                            
         a31 a32
                   a33   0 a32
                                      a33   0 a32
                                                        a33   0    0    a33 
                                                                              


 59
                                                                                    R. M. Rao, 2008
                  Systolic Arrays
• Structured arrays with identical cells. Usually a
  “boundary” cell and an “internal” cell for the QRD
  process.
                   Internal cell
                                   1. The boundary cell generates the
                                      rotations.
                                   2. Internal cell applies the rotations to all
                                      the cells in the row.
  Boundary cell                    3. The systolic array in this figure can
                                      handle any matrix below 3x3.




 60
                                                                     R. M. Rao, 2008
                 Triangularization mode
                                a33
                       a32
                                                                               • For QRD of upto a 3x3
                                a23
                a31    a22
                                                                                 matrix we need 3 boundary
                                a13
                a21    a12
                                                                                 cells and 3 internal cells.
                a11                                                            • Boundary cells calculate
                                                                                 rotation vectors and
                                            The rotation factors for             internal cells store them.
                                            zeroing out cell A(2,1)
                                            are stored in cell                 • Data is fed column-wise
                                            A(1,2), etc.                         into the systolic array.
                                                                               • This may have to be
                                                                                 staggered depending on
                                                                                 the pipelining delays thru
 a11 a12    a13   a11 a12   a13   a11 a12   a13   a11 a12       a13      the boundary cell and
                                                                      
a
 21 a22     a23    0 a22
                              a23    0 a22   a23    0 a22       a23      internal cell.
                                                                        
 a31 a32
            a33   a31 a32
                             a33   0 a32
                                               a33   0             a33 
                                                          0
                                                                           


        61
                                                                                                    R. M. Rao, 2008
Q-matrix computation mode
                1
       0                          s  x * I .s  s * I .c
                0
 0     1                          z  x * I .c*  s * I .s*
                0
 0     0                          c  c;
                                                                                            QH A  R
 1
                                                                                            QH I  QH
                          first column of Q matrix
                          second column of Q matrix
                          third column of Q matrix

1  0       0   c21 s21 0  c31 0 s31   a11 a12              a13   a11 a12
                                                                        
                                                                                    a13 
                                                                                        
0 c       s32    s21 c21 0  0 1 0   a21 a22                    0 a
                                                                  a23              a23 
    32                                                           
                                                                               22
                                                                                        
0  s32
               0
           c32                 s31 0 c31   a31 a32
                          0 1                                 a33   0
                                                                              0    a33 
                                                                                       


                     QH                                       A                R
 62
                                                                                                        R. M. Rao, 2008
                                Agenda
• Introduction to Wireless communications
       – Systems design and considerations
           • The wireless environment
           • Link budget
           • MIMO and OFDM Systems
       – High level view of wireless communication systems
           • Mobile WiMax, an example of wireless comm system,
           • Hardware/software partitioning
           • PHY/MAC etc.
• The Platform FPGA
       – Overview of FPGAs and FPGA tools
       – Building DSP sub-systems on FPGAs
       – Digital baseband
• FPGA tools and design methodology


  63
                                                                 R. M. Rao, 2008
  FPGA Tools for DSP Systems
           Design
• Higher level tools are raising the level of
  abstraction.
• Allows non-hardware engineers (algorithm
  designers) to get a first look at hardware.
• System Generator
      – Simulink to Hardware
• C-to-Gates tools
      – C or “higher” level languages to gates
 64
                                                 R. M. Rao, 2008
             System Generator
                 System Level Modeling & Simulation Framework




HDL


C




Work in the language of your problem
      65
                                                                R. M. Rao, 2008
           System Generator Flow
DSP Development Flow
1. Develop Algorithm &
     System Model

     Simulink MDL                          HDL Simulation Flow


   2. Automatic Code
       Generation


   RTL VHDL & Cores
                                  HDL Test Bench         Test Vectors
3. Xilinx Implementation
           Flow

         Bitstream



   Download to FPGA        FPGA

    66
                                                          R. M. Rao, 2008
                                                            Configurable MIMO-OFDM
                                                                  Transmitter
                                                                                                Pilot insertion and                                                    Time shared                                                                Add Cyclic
                                                                                                   data loading                                                        FFT across                                                               Extension/Block
                                                                                                                                                                         antennas                                                                   Shaping                             1
                                                                                                                                                                                                                                                                                     RealOut1
           double
    1                                                                                                                              RealIn                    double                              double                                                                   double        2
                                                                                                                                                                                                            RealIn                  Fix_16_10
                                                                                                  DataIn                                          RealOut                                xk_re                                                                RealOut1
  DataIn                                                                                                                                                              xn_re                                               RealOut                RealIn                              ImagOut1
                                                                                                                                   ImagIn                                                                                                                                 double
                                                                                                  SampleClk               double                             double                              double                                                      ImagOut1
                                                                                                                RealOut                           ImagOut                               xk_im
                                                                                                                                   SampleClk                                                                ImagIn                                                        double
           double               Bool                                                              Zeroblks                                                                                                                                                    RealOut2                  3
    3                sysgen
                       not                                                                                                                                   double   xn_im                      UFix_6_0                           Fix_16_10
                                         and       double                                                                          Bdata             Start                            xk_index                            ImagOut                ImagIn                   double
                                        sysgen                                                    Preamble                                                                                                                                                   ImagOut2                RealOut2
DataDone             Inverter              -0                                                                                                                                   FFT                         Addr
       Bool                              z                                                                                         rfd                       double                              double
    2                                                                                                                                              Enable                                  rfd                                                                            double        4
                                                                                                  Bdata                                                                                                                                                       RealOut3
                                                                                                                                                                      start                                                         double
DataEnable                             Logical2                                                                           double   Preamble                  Bool                                double                                                                   double     ImagOut2
                                                                                                                                                                                                                        ReadFIFO                 WriteFIFO
                                                                                       double     DataSubc     ImagOut                         DataRequest                                vout              WriteFIFO                                        ImagOut3
                                                                            Zeroblks                                               BFrame                                                                                                                                 double        5
                                                                                                  DataEnable                                                 double                              double                                                       RealOut4
                                                                                                                                            DataSubcarrier            enable             Busy                Add Cyclic Extension                                                    RealOut3
                                                                                                                                   FFTbusy                                                                                                                                double
                                                                                       double                                           Pilot Insertion                                                                                          BaudClk     ImagOut4
                                                                          Preamble                    Packetization                                                            FFT                                                                                                      6
                                        and       Bool                                                and Encoding                    and Data loading
                                       sysgen               SampleClk                                                                                                                                                                                                                ImagOut3
                                          -0                                                                                                                                                                                                     Spatial Demultiplexing
                                        z                                              double
                                                                              Bdata                                                                                                                                                                                                     7
                                       Logical                                                                                                                                                                                                                                       RealOut4
                                                                                       double
                                                                            BFrame                                                                                                                                                                                                      8
                                                                                                                                                                                                                                                                                     ImagOut4
        SampleClk
                      double                                   Packet Controller
                                                                                                       Packetization and                                                                                                  Spatial
 Clock Generator
                                                  Packet                                               configurable STBC                                                                                              Demultiplexing
           BaudClk
                      double
                                                 Controller                                                 encoding                                                                                                 and Interpolation

      Clock
    Generator




             Resource sharing (folding factor)
             Ratio of System clock rate to symbol rate > 8 needed for a 4 transmit antenna system

                      67
                                                                                                                                                                                                                                                                   R. M. Rao, 2008
MIMO Receiver Architecture
                                 Combine
                                   PD
                                                            Block
                                                Block      Boundary
                     Packet
                                               Boundary
                    Detection
                                               Detection

           Rx 1                                                                         Strip     Input                   Output
                                                                                                                  FFT
                                                                                         CP       FIFO                    FIFO


                     Packet
                    Detection


           Rx 2                                                                         Strip     Input                   Output




                                                                      CFO Compensator
                                                                                                                  FFT
                                                                                         CP       FIFO                    FIFO


                                                        CFO                                                                                        MIMO         Soft
                     Packet
                                  Coarse CFO          estimator                                                                                   Decode      Decisions
                    Detection
                                   estimate


           Rx 3                                                                         Strip     Input                   Output
                                                                                                                  FFT
                                                                                         CP       FIFO                    FIFO


                     Packet
                    Detection    Coarse CFO
                                  estimate
           Rx 4                                                                         Strip     Input                   Output
                                                                                                                  FFT
                                                                                         CP       FIFO                    FIFO




                                                                                                Pilot based CFO
                                                                                                    estimator



                                           Preamble
                                                                                                                                                  MIMO
                          Packet                                                                                                    Channel      Decoder
                         Controller                                                                                                 Estimator     FIFO
                                           Payload



                                                                                                                                                   MIMO
                                                                                                                                                  Decoder
                                                                                                                                                   Matrix
                                                                                                                                                (MMSE, etc)
 Samples processed at sample clock rate                                                                                 Samples processed
                                                                                                                        at system clock rate

68
                                                                                                                                                                          R. M. Rao, 2008
          Fine-timing acquisition using a
                 clipped correlator
      10 time multiplexed
           correlators
                                                                                                                                                                                                                 in0
                                                                                                                                                                                                         out0



                                                                                                                                                                                                                                                                        Full precision correlators :
                                                                                                                                                                                                                 in1

                                                                                                                                                                                                        Register1
                                                                                                    2
                                                                                                   xnz

           1
           xn
           2
                               d

                               addr q
                                sysgen                         a
                                                                                                                                                            1
                                                                                                                                                            a
                                                                                                                                                            2                      sysgen
                                                                                                                                                                                     cast
                                                                                                                                                                                                        a
                                                                                                                                                                                                        bsysgenb
                                                                                                                                                                                                        sub
                                                                                                                                                                                                            a                           d

                                                                                                                                                                                                                                            -1
                                                                                                                                                                                                                                           z q
                                                                                                                                                                                                                                         sysgen                 1
                                                                                                                                                                                                                                                                        32 embedded multipliers
                                                                                                                                                                                                                                                                        896 flipflops
          DAddr                                                                                                                                            coeff                    bc2                 AddSub
                               en                                                                                                                                                                                                                              yn
                                                               coef f                 yn            1                                                       3                        cast
                                                                                                                                                                                   sysgen                                                en
                                    R
                                                                                                   yn                                                       ld                      bc3
           3                   addr-1
                                sysgen
                                  z                            ld




                                                                                                                                                                           1-bit correlator
          CAddr
                                ROM1                                     MAC
           4                                    -1
                                             sysgen
                                               z
           LD                                Delay2




                  Data Addr                              -1
                                                      sysgen                                                                                                                            -1
                                                                                                                                                                                     sysgen
                                                        z                                                                                                                              z
                                                      Delay2                                                                                                                         Delay4
  2               Coef Addr
            BaudClk                         -2
                                         sysgen
                                           z
BaudClk                                  Delay
                        load


                  FSM




  1
  x
                                        xn

                                        DAddr
                                                         yn
                                                                    xn

                                                                    DAddr
                                                                                      yn
                                                                                                    xn

                                                                                                    DAddr
                                                                                                                      yn
                                                                                                                                       xn

                                                                                                                                       DAddr
                                                                                                                                                     yn
                                                                                                                                                                     xn

                                                                                                                                                                     DAddr
                                                                                                                                                                                          yn
                                                                                                                                                                                                            xn

                                                                                                                                                                                                            DAddr
                                                                                                                                                                                                                                 yn
                                                                                                                                                                                                                                              xn

                                                                                                                                                                                                                                              DAddr
                                                                                                                                                                                                                                                              yn
                                                                                                                                                                                                                                                                        Each 1-bit correlator :
                                                                                                                                                                                                                                                                                   10 slices
                                        CAddr                       CAddr                           CAddr                              CAddr                         CAddr                                  CAddr                             CAddr
                                                         xnz                          xnz                             xnz                            xnz                               xnz                                       xnz                          xnz
                                        LD                          LD                              LD                                 LD                            LD                                     LD                                LD

                                                 C1                           C2                                 C3                             C4                             C5                                        C6                             C7


                                                                                        -8
                                                                                     sysgen
                                                                                       zen
                                                                                     Delay1
                                                                                                                                                                                                                                 -1
                                                                                                                                                                                                                              sysgen
                                                                                                                                                                                                                                zen

                                                                                                                                                                                                                                                                        Total for clipped correlator :
                                                                                                                                       a
                                                                                                                                            a+b b
                                                                                                                                               en




                                                                                                                                                                                                                              Delay5
                                                                                                                            AddSub12       -1
                                                                                                                                       sysgen
                                                                                                                                                                                                                 a
                                                                                                                                                                                                                     a+b b
                                                                                                                                                                                                                        en




                                                                                                                                         z
                                                                                                                                                                                                                    -1
                                                                                                                                                                                                                 sysgen




                                                                                                                                                                                                                                                                                   589 slices
                                                                                                                                                                                                 AddSub1
                                                                         a
                                                                             a+b b
                                                                                en




                                                                                                                                                                                                                     z
                                                               AddSub       -1
                                                                         sysgen
                                                                           z
                                                                                                                                 -8
                                                                                                                              sysgen
                                                                                                                                zen
                                                                                                                                                                                                                                             -1
                                                                                                                                                                                                                                         sysgen
                                                                                                                                                                                                                                           z
                                                                                                                                                                                                                                          en
                                                                                                                              Delay3
                                                                                                                                                                                                                                         Delay7
                                                                                                                                                                                                                                                  a
                                                                                                                                                                                                                                                      a+b b
                                                                                                                                                                                                                                                         en
                                                                                                         a
                                                                                                             a+b b
                                                                                                                en




                                                                                                                                                                                                                                                  -1
                                                                                                                                                                                                                                       AddSub2 sysgen
                                                                                              AddSub13      -1
                                                                                                         sysgen                                                                                                                                  z
                                                                                                             z

                                                                                                                                                                                                  -7
                                                                                                                                                                                               sysgen
                                                                                                                                                                                                 zen
                                                                                                                                                                                               Delay6




Bank of correlators
                                                                                                                                                                           a
                                                                                                                                                                               a+b b
                                                                                                                                                                                  en




                                                                                                                                                                 AddSub4        -1
                                                                                                                                                                             sysgen
                                                                                                                                                                               z


                                                                                                                                                                                                                                                                    1
                                                                                                                                                                                                                                                                    y




           69
                                                                                                                                                                                                                                                                                        R. M. Rao, 2008
                                              MIMO-OFDM Receiver
                                                                           Packet Detection
  1                                     -1
                                       z        RealIn1
RealIn1                           en
                                                                           PacketDetect                                                                                                                                                                                                                                                                                             9
  2                                   Delay
                                        -1                                                                                                                                                                                                                                                                                                                                  PacketDetect
                                       z
ImagIn1                           en

  3                               Delay1        ImagIn1
                                     -1
                                   z
RealIn2                           en

  4                                Delay2
                                      -1
                                     z
ImagIn2                           en
                                                                                                                                       0




                                                                             Fine Timing Acq                                                                                                           Carrier Frequency
                                                RealIn2                        CFO_Est
  5                               Delay3
                                     -1
                                   z
RealIn3                           en                                                                                        Display2

  6                               Delay4
                                     -1
                                   z
ImagIn3                           en            ImagIn2

  7                               Delay5




                                                                                                                                                                                                       Offset Correction
                                     -1
                                   z
RealIn4                           en
                                                                            PktDetPulse
  8                               Delay6
                                     -1         Baud_clk
                                   z
ImagIn4                           en
                                  Delay7
                                                          MIMO Packet Detect1
  9
 Reset

                                                                                                          a
                                                                                                              a -b




                                                                                                                                                                                                                                                                                                   Output FIFO
                                                                                                          b
                        -1
                    z        Delay8
                                                                                                          AddSub
                                               RealIn

                                                                                   Out2




                                                                                                                     Cyclic prefix
                                                                                                                                                                  0




                                                                                                                                                                                                                                FFT
                                                                                                                                                       Display1

                                               ImagIn
      SampleClk


Clock Generator


          BaudClk                              BaudClk
                                                                              BBDValid
                                                                                                                       removal
     Clock
                                                        Fine T iming Acquisition
   Generator
                                                                                          BlkBounDetect
                                                                                                                                                                                                                             Rxreal1                        Out_real1
                                                                                                               ReadEnable                  WriteFIFO
                                                                                          RealIn1                                                                                                    RxReal1                                                                                                                 Rxreal1
                                                                                                                                                                      RxOut1                                                 Rximag1                       Out_imag1
                                                                                                                                           RxStream1                            RxStream1
                                                                                          ImagIn1
                                                                                                                                                                                                                                                                                                                             Rximag1
                                                                                                                                                                                                    RxImag1
                                                                                                               RxStream1
                                                                                          RealIn2                                          RxStream2                                                                         Rxreal2                        Out_real2
                                                                                                                                                                                                                                                                                                                             Rxreal2
                                                                                                                                                                      RxOut2    RxStream2            RxReal2                                                                                                                                             Out_real1          1
                                                                                          ImagIn2
                                                                                                                                           RxStream3
                                                                                                                                                                                                                             Rximag2                       Out_imag2                                                                                                   SoftDecReal1
                                                                                                                                                                                                                                                                                                                             Rximag2
                                                                                          RealIn3              RxStream2
                                                                                                                                                                                                    RxImag2
                                                                                                                                           RxStream4
                                                                                                                                                                                RxStream3                                    Rxreal3                        Out_real3                                                        Rxreal3
                                                                                          ImagIn3                                                                     RxOut3
                                                                                                                                           Enable                                                    RxReal3
                                                                                          RealIn4                                                                                                                                                                                                                            Rximag3
                                                                                                               RxStream3                                                                                                     Rximag3                       Out_imag3
                                                                                                                                           ReadFIFO                             RxStream4
                                                                                          ImagIn4                                                                                                   RxImag3
                                                                                                                                                                      RxOut4                                                                                                                                                 Rxreal4
                                                                                                                                                                                                                             Rxreal4                        Out_real4
                                                                                                                                                                                                                                                                                                                                                        Out_imag1           2
                                                                                          PacketDetect                                     CFO_est
                                                                                                               RxStream4                                                                             RxReal4                                                                                                                 Rximag4                                   SoftDecImag1
                                                                                                                                                                                FIFO_status_f lag
                                                                                          BaudClk                                                                                                                            Rximag4                       Out_imag4
                                                                                                                                           FFT_Start
                                                                                                                                                            FIFO_status_f lag
                                                                                              Cyclic Prefix Removal                                                                                                                                                                                                          ReadFIFO
                                                                                                                                                                                                    RxImag4
                                                                                                                                           CFO_Valid                                                                         ValidData                      ReadFIFO
                                                                                                                                                                                Enable                                                                                                                                       Addr
                                                                                                                                                       Input Buffer                                  Valid out
                                                                                                                                                                                                                             Addr                             AddrOut
                                                                                                                                                                                                                                                                                                                             wreal_1_1
                                                                                                                                                                                                         Addr
                                                                                                                                                                                CFO_Valid                                                  Output FIFO                                                                                                    v alid_out       10
                                                                                                                                                                                                                                                                                                                             wimag_1_1
                                                                                                                                                                                                                                                                                                                                                                         ValidOut
                                                                                                                                                                                                    FFT_RFD
                                                                                                                                                                                                                                                                                                                             wreal_1_2




                                                                Channel
                                                                                                                                                                                Reset
                                                                                                                                                                                                    FFT_Start
                                                                                                                                                                                                                                                                                                                             wimag_1_2
                                                                                                                                                                                            FFT
                                                                                                                                                                                                                                                                                                                             wreal_1_3

                                                                                                                                                                                                                                                                                                                                                  ReadWeightMatrix




                                                               Estimation
                                                                                                                                                                                                                                                                                                                             wimag_1_3


                                                                                                                                                                                                                                                                                                                             wreal_1_4


                                                                                                                                                                                                                                                                                                                             wimag_1_4


                                                                                                                                                                                                                                                                                                                             wreal_2_1
                                                                                                                                                                                                                                                               Ch_1_1    Ch_tx1rx1
                                                                                                                                                                                                                 Rxreal1
                                                                                                                                                                                                                                                                                                                 wreal_1_1   wimag_2_1                   Out_real2                  3
                                                                                                                                                                                                                                                               Ch_1_2    Ch_tx1rx2
                                                                                                                                                                                                                                                                                                             wimag_1_1                                                     SoftDecReal2
                                                                                                                                                                                                                                                                                                                 wreal_1_2   wreal_2_2
                                                                                                                                                                                                                 Rximag1
                                                                                                                                                                                                                                                               Ch_1_3    Ch_tx1rx3
                                                                                                                                                                                                                                                                                                             wimag_1_2
                                                                                                                                                                                                                                                                                                                 wreal_1_3   wimag_2_2
                                                                                                                                                                                                                                                               Ch_1_4    Ch_tx1rx4
                                                                                                                                                                                                                                                                                                             wimag_1_3
                                                                                                                                                                                                                 Rxreal2
                                                                                                                                                                                                                                                                                                                 wreal_1_4   wreal_2_3
                                                                                                                                                                                                                                                               Ch_2_1    Ch_tx2rx1




                                                  Weight Matrix
                                                                                                                                                                                                                                                                                                             wimag_1_4
                                                                                                                                                                                                                                                                                                                 wreal_2_1   wimag_2_3
                                                                                                                                                                                                                                                                                                                                                        Out_imag2                   4
                                                                                                                                                                                                                                                               Ch_2_2    Ch_tx2rx2
                                                                                                                                                                                                                 Rximag2                                                                                     wimag_2_1
                                                                                                                                                                                                                                                                                                                                                                           SoftDecImag2
                                                                                                                                                                                                                                                                                                                 wreal_2_2   wreal_2_4
                                                                                                                                                                                                                                                               Ch_2_3    Ch_tx2rx3
                                                                                                                                                                                                                                                                                                             wimag_2_2
                                                                                                                                                                                                                                                                                                                 wreal_2_3   wimag_2_4




                                                  Computation
                                                                                                                                                                                                                 Rxreal3
                                                                                                                                                                                                                                                               Ch_2_4    Ch_tx2rx4
                                                                                                                                                                                                                                                                                                             wimag_2_3
                                                                                                                                                                                                                                                                                                                 wreal_2_4   wreal_3_1
                                                                                                                                                                                                                                                               Ch_3_1    Ch_tx3rx1
                                                                                                                                                                                                                                                                                                             wimag_2_4
                                                                                                                                                                                                                 Rximag3
                                                                                                                                                                                                                                                                                                                 wreal_3_1   wimag_3_1
                                                                                                                                                                                                                                                               Ch_3_2    Ch_tx3rx2                                                                       Out_real3                  5
                                                                                                                                                                                                                                                                                                             wimag_3_1
                                                                                                                                                                                                                                                                                                                 wreal_3_2   wreal_3_2                                     SoftDecReal3
                                                                                                                                                                                                                                                               Ch_3_3    Ch_tx3rx3
                                                                                                                                                                                                                 Rxreal4                                                                                     wimag_3_2
                                                                                                                                                                                                                                                                                                                 wreal_3_3   wimag_3_2




                                                                                                                                                                                                                                                                                                                                                                          MIMO Decoder
                                                                                                                                                                                                                                                               Ch_3_4    Ch_tx3rx4
                                                                                                                                                                                                                                                                                                             wimag_3_3
                                                                                                                                                                                                                                                                                                                 wreal_3_4   wreal_3_3
                                                                                                                                                                                                                 Rximag4
                                                                                                                                                                                                                                                               Ch_4_1    Ch_tx4rx1
                                                                                                                                                                                                                                                                                                             wimag_3_4
                                                                                                                                                                                                                                                                                                                 wreal_4_1   wimag_3_3
                                                                                                                                                                                                                                                               Ch_4_2    Ch_tx4rx2
                                                                                                                                                                                                                                                                                                             wimag_4_1                                  Out_imag3                       6
                                                                                                                                                                                                                 ValidData
                                                                                                                                                                                                                                                                                                                 wreal_4_2   wreal_3_4                                       SoftDecImag3
                                                                                                                                                                                                                                                               Ch_4_3    Ch_tx4rx3
                                                                                                                                                                                                                                                                                                             wimag_4_2
                                                                                                                                                                                                                                                                                                                 wreal_4_3   wimag_3_4
                                                                                                                                                                                                                                                               Ch_4_4    Ch_tx4rx4
                                                                                                                                                                                                                 Addr                                                                                        wimag_4_3
                                                                                                                                                                                                                                                                                                                 wreal_4_4   wreal_4_1
                                                                                                                                                                                                                                                              CFO_Est    En
                                                                                                                                                                                                                                                                                                             wimag_4_4
                                                                                                                                                                                                                                                                                                                             wimag_4_1
                                                                                                                                                                                                                 ReadAddr
                                                                                                                                                                                                                                                         CFO_Est_Valid   Addr
                                                                                                                                                                                                                                                                                                                                                         Out_real4                      7
                                                                                                                                                                                                                                                                                     Weight Matrix Computation               wreal_4_2
                                                                                                                                                                                                                                                                                                                                                                                SoftDecReal4
                                                                                                                                                                                                                                    Channel Estimation
                                                                                                                                                                                                                                                                                                                             wimag_4_2


                                                                                                                                                                                                                                                                                                                             wreal_4_3


                                                                                                                                                                                                                                                                                                                             wimag_4_3

                                                                                                                                                                                                                                                                                                                                                        Out_imag4                       8
                                                                                                                                                                                                                                                                                                                             wreal_4_4
                                                                                                                                                                                                                                                                                                                                                                             SoftDecImag4
                                                                                                                                                                                                                                                                                                                             wimag_4_4


                                                                                                                                                                                                                                                                                                                             BaudClk
                                                                                                                                                                                                                                                                                                                                         MIMO Decoder




                                        70
                                                                                                                                                                                                                                                                                                                                                                                  R. M. Rao, 2008
                                                                                               Channel Estimation
                                                                                                                                                                                                                             Channel Estimation Pilots                                                                                                                                                                                                Channel Estimation Pilots
                                                                                                                                                                                                       rst
                                                                                                                                                                                                         sysgen UFix_6_0 UFix_6_0
                                                                                                                                                                                                              out sysgen
                                                                                                                                                                                                                    z
                                                                                                                                                                                                                      -2
                                                                                                                                                                                                                                     for Tx1                                                                                                                                                                                                                  for Tx4
                                                                                                                                                                                                                                                                                                                                                    Enable                                                       Enable
                                                                                                                                                                                                       en                                                                      Enable
                                                                                                                                                                                              double
                                                                                                                                                                   Enable          Pilots                         Delay2                                                                                                                                                      Fix_2_0                                                       Fix_2_0
                                                                                                                                                                                                       Counter1                                                                                          double                                                  Pilot_real                                                   Pilot_real
                                                                                                                                                                                                                                                                                           Pilot_real
                                                                                                      sel
                                                                                                              UFix_6_0                                                                                                                                                                                                                              Reset                                                        Reset
                                                                                                                                                                                                                                                                               Reset
                                                                   Bool          rst                  d0
                                                                                                     sysgen                                                                                                                         sel
                                                                                   sysgen UFix_6_0
                                                                                        out
                                                                                                                                                                   Reset               Addr                                               double
                                                                                                      d1                                                                                                                         d0
                                                                                                                                                                                                                                sysgen                                                                                                              Training Symbols                                             Training Symbols
                                                                        -1       en
                                                                     sysgen Delay6
                                                                       z                                                                                                                                                                                                       Training Symbols
                                                                                                                                                                                                                                    d1                                                                                                                     Tx3                                                          Tx4
                                                                                                     Mux1                                                          Training Symbols                                                                                                   Tx2
                                                                                Counter2
                                                                                                                                                                          Tx1
                    UFix_6_0                    UFix_6_0                                                                                                                                                                            Mux
          10                              -2
                                       sysgen
                                         z
         Addr                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  7
                                       Delay3                                                                                                                                                                                                                                                                                                                                                                                                5                                                               Chreal4
                                                                                                                                                                                                                                                                                  double                                                             double                                                      Fix_16_10                                                    Fix_16_10
                                                                                                                                                                                                                                                     addr             real_out                                          addr             real_out                                        addr        real_out                              Chreal3    addr        real_out                                      8
                                                                                                                            addr                                                                                                                     Pilots1                      double                                Pilots1                      double                              Pilots1                 Fix_16_10                    6       Pilots1                 Fix_16_10                      Chimag4
                                                                                                                                                     Fix_16_10                 Fix_32_20                                                                             imag_out                                                         imag_out                                                      imag_out                                                     imag_out
                   Fix_16_10 -2 Fix_16_10                                                                                                 real_out                  x sysgen
                                                                                                                                                                       0.3535                                                                        Real                                                               Real                                                             Real                                           Chimag3       Real
          1                sysgen
                               z                                                                                            Real
                                                                                                                                                                                                                                                     Imag                         Fix_32_20                             Imag                         Fix_32_20                           Imag                    Fix_32_20                            Imag
    Rxreal1                                    -2     Fix_16_10                                                                                                                                                                                                       Real_in                                                            Real_in                                                     Real_in                                                      Real_in
                                            sysgen
                                              z                                                                             Imag                                     CMult
                           Delay4
                   Fix_16_10                                                                                                                                                                                                                         WE                                                                 WE                                                               WE                                                           WE
                                                                                                                                                                                                                                                                                  Fix_32_20                                                          Fix_32_20                3                                  Fix_32_20
          2                                                                                                                                          Fix_16_10                 Fix_32_20
                                                                                                                            WE                                                                                                                       VDATA            Imag_in                                           VDATA            Imag_in                                         VDATA       Imag_in                                          VDATA       Imag_in
                                            Delay5                                                                                       imag_out                   x sysgen
                                                                                                                                                                       0.3535                                                                                                                                                                                            Chreal2
    Rximag1
                                                                                                                            EN                                                                                                                                                                                                                                              4
                                                                                                                                                                     CMult1                                                                               ChEst Tx1-Rx1                                           1       ChEst Tx2-Rx1                                                    ChEst Tx3-Rx1                                                ChEst Tx4-Rx1
                                                                                                                                                                                                                                                                                                                                                                        Chimag2
                                                                                                                            Single Port RAM                                                                                                                                                                   Chreal1
                                                                                                                                                                                                                                                                                                                  2
                                                                                                                                                                                                                                                                                                             Chimag1
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               double (8)
                                                                                                                                                                                                                                                                               double              9                                                                                                                                                                                                               simout11
                                                                                                                                                                                                                                                                                                                                                       double                                                     Fix_16_10             13                                     Fix_16_10
                                                                                                                                                                                                                                                   addr             real_out
                                                                                                                                                                                                                                                                                                Chreal5                   addr             real_out                                       addr        real_out                                         addr        real_out                15
                                                                                                                            addr                                                                                                                   Pilots1                                                                                                                                                                          Chreal7                                                                    To Workspace2
                                                                                                                                                                                                                                                                               double             10                      Pilots1                                                         Pilots1                                                      Pilots1                        Chreal8
                                                                                                                                                     Fix_16_10                double                                                                              imag_out                                                                             double                                                     Fix_16_10                                                    Fix_16_10
                    Fix_16_10 -2 Fix_16_10                                                                                                real_out                 x sysgen
                                                                                                                                                                      0.3535                                                                       Real                                                                                   imag_out                                                   imag_out                           14                        imag_out
           3                sysgen z                                                                                        Real                                                                                                                                                                Chimag5                   Real                                                            Real                                                         Real
                                                                                                                                                                                                                                                                               double                                                                                                                                                                                                      16
                                                         Fix_16_10                                                                                                                                                                                 Imag                                                                                                double                                                     double           Chimag7
     Rxreal2                                        -2                                                                                                              CMult2                                                                                          Real_in                                               Imag                                                            Imag                                                         Imag
                                                sysgen
                                                  z                                                                         Imag                                                                                                                                                                                                           Real_in                                                    Real_in                                                      Real_in           Chimag8
                            Delay7                                                                                                                                                                                                                 WE
                    Fix_16_10                                                                                                                                                                                                                                                  Fix_32_20                                  WE                                                              WE                                                           WE
                                                                                                                                                                                                                                                                                                                                                       Fix_32_20                  11                              Fix_32_20
           4                                                                                                                WE                       Fix_16_10                Fix_32_20                                                            VDATA            Imag_in
                                                Delay8                                                                                                                                                                                                                                                                    VDATA            Imag_in                                        VDATA       Imag_in                                          VDATA       Imag_in
                                                                                                                                         imag_out                  x sysgen
                                                                                                                                                                      0.3535                                                                                                                                                                                                  Chreal6
     Rximag2                                                                                                                EN
                                                                                                                                                                                                                                                     ChEst Tx1-Rx2
                                                                                                                                                                    CMult3                                                                                                                                                   ChEst Tx2-Rx2                                        12        ChEst Tx3-Rx2                                                ChEst Tx4-Rx2
                                                                                                                            Single Port RAM1                                                                                                                                                                                                                                  Chimag6



                                                                                                                                                                                                                                                                                                                                                                                  19
                                                                                                                                                                                                                                                                                                        17
                                                                                                                                                                                                                                                                                                                                                                              Chreal10                                             21
                                                                                                                                                                                                                                                                                                  Chreal9                                               Fix_16_10                                                 Fix_16_10                                                    Fix_16_10          23
                                                                                                                                                                                                                                                                                   Fix_16_10                               addr             real_out                                      addr        real_out                                         addr        real_out
                                                                                                                                                                                                                                                        addr           real_out                                                                                                   20                                           Chreal11
                                                                                                                                                                                                                                                                                                        18                 Pilots1                                                        Pilots1                                                      Pilots1                                  Chreal12
                                                                                                                            addr                                                                                                                        Pilots1                                                                                         Fix_16_10             Chimag10                            Fix_16_10                                                    Fix_16_10
                                                                                                                                                                                                                                                                                   Fix_16_10                                               imag_out                                                  imag_out                      22                             imag_out
                                                                                                                                                     Fix_16_10                 Fix_32_20                                                                              imag_out                   Chimag9                   Real                                                           Real                                                         Real                                       24
                     Fix_16_10-2         Fix_16_10                                                                                        real_out                  x sysgen
                                                                                                                                                                       0.3535                                                                           Real
              5             sysgen
                              z                                                                                             Real                                                                                                                                                                                                                        Fix_32_20                                                 Fix_32_20 Chimag11
                                                                                                                                                                                                                                                                                   Fix_32_20                               Imag                                                           Imag                                                         Imag                                     Chimag12
                                                      Fix_16_10                                                                                                                                                                                         Imag                                                                                 Real_in                                                  Real_in                                                      Real_in
         Rxreal3                               -2                                                                                                                    CMult4                                                                                             Real_in
                 Fix_16_10                  sysgen
                                              z                                                                             Imag                                                                                                                                                                                           WE                                                             WE                                                           WE
                       Delay9                                                                                                                                                                                                                           WE                                                                                              Fix_32_20                                                 Fix_32_20
            6                                                                                                                                                                                                                                                                      Fix_32_20
                                                                                                                                                     Fix_16_10                 Fix_32_20                                                                                                                                   VDATA            Imag_in                                       VDATA       Imag_in                                          VDATA       Imag_in
                                                                                                                            WE                                                                                                                          VDATA          Imag_in
        Rximag3                             Delay10                                                                                      imag_out                   x sysgen
                                                                                                                                                                       0.3535
                                                                                                                            EN                                                                                                                                                                                                 ChEst Tx2-Rx3                                                ChEst Tx3-Rx3                                                ChEst Tx4-Rx3
                                                                                                                                                                     CMult5                                                                               ChEst Tx1-Rx3
                                                                                                                            Single Port RAM2

                                                                                                                                                                                                                                                                                                         25
                                                                                                                                                                                                                                                                                                                                                                                  27
                                                                                                                                                                                                                                                                                                                                                                                                                                     29
                                                                                                                                                                                                                                                                                                    Chreal13
                                                                                                                                                                                                                                                                                                                                                                              Chreal14
                                                                                                                                                                                                                                                                                                                                                                                                                                 Chreal15
                                                                                                                                                                                                                                                                                    Fix_16_10            26                                                 Fix_16_10                                             Fix_16_10                                                    Fix_16_10               31
                                                                                                                                                                                                                                                                                                                                                                                  28
                                                                                                                                                                                                                                                          addr          real_out                                               addr          real_out                                     addr        real_out                       30                addr        real_out
                                                                                                                                                                                                                                                                                                   Chimag13                                                                                                                                                                                       Chreal16
                                                                                                                            addr                                                                                                                          Pilots1                                                              Pilots1                                        Chimag14    Pilots1                                                      Pilots1
                                                                                                                                                                                                                                                                                    Fix_16_10                                                               Fix_16_10                                             Fix_16_10      Chimag15                                      Fix_16_10
                                                                                                                                                     Fix_16_10                 Fix_32_20                                                                               imag_out                                                             imag_out                                                 imag_out                                                     imag_out                             32
                       Fix_16_10
                               -2        Fix_16_10                                                                                        real_out                  x sysgen
                                                                                                                                                                       0.3535                                                                             Real                                                                 Real                                                       Real                                                         Real
               7            sysgen
                              z                                                                                             Real
                                                                                                                                                                                                                                                          Imag                      Fix_32_20                                  Imag                         Fix_32_20                     Imag                    Fix_32_20                            Imag                                       Chimag16
          Rxreal4                              -2     Fix_16_10                                                                                                                                                                                                          Real_in                                                              Real_in                                                 Real_in                                                      Real_in
                                            sysgen
                                              z                                                                             Imag                                     CMult6
                           Delay11                                                                                                                                                                                                                        WE                                                                   WE                                                         WE                                                           WE
                       Fix_16_10                                                                                                                                                                                                                                                    Fix_32_20                                                               Fix_32_20                                             Fix_32_20
               8                                                                                                            WE                       Fix_16_10                 Fix_32_20                                                                  VDATA         Imag_in                                                VDATA         Imag_in                                      VDATA       Imag_in                                          VDATA       Imag_in
                                            Delay12                                                                                      imag_out                   x sysgen
                                                                                                                                                                       0.3535
         Rximag4                                                                                                            EN
                                                                                                                                                                                                                                                             ChEst Tx1-Rx4                                                        ChEst Tx2-Rx4                                             ChEst Tx3-Rx4                                                ChEst Tx4-Rx4
                                                                                                                                                                     CMult7
                                                                                                                            Single Port RAM3



              double
    9                                             and       Bool
                                                 sysgen
                                                   -2
ValidData                                         z
              double
    11                                           Logical
ChEstPilots


                                                                                                                                                                    -3      Bool
                                                                                                                                                                 sysgen
                                                                                                                                                                   z


                                                                                                                                                                 Delay1
                                                                                                                             ChEstEn
                                                                                                                                          double
                                                                                                              ValidData     ChEstRst
                                                                                                                                          double
                                                                                                                                   En
                                                                                                                                          double
                                                                                                                                   Rst



                                                                                                                                                                                                                                                                                                                                                                                                                                                                   4x4 Channel Estimation
                                                                                                                                          double
                                                                                                              ChEstPilots          En2
                                                                                                                                          double
                                                                                                                          ChEstPilots1
                                                                                                                 ControlSignals



                                                                                                                                                                                                                                                                                                              Input FIFO                                                                                                                                                  Memory

              double
    12
ReadAddr




                                                                                                                                   Control Signals

     71
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                R. M. Rao, 2008
                                                             Packet Detection
                                                                                                                                                          Identical halves of 1 OFDM symbol


Schmidl and Cox algorithm for Packet
   Detection and coarse carrier frequency
   offset estimation.
                                                                                                                                                                                                    C                 c(n)          2
                                                                                                                                                                                                                                                   
                                                                                                                       r(n)                                                                                                                                             m(n)
T. M. Schmidl, D. C. Cox, “Low Overhead Low                                                                                                                            *
     Complexity Synchronization for OFDM”,
     ICC 1996, Vol 3, pp 1301-1306.                                                                                                            Z-D                                                   P                p(n)( )2
                                                                                                                                                                                    *
                                                                                                                                                                                                                                                              2
                                                                                 RealIn1                                                                                                                                                                  CorrMetric
                                                                                                                 Fix_8_0
                                                                                 ImagIn1               RealOut             RealIn              Fix_16_0 RealIn1
            double                 Fix_16_8        Fix_8_0                                                                           RealOut
     1                    force
                        sysgen              cast
                                        sysgen                                              Complex
                                                              sysgen Fix_8_0
                                                                z-32             RealIn2
   RealIn                                                    en                             Multiply                       ImagIn                                    Complex          double
                     Reinterpret1       Convert                                                                                                           ImagIn1             RealOut                                 a
                                                              Delay              ImagIn2                         Fix_8_0                                             Multiply
                                                                                                   ImagOut                                     Fix_16_0
                                                                                 BaudClk                                   BaudClk
                                                                                                                                     ImagOut                                                                                a>b          double
                                                                                                                                                          En                                                               sysgen                             1
                                                                                                                                                                                                                            z-1
                                                                                           Correlate                                                                                                                                                     PacketDetect
                                                                                                                           Complex Sliding                      Power Calculator1
            double                Fix_16_8         Fix_8_0                                                                                                                                                            b
     2                 sysgen
                         force          sysgen
                                            cast                                                                           Window Averager
                                                                       Fix_8_0
   ImagIn                                                       z-32
                                                              sysgen
                     Reinterpret       Convert1              en
                                                                                                                                                                                                                          Relational
                                                             Delay1              RealIn1

                                                                                                                                                                                                                  DecisionMetric = (CorrelationPeak >= 0.5(AveragePower))
            Bool                                                                            Complex         Fix_8_0
     3                                                                           ImagIn1             PwrOut                In                             In1
                                                                                            Multiply
   BaudClk
                                                                                                                                               Fix_16_0                                    Fix_32_0 X >> 1   double
                                                                                                                                         Out                                        Out1           sysgen
                                                                                 BaudClk                                                                                                           z-0
                                                                                                                           BaudClk
                                                                                                                                                          En
                                                                                                                                                                                                    Shift
                                                                                     Power Calculator
                                                                                                                                                                                                                                                              3
                                                                                                                            Sliding Window                                                                                                                AvePower
                                                                                                                                                                    Squarer
                                                                                                                                Averager


         72
                                                                                                                                                                                                                                                     R. M. Rao, 2008
 Two Branch CFO estimation using
      Schmidl and Cox algo
                                                               Y                                     Ye jq

Carrier Frequency Offset causes a linearly increasing rotation in the time domain
               1       [a:b]    reinterpret                        RealIn 1
                                               a
         RealIn 1                                                                          RealOut
                    Slice 2    Reinterpret 4                       ImagIn 1
                                                                                                        RealIn
                                                         -32                    Complex                            RealOut
                                                     z             RealIn 2
                                                   en                           Multiply                ImagIn
                                                                   ImagIn 2
                                                    Delay                                  ImagOut      BaudClk
                                                                   BaudClk                                        ImagOut
                                                                                                        Rst
                                                                        Complex Multiply 2
               2       [a:b]    reinterpret                                                             Complex Sliding                    a
                                               b     z
                                                         -32
         ImagIn 1                                  en                                                   Window Averager                         -1
                    Slice 1    Reinterpret 1                                                                                                   za + b                  1
                                                   Delay 1                                                                                 b                    CorrMetric _real
                                                                     RealIn 1
                                                                     ImagIn 1                                                              AddSub 1
                                                                                Squarer                  In
                                                                     RealIn 2              RealOut
                                                                     ImagIn 2
                                                                                                         BaudClk       Out            -2
                                                                     BaudClk                                                      z
                                                                                                                             en
                                                                       Magnitude -Squared 1              Rst                 Delay 2
                                                                                                                                           a
                                                                                                                                                -1
                                                                                                          Sliding Window                       za + b                     2
                                                                                                              Averager                     b                    CorrMetric _imag

                                                                                                                                           AddSub 2




               3       [a:b]     reinterpret                       RealIn 1
         RealIn 2                                                                          RealOut       RealIn
                    Slice 5     Reinterpret 2                      ImagIn 1
                                                                                                                   RealOut
                                                         -32                    Complex                  ImagIn
                                                     z             RealIn 2
                                                   en                           Multiply
                                                                   ImagIn 2
                                                                                                         BaudClk
                                                   Delay 3                                 ImagOut
                                                                                                                   ImagOut
                                                                   BaudClk
                                                                                                         Rst
                                                                                                                                                                      3
               4       [a:b]      reinterpret            -32            Complex Multiply 3               Complex Sliding                                          AvePwr
                                                     z                                                  Window Averager 1
         ImagIn 2                                  en
                    Slice 3      Reinterpret 3
                                                   Delay 4




                                                                                                                                                        Combine the metric
          5
       BaudClk
                                                                                                                                                        from both Antennas
          6
         Rst




  73
                                                                                                                                                                              R. M. Rao, 2008
         Carrier Frequency Offset
                Estimation
• Pre-FFT
      – Uses a dedicated preamble or symbol for CFO estimation
• Post-FFT using channel estimation pilots
      – Uses channel estimation training symbols
• Post-FFT CFO Tracking
      – Needs continuous pilots during payload symbols
• CFO Estimation using Cyclic Prefix
      – Works well when you have a lengthy cyclic prefix
      – Examples: WiMax, 3GPP-LTE, DVB-T/H
      – Does not need preamble or pilot support

 74
                                                            R. M. Rao, 2008
           Pre-FFT Carrier Frequency Offset
                     Estimation
  7
 BBD                z-14
                  en
  1               Delay5                                                                                                     qˆ
RealIn 1
                                                                                                                             N 
                                                                                                                          2p  s 
   2




                                                                                                                                      Out 1 1
                                                                                                                                                Rising edge




                                                                                                                                          In
ImagIn1
                                                                                                                              2 
                     RealIn 1
                                                                                        x                                                       detector
                                 CorrMetric _ real            In 1              Out 1               mag
                     ImagIn 1
  3
                                                                                            z -17
RealIn 2             RealIn 2
                                CorrMetric _ imag             In 2              Out 2                      x 0 . 003906
                     ImagIn 2                                                           y           atan     -2                cast                d
   4                                                                                                       z
                                                                                                                                                   rstz - 1 q      1
ImagIn2              BaudClk                                                                                                Convert
                                         AvePwr               In 3              Out 3   CORDIC ATAN                                                en           CFO_Est
   5                                                   z-24                                                   CMult8
                     Rst
                                                     en                                                                                           Register1
Baud_clk                   Packet Detection 3                        Truncate
                                                     Delay6
   6
  Rst




     The angle of the correlation metric is
     proportional to the Carrier frequency offset.

     Right size the number of bits before the
     CORDIC operation.

     CORDIC ATAN from the Xilinx Math library
     calculates the angle.

           75
                                                                                                                                                                  R. M. Rao, 2008
       Post-FFT CFO Estimation and
                 tracking
       Location of channel estimation
       training symbols for Antenna 1   Angular rotation         Proportional to
        for a 2 antenna MIMO system
                                                                                   CFO causes a linear
                                         on symbol 1
                                                       q (k )
                                                                     CFO


                                                                                   rotation every sample in
                                                                                   the time domain.
 A subset of channel estimation                            Angular rotation
training symbols is used for CFO                            on symbol 2
           estimation



                                                  mean(q (k ))
                                                                                   CFO causes a constant
                                             e 
                                             ˆ                                     rotation on all subcarriers
                                              c         N
                                                 2p (1  CP )                      in the frequency domain.
                                                         N
                                                           s
                                                                                   This rotation increases
                                                                                   from OFDM symbol to
                                                                                   symbol and can be used
                                                                                   to estimate CFO.


       76
                                                                                                      R. M. Rao, 2008
                                                           Carrier Frequency Offset
                                                                  Correction
            9
                Fix_16_12
                                                                                                                                                                                                                                                        Direct digital synthesizer (DDS) from
                                                                                                                                                                                                                                                        the Xilinx DSP SysGen library.
                                                                                                         Fix_16_16
     CFO_Est                                                                 x 0 . 01563                                                       freq_off                   Fix_16_15
                                                                                                                                                                cos_out

         11                                                                     CMult                                                          Enable
  CFO_Est_valid
                                                                                                                                                                          Fix_16_15 Fix_17_15
                double                                                                                                                                          sin_out      x(- 1 )
         12                                                                                                                                    Reset
        Reset
                                                                                                                                                          DDS               Negate 1


                   Fix_16_10                                                           -1            Fix_16_10
            1                                                                      z                                                                                                            RealIn 1
                                                                                                                                 Fix_16_10                                                                                      Fix_16_10
        RealIn 1                                                                                                    z
                                                                                                                        -1
                                                                                                                                                                                                ImagIn 1              RealOut                  1
                   Fix_16_10                                                    Delay                                                                                                                      Complex                          RealOut 1
            2                                                                                                                                                                                   RealIn 2
                                                                                                                                                                                                           Multiply
        ImagIn 1                                                                                            Delay 1
                                                                                                                                                                                                ImagIn 2                        Fix_16_10
                                                                                                                                                                                                                  ImagOut                      2
                                                                                                                                                                                                BaudClk
                                                                                                                                                                                                                                            ImagOut 1
                                                                                                                                                                                                     Complex Multiply




                   Fix_16_10                                                               -1            Fix_16_10
            3                                                                          z                                                                                                        RealIn 1
                                                                                                                                Fix_16_10                                                                                       Fix_16_10
        RealIn 2                                                                                                z
                                                                                                                    -1
                                                                                                                                                                                                ImagIn 1              RealOut                  3
                   Fix_16_10                                                     Delay 2                                                                                                                   Complex                          RealOut 2
            4                                                                                                                                                                                   RealIn 2
                                                                                                                                                                                                           Multiply
        ImagIn 2                                                                                           Delay 3
                                                                                                                                                                                                ImagIn 2                        Fix_16_10
                                                                                                                                                                                                                  ImagOut                      4
                                                                                                                                                                                                BaudClk
                                                                                                                                                                                                                                            ImagOut 2
                                                                                                                                                                                                    Complex Multiply 1




                   Fix_16_10                                                           -1            Fix_16_10
            5                                                                      z                                                                                                            RealIn 1
                                                                                                                             Fix_16_10                                                                                          Fix_16_10
        RealIn 3                                                                                               -1                                                                               ImagIn 1              RealOut                  5
                                                                                                           z
                   Fix_16_10                                                   Delay 4                                                                                                                     Complex                          RealOut 3
            6                                                                                                                                                                                   RealIn 2
                                                                                                                                                                                                           Multiply
        ImagIn 3                                                                                         Delay 5
                                                                                                                                                                                                ImagIn 2                        Fix_16_10
                                                                                                                                                                                                                  ImagOut                      6
                                                                                                                                                                                                BaudClk
                                                                                                                                                                                                                                            ImagOut 3
                                                                                                                                                                                                    Complex Multiply 2




                   Fix_16_10                                            -1         Fix_16_10
            7                                                       z                                                                                                                           RealIn 1
                                                                                                            Fix_16_10                                                                                                           Fix_16_10
        RealIn 4                                                                                    -1                                                                                          ImagIn 1              RealOut                  7
                                                                                                z
                   Fix_16_10                                   Delay 6                                                                                                                                                                      RealOut 4
            8                                                                                                                                                                                              Complex
                                                                                                                                                                                                RealIn 2
        ImagIn 4                                                                                                                                                                                           Multiply
                                                                                            Delay 7
                                                                                                                                                                                                ImagIn 2                        Fix_16_10
                                                                                                                                                                                 Bool                             ImagOut                      8
                                                                                                                                                                             1                  BaudClk
                                                                                                                                                                                                                                            ImagOut 4
                                                                                                                                                                    Constant 3                      Complex Multiply 3
                                                                                                                               or       Bool
                                                                                                                               z -0

                                                                                                                         Logical 1



                                                        UFix_16_0
                                                    0
                                                                              a a <b            Bool
                                         Constant 1
                                                                                   -0
                                                                              bz

                                                                             Relational
         Bool                     Bool                  UFix_16_0                                                       and           Bool
   10               In1   Out1           rst   out                                                                        -0
                                                                                                                        z
FFT_Start
                                          Counter                             aa < = b                              Logical
                    Rising edge                                                                 Bool
                      detector                                                   -0
                                                                              bz
                                                        UFix_16_0
                                               78                        Relational 1

                                         Constant 2




                          77
                                                                                                                                                                                                                                                                                   R. M. Rao, 2008
 Design methodology issues
• FPGA tools
      – Where to from here?
• C-to-gates
      – Higher level design languages to gates
      – Raising the level of abstraction




 78
                                                 R. M. Rao, 2008
                               End of Roadmap for the
                                Von Neumann Model
 1945-2005               CPUs are as smart as they can be!                                         Spot the CPU!
 Sequential                                                                  Clock L2 $
programming                                                               frequency
               SPECInt92/MHz
                                                                            scaling L1 $

                                                                                       CPU

                                 Source: Ronen [2001]               MHz                        Source: Agarwala [2002]
                                                                                                                          TI 6416
                                                                          With Moore’s law you
                               Multi-core Arrays
                                                            Divide and     also get leakage!
                                                             conquer


 2005 - ????                                                                                                  Absolute
 Concurrent                                                                                                  power limits
                                 Source: Zu & Baas [2006]
programming                    6x6 GALS Processor Array                         Source: Borkar [1999]


    79
                                                                                                             R. M. Rao, 2008
                                               Merging Mindsets:
            Software Design vs. Hardware Design
      class A                   class C


      start()
                                                     Encapsulation
                                                     Abstraction
                                                     Portability
                      class D
                                                     Re-use

                                                    Implementation Detail 
     class B
                                                             Control Logic 
                                                            Interface Glue 
resourceA        resourceB         resourceC                  Concurrency 
                                                          Communication 
                                                Events       Architecture 
                                                Protocols
                                                Ordering
                                                                    Clocks 
                                                Sequential
                                                                   Signals 
                                                 execution
                                                                    Timing 

   Combining the strengths of both paradigms can bring about a radical
     improvement in hardware/software system design productivity.
            80
                                                                               R. M. Rao, 2008
    Objective for a New Methodology:
                    reduce design cost (by a lot)
  • Quality of result (QoR) is not a design goal!
         Ø Performance, power, BOM cost budgets make QoR a design constraint
  • The real objective is to meet the QoR target and minimize:
         Ø Non-recurring engineering costs (NRE)
         Ø Time-to-market (TTM)
  • The new methodology should save on design cost by enabling
         Ø Design of portable, retargetable, composable IP blocks
         Ø Rapid design space exploration and system composition

                               Abstraction                    Traditional HDL Flow
           QoR                   Profit
 performance/$
performance/W                                                 New methodology
                                                     abstraction
                                                        cost
                                                                    Total Design Cost
                                                                    NRE $, TTM

    81
                                                                                 R. M. Rao, 2008
 ‘C’ or higher level language to
              Gates
• There is interest in higher level design
  methodologies, such as C-to-Gates from the
  design community.
• ESL (Electronic system level) tools/design
  methodologies are being explored.
• But, extracting all the concurrency from a
  sequential description is not an easy problem.


 82
                                               R. M. Rao, 2008
Actor/Dataflow Programming Model
      actors       guarded atomic actions          point-to-point, buffered
                                                 token-passing connections


                                   Actions
                                                            encapsulated
                                     State                      state




• A well-known and researched model for concurrent systems
       – Edward Lee et. al. (UC Berkeley)
       – Arvind et. al. (MIT)
• Broadly applicable to heterogeneous HW/SW systems
• Actors are described in the CAL language (UC Berkeley)
       – Open source simulator available from SourceForge
       – Under consideration as reference model for MPEG
 83
                                                                    R. M. Rao, 2008
                Conclusion
• FPGAs are finding wide use in infrastructure
  communication systems and signal processing
  systems.
• FPGA are an efficient choice for exploring VLSI
  architectures.
• FPGA tools are raising the level of abstraction to
  allow algorithm designers the ability to explore
  h/w architectures without learning “h/w design
  tools/languages”.
 84
                                                R. M. Rao, 2008
     Questions?




85
                  R. M. Rao, 2008

				
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