Real-Time Operating Systems by 7sC1UGX

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									           ARM9 Jazelle
• Targetted for ARMx20-type products:
   MMU provides virtual-memory support for OS
    Windows CE, EPOC, and Linux.
• Provide high performance at low cost, as well
  as good power efficiency:
   5.5 times performance
• Even though Jazelle adds a lot of
  functionality to the already existing ARM
  core:
   Only around 20,000 additional gates are needed.
                                                 1
          ARM Modes
• The status bit is located in the code
  program status register (CPSR), the
  register that contains the flags as well
  as some mode bits.
• T=1: Thumb mode
• J=1: Java mode
• T=0,J=0; ARM mode
• T=1,J=1: Illegal
                                        2
                    ARM
• To keep the design clean, simple and fast, the
  original ARM implementation was hardwired
  without microcode.
• RISC features:
• Load/store architecture.
• 16 × 32-bit register file.
• Fixed instruction width of 32 bits to ease
  decoding and pipelining, at the cost of
  decreased code density.
   Later, "Thumb mode" increased code density.
• Mostly single-cycle execution.
                                                  3
ARM Architecture


• Load/store
  architecture
• A large array of
  uniform registers
• Fixed-length 32-
  bit instructions
• 3-address
  instructions
                      4
Processor modes




                  5
                The Registers
• ARM has 37 registers all of which are 32-bits long.
    1 dedicated program counter
    1 dedicated current program status register
    5 dedicated saved program status registers
    30 general purpose registers


• The current processor mode governs which of several banks is accessible.
  Each mode can access
    a particular set of r0-r12 registers
    a particular r13 (the stack pointer, sp) and r14 (the link register, lr)‫‏‬
    the program counter, r15 (pc)‫‏‬
    the current program status register, cpsr


  Privileged modes (except System) can also access
    a particular spsr (saved program status register)‫‏‬
                                                                                 6
          Registers
• Only 16 registers are visible to
  a specific mode.
  A particular set of r0-r12
  r13 (sp, stack pointer)‫‏‬
  r14 (lr, link register)‫‏‬
  r15 (pc, program counter)‫‏‬
  Current program status
   register (cpsr)‫‏‬
                                 7
Register organization




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            Freescale 68HC11
• 68HC11 (6811 or HC11 for short) is an
  8-bit microcontroller (µC) family
  introduced by Motorola in 1985.
    Now produced by Freescale
    Semiconductor,
    Descended from the Motorola 6800
     microprocessor.


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            Freescale 68HC11
• It is a CISC microcontroller.
• 68HC11 devices are more powerful
  and expensive than 68HC08
  microcontrollers,
    Used in barcode readers, hotel card
     key writers, amateur robotics, and
     various other embedded systems
    Different versions of the HC11 have
     different numbers of external ports.
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            Freescale 68HC11
• The most common version has five
  ports
• Freescale 68HC12 is an enhanced 16-
  bit version of the 68HC11.




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         Flash Memory
• A form of EEPROM:
   However, allows a block to be erased or
    written in a single operation (in a flash).
• Floating Gate Avalanche-injection Metal
  Oxide Semiconductor (FAMOS)‫‏‬
• Electrons are trapped in a floating gate.
• Writing a byte requires creating a new
  block:
   Old block is copied along with the byte to be
    written.                                   14
  Flash vs. EEPROM
• EEPROM can write to one location
  or byte at a time:
   Flash writes multiKB blocks.
   As a result flash memory is faster.
   Also flash can be written in-system
    in contrast to EEPROM.
   The control circuitry required for
    erasing is much less leading to higher
    capacity.
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          Flash Memory
• Memory capacity is increased:           cont…
   By reducing the area dedicated to control
    erasing.
• Number of writes is restricted due to
  wear in insulating oxide layer.
• Used to take 12V to write:
   Present generation flash operates at 2.7V.
• Multilevel flash technology:
   With precise multilevel voltage it becomes
    possible to store more than one bit per cell.
                                               17
     Integrated Circuits Costs

IC cost = Die cost + Testing cost + Packaging cost
                   Final test yield

  Final test yield: Fraction of packaged dies which pass the
  final testing state.




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Integrated Circuits
     Capacity




                      21
          Feature Size




Feature size shrinks by 70% per 18 to 24 months   22
Average Transistor Cost Per Year




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  Power Consumption in a Processor
• Power=Dynamic power + Leakage power
• Dynamic power = Number of transistors x
  capacitance x voltage2 x frequency
• Leakage power is rising and will soon match dynamic
  power.
              Pentium   P-Pro      P-II     P-III       P-4
Year          1993        95        97      99          2000
Transistors   3.1M       5.5M      7.5M     9.5M        42M
Clock Speed   60M           200M     300M        500M         1.5G




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              Dynamic Power

                 dyn V if
                 P k i A                  2
                      C
                      i
                           
                           i units
• Dynamic power in CMOS current flows when active
   Transistor switches on
   Combinational logic evaluates new inputs
   Flip-flop, latch captures new value (clock edge)‫‏‬
• Terms
   C: capacitance of circuit
     • wire length, number and size of transistors
   V: supply voltage
   A: activity factor
   f: frequency
• Future: Power dissipation a major factor              28

								
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