# Finite State Machines - I

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```					Sequential Circuit
Synthesis
Virendra Singh
Indian Institute of Science
Bangalore

IEP on Digital System Synthesis
IIT Kanpur
Concept of the State Machine
Computer Hardware = Datapath + Control

Qualifiers
Registers                                       FSM generating sequences
Combinational Functional                            of control signals
Units (e.g., ALU)                            Instructs datapath what to
Buses                                               do next
Control

Control             "Puppeteer who pulls the
strings"
State

Qualifiers                      Control
and                             Signal
Inputs                          Outputs

"Puppet"                 Datapath

Dec 13,2007                    Sequential@iitk                         2

X1
X2

X1    0 1 1 0 0
X2    0 1 1 1 0
--------------------------
Z     1 1 0 1 0
Dec 13,2007                       Sequential@iitk       3
PS   NS,Z
x1x2
A    A,0        A,1      B,0            A,1
B    A,1        B,0      B,1            B,0

11/0
01/1                                                    01/0
00/0              A                                 B   10/0
10/1                                                    11/1
00/1
Dec 13,2007                     Sequential@iitk                4

y   NS                                Z
X1x2   00 01      11     10       X1x2   00 01   11   10
0          0    0      1      0              0   1   0    1

1          0    1     1      0               1   0   1    0

Dec 13,2007                       Sequential@iitk                            5
Memory Elements

R                              Q

Q’
S

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SR FF
Q(t)        S(t)   R(t)      Q(t+1)
0           0      0         0
0           0      1         0
0           1      1         ?
0           1      0         1
1           1      0         1
1           1      1         ?
1           0      1         0
1           0      0         1

RS = 0
Q(t+1) = R’Q(t) + S

Dec 13,2007                 Sequential@iitk   7
SR FF
Excitation Table

Circuit change     Required Input
From       To      S      R

0          0       0           --
0          1       1           0
1          0       0            1
1          1       --           0

Dec 13,2007                Sequential@iitk   8
JK FF
Excitation Table

Circuit change     Required Input
From       To      J     K

0          0       0           --
0          1       1           --
1          0       --           1
1          1       --           0

Dec 13,2007                Sequential@iitk   9
T FF
Excitation Table

Circuit change     Required Input
From       To      T

0          0        0
0          1        1
1          1        0
1           0       1

Dec 13,2007                Sequential@iitk   10
D FF
Excitation Table

Circuit change     Required Input
From       To      T

0           0       0
0           1       1
1           1       1
1           0       0

Dec 13,2007                Sequential@iitk   11

y   NS                                Z
X1x2   00 01      11     10       X1x2   00 01   11   10
0          0    0      1      0              0   1   0    1

1          0    1     1      0               1   0   1    0

Dec 13,2007                       Sequential@iitk                            12

Y = x1x2 + x1y + x2y
Z = x1’x2’y + x1’x2y’ + x1x2’y’ +x1x2y

Dec 13,2007      Sequential@iitk         13
Basic Design Approach

Six Step Process
1. Understand the statement of the Specification

2. Obtain an abstract specification of the FSM

3. Perform a state minimization

4. Perform state assignment

5. Choose FF types to implement FSM state register

6. Implement the FSM

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Basic Design Approach
Example: Vending Machine FSM
General Machine Concept:
 deliver package of gum after 15 cents deposited

 single coin slot for dimes, nickels

 no change
Step 1. Understand the problem               Draw a picture!
Block Diagram
N
Coin           Vending               Gum
Sensor D                     Open
Machine              Release
Res et    FSM                Mechanism

Clk

Dec 13,2007                    Sequential@iitk                        15
Vending Machine Example
Step 2. Map into more suitable abstract representation
Tabulate typical input sequences:
Reset
three nickels                                             S0
nickel, dime
dime, nickel
two dimes                                             N        D
two nickels, dime
S1                 S2

Draw state diagram:
N                                 D
D            N
Inputs: N, D, reset
S3              S4                 S5        S6
Output: open                                    [open]          [open]       [open]
N                D

S7                S8
[open]        [open]

Dec 13,2007                  Sequential@iitk                                      16
Vending Machine Example
Step 3: State Minimization

Reset
Pres ent        Inputs    Next       Output
0¢               State          D N       State       Open
0¢           0   0      0¢          0
N                                0   1      5¢          0
5¢                              1   0      10¢         0
D                       1   1       X          X
N
5¢           0   0      5¢          0
0   1      10¢         0
10¢
1   0      15¢         0
D
1   1       X          X
N, D                 10¢           0   0      10¢         0
15¢                             0   1      15¢         0
[open]                           1   0      15¢         0
1   1       X          X
15¢           X   X      15¢         1
reuse states
whenever
possible                              Symbolic State Table

Dec 13,2007                  Sequential@iitk                                   17
Vending Machine Example
Step 4: State Encoding
Pres ent St at e I nput s              Next S tate   Output
Q1 Q0         D     N                D1 D0         Open
0   0      0     0                 0     0       0
0     1                 0     1       0
1     0                 1     0       0
1     1                  X   X        X
0   1      0     0                 0     1       0
0     1                 1     0       0
1     0                 1     1       0
1     1                 X    X        X
1   0      0     0                 1     0       0
0     1                 1     1       0
1     0                 1     1       0
1     1                 X    X        X
1   1      0     0                 1     1       1
0     1                 1     1       1
1     0                 1     1       1
1     1                 X    X        X

Dec 13,2007                         Sequential@iitk                   18
Vending Machine Example
Step 5. Choose FFs for implementation                          D FF - easiest to use

Q1
D       D1 D        Q    Q1
CLK               \ Q1
Q0                              Q
N                          R

N
\reset                               D1 = Q1 + D + Q0 N
\ Q0                                        OPEN

Q0                                                      D0 = N Q0 + Q0 N + Q1 N + Q1 D
\N
D0 D        Q   Q0
Q1
N
CLK           Q \ Q0                  OPEN = Q1 Q0
R
Q1                 \reset
DDec   13,2007                            8 Gates
Sequential@iitk                         19
Vending Machine Example
Step 5. Choosing FF for Implementation
J-K FF       Pres ent State Inputs     Next State J1      K1   J0 K 0
Q1 Q0       D N         D 1 D0
0     0     0   0         0       0   0   X    0   X
0   1         0       1   0   X    1   X
1   0         1       0   1   X    0   X
1   1         X      X    X   X    X   X
0     1     0   0         0       1   0   X    X   0
0   1         1       0   1   X    X   1
1   0         1       1   1   X    X   0
1   1         X      X    X   X    X   X
1     0     0   0         1       0   X   0    0   X
0   1         1       1   X   0    1   X
1   0         1       1   X   0    1   X
1   1         X      X    X   X    X   X
1     1     0   0         1       1   X   0    X   0
0   1         1       1   X   0    X   0
1   0         1       1   X   0    X   0
1   1         X      X    X   X    X   X
Remapped encoded state transition table

Dec 13,2007                       Sequential@iitk                          20
Vending Machine Example
Implementation:
J1 = D + Q0 N

K1 = 0

J0 = Q0 N + Q1 D

K0 = Q1 N

N
Q0                           J   Q    Q1
D                                    \ Q1
CLK   K RQ
\ Q0

N
OPEN
Q1

D                                      Q0
J   Q
\ Q1            CLK
\ Q0
KR Q
N

\reset                         7 Gates
Dec 13,2007          Sequential@iitk                                            21
Modulo 6 Counter - Specification
• A module 6 counter is a 3-bit counter that counts through
the following sequence:
– 000->001->010->011->100->101->000->…
– 0 -> 1 -> 2 -> 3 -> 4 -> 5 -> 0 …
• It doesn’t use value 6 (110) nor 7 (111)
• It has an input U that controls the counter:
– When U=1 the counter increments its value on the rising edge of
the clock
– When U=0 the counter retains its value on the rising edge of the
clock
• The value of the count is represented as three bit value
(V2V1V0)
• There is an additional output C (Carry) that is 1 when going
from 5 to 0 and 0 otherwise (the C output remains 1 until
the counter goes from 0 to 1)
Dec 13,2007                    Sequential@iitk                           22
Modulo 6 Counter – State table
Present   U Next C V2V1V0
State      State
• For each state examine what
happens for all possible values of
S0      0    S0   1   000         the inputs
S0      1    S1   0   001             – In state S0 input U can be either 0
S1      0    S1   0   001               or 1
– If U=0 the state machine remains in
S1      1    S2   0   010               state S0 and outputs C=1 and
S2      0    S2   0   010               V2V1V0=000
S2      1    S3   0   011             – If U=1 the state machine goes in
state S1, outputs C=1 and
S3      0    S3   0   011               V2V1V0=001
S3      1    S4   0   100       • In the same manner, each state
S4      0    S4   0   100         goes to the next state if U=1 and
S4      1    S5   0   101
remains in the same state if U=0
S5      0    S5   0   101
S5      1    S0   1   000
Dec 13,2007                  Sequential@iitk                          23
Modulo 6 Counter - Mealy state diagram

• The outputs are represented on the arcs as
CV2V1V0
Dec 13,2007           Sequential@iitk          24
Modulo 6 Counter – Moore state diagram

• The outputs are represented adjacent to the state
• The inputs are represented on the arcs
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Assigning State Values

• Each state must be assigned to a unique binary value; for a
machine with n states we have [log2n] bits;
• For the modulo 6 counter example, we have six states. We
will assign state value 000 to S0, 001 to S1, and so on, up to
101 to S5.
Dec 13,2007               Sequential@iitk                    26
Assigning State Values

• Any values can be assigned to the states, some values can be better than
others (in terms of minimizing the logic to create the output and the next
state values)
• This is actually an iterative process: first the designer creates a preliminary
design to generate the outputs and the next states, then modifies the state
values and repeats the process. There is a rule of thumb, that simplifies the
process: whenever possible, the state should be assigned the same with the
output values associated with that state. In this case, same logic can be used
to generate the next state and the output
Dec 13,2007                      Sequential@iitk                           27
Mealy and Moore Machine Implementations
• The current state value is stored into the
register
• The state value together with the machine
inputs, are input to a logic block (CLC)
that generates the next state value and
machine outputs
• The next state is loaded into the register
on the rising edge of the clock signal

Dec 13,2007       Sequential@iitk                        28
Mod 6 Counter – Mealy Implementation

• The logic block (CLC) is
specific to every system and
may consist of combinatorial
logic gates, multiplexers,
lookup ROMs and other
logic components
• The logic block can’t include
any sequential components,
since it must generate its
value in one clock cycle
• The logic block contains two
parts:
– One that generates the outputs
(f function, CLC1)
– One that generates the next
Dec 13,2007              Sequential@iitk     state (g function, CLC2)
29
Mod 6 Counter – Moore Implementation

• The outputs depend only on the present state and not on its inputs
• Its configuration is different than the Mealy machine
– The system output depends only on the present state, so the implementation of the
output logic is done separately
– The next state is obtained from the input and the present state (same as for the Mealy
machine)
Dec 13,2007                        Sequential@iitk                               30
Generating the Next State

• Since the Mealy and Moore machines must
traverse the same states under the same conditions,
their next state logic is identical
• We will present three methods to generate the next
state logic:
– (i) Combinatorial logic gates
– (ii) Using multiplexers
– (iii) Using lookup ROM
• To begin with, we need to setup the truth table for
the next state logic
Dec 13,2007                Sequential@iitk          31
Modulo 6 Counter - Next State Logic
Present       U    Next
State             State
P2P1P0            N2N1N0   • The system inputs and the
000          0    000       present states are the inputs of
000          1    001       the truth table
001          0    001
• Next state bits are the outputs
001          1    010
010          0    010
• We have to construct a
010          1    011       Karnaugh map for each output
011          0    011       bit and obtain its equation
011          1    100     • After that we design the logic to
100          0    100       match the equations
100          1    101
101          0    101
101          1    000
Dec 13,2007                    Sequential@iitk               32
Modulo 6 Counter – Next State Logic

• N2 = P2P0’ + P2U’ +P1P0U
• N1 = P1P0’ + P1U’ + P2’P1’P0U
• N0 = P0’U + P0U’
Dec 13,2007       Sequential@iitk     33
• Modulo 6
Counter –
Next State
implementati
on using
logic gates (i)

Dec 13,2007      Sequential@iitk   34
State Minimization

X-Successor – If an input sequence X takes a
machine from state Si to state Sj, then Sj is said
to be the X-successor of Sj
Strongly connected:- If for every pair of states Si,
Sj of a machine M there exists an input
sequence which takes M from state Si to Sj,
then M is said to be strongly connected

Dec 13,2007          Sequential@iitk             35
State Equivalence

• Two states Si and Sj of machine M are
distinguishable if and only if there exists at least
one finite input sequence which, when applied
to M, causes different output sequences,
depending on whether Si or Sj is the initial state
• The sequence which distinguishes these states
is called a distinguishing sequence of the pair
(Si, Sj)
• If there exists for pair (Si, Sj ) a distinguishing
sequence of length k, the states in (Si, Sj ) are
said to be k-distinguishable

Dec 13,2007           Sequential@iitk              36
State Equivalence
Machine M1

PS                NS, z                   (A, B) – 1 Distinguishable
X=0            X=1             (A, E) – 3 Distinguishable
A         E, 0           D, 1                         Seq - 111
B         F, 0           D, 0
k-equivalent – The states that
C         E, 0           B, 1       are not k-distinguishable are
D         F, 0           B, 0       said to be k-equivalent
E         C, 0           F, 1
F         B, 0           C, 0       Also r-equivalent r<k

Dec 13,2007                     Sequential@iitk                       37
State Equivalence

• States Si and Sj of machine M are said to be
equivalent if and only if, for every possible input
sequence, the same output sequence will be
produced regardless of whether Si or Sj is the
initial state
• States that are k-equivalent for all k < n-1, are
equivalent
• Si = Sj, and Sj=Sk, then Si=Sk

Dec 13,2007           Sequential@iitk             38
State Equivalence

• The set of states of a machine M can be
partitioned into disjoint subsets, known as
equivalence classes
• Two states are in the same equivalence class if
and only if they are euivalent, and are in
different classes if and only if they are
distinguishable
Property: If Si and Sj are equivalent states, their
corresponding X-successors, for all X, are also
equivalent

Dec 13,2007          Sequential@iitk             39
State Minimization Procedure
1.      Partion the states of M into subsets s.t. all states in same subset are
1-equivalent
2.      Two states are 2-equivalent iff they are 1-equivalent and their Ii
successors, for all possible Ii, are also 1-equivalent

P0 = (ABCDEF)
PS                 NS, z
X=0            X=1            P1 = (ACE), (BDF)
A          E, 0           D, 1
B          F, 0           D, 0
P2 = (ACE), (BD), (F)
C          E, 0           B, 1
D          F, 0           B, 0           P3 = (AC), (E), (BD), (F)
E          C, 0           F, 1           P4 = (AC), (E), (BD), (F)
F          B, 0           C, 0
Dec 13,2007                     Sequential@iitk                              40
Machine Equivalence
• Two machines M1, M2 are said to be equivalent if and only if,
for every state in M1, there is corresponding equivalent state in
M2
• If one machine can be obtained from the other by relabeling its
states they are said to be isomorphic to each other

PS                NS, z       δ
X=0            X=1
AC - α        β, 0           γ, 1
E-β          α, 0           δ, 1
BD - γ        δ, 0           γ, 0
F-δ          γ, 0           α, 0
Dec 13,2007                  Sequential@iitk                          41
Example
Machine M2
P0 = (ABCDEFG)
PS                NS, z
X=0            X=1        P1 = (ABCDFG) (E)

A         E, 0           C, 0       P2 = (AF) (BCDG) (E)
B         C, 0           A, 0       P3 = (AF) (BD) (CG) (E)
C         B, 0           G, 0       P4 = (A) (F) (BD) (CG) (E)
D         G, 0           A, 0       P5 = (A) (F) (BD) (CG) (E)
E         F, 1           B, 0
F         E, 0           D, 0
G         D, 0           G, 0
Dec 13,2007                     Sequential@iitk                      42

```
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